Abstract: Systems and methods reduce unwanted effects caused by mismatch in amplifier circuits having components that are trimmable during and post-production to minimize DC offset. Various embodiments of the invention trim out amplifier mismatch by determining trim codes for two or more phases of operation of an amplifier circuit and use those trim codes to determine a final trim code for use in regular operation.

Abstract: There is provided a semiconductor device, which includes a calibration code generator circuit configured to generate a calibration code according to changes in external conditions, a first driver circuit configured to output a data signal with an impedance value controlled by the calibration code, an emphasis control circuit configured to generate an emphasis data signal using the data signal, and to change the calibration code according to an operating frequency to generate an emphasis code; and a second driver circuit configured to output the emphasis data signal with an impedance value controlled by the emphasis code.

Abstract: A chopper amplifier circuit includes a modulator circuit tuned to a chopper frequency, the modulator circuit being configured, in accordance with the chopper frequency, to convert a voltage into an AC voltage; an amplifier circuit having an inverting input and a non-inverting input for the AC voltage, and having an inverting output and a non-inverting output for providing an amplified AC voltage; and a demodulator circuit tuned to the chopper frequency, the demodulator circuit being configured to convert the amplified AC voltage into an amplified DC voltage. The demodulator circuit is configured to, during different switching phases, couple each of the inverting and non-inverting outputs of the amplifier circuit, both directly and capacitively, to each inverting and non-inverting input of a summing circuit.

Abstract: Circuits and methods for sensing output current of a power converter, controlling output current in multiple parallel power converters, and enabling reconfigurability of output control for multiple parallel power converters. One embodiment includes a current sensing circuit configured to be coupled to a power converter, the current sensing circuit configured to receive a first voltage representative of an output current of the power converter and output a low-frequency filtered second voltage based on the first voltage and a high-frequency filtered third voltage based on the first voltage. In some embodiments, the first voltage is generated by sensing an output current of the power converter and converting the sensed output current to the first voltage. Other embodiments include a plurality of power stages and corresponding current sensing circuits, wherein the outputs of the low-frequency filters of the current sensing circuits are coupled in common.

Abstract: A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of the plurality of values having one of four states. The evaluation further includes operation circuitry that receives the plurality of values and the control signals, performs one or more operations of the circuit design with the plurality of values based on the control signals, and outputs operation values based on performing the one or more operations, the operation values indicative of an error within the circuit design.

Abstract: An LED dimming method, a dimming controller and system are disclosed. In a phase where a duty cycle of a PWM signal does not exceed a first threshold, every n periods of the PWM signal is taken as one set, taking a set as an output unit, and the duty cycle of the PWM signal is changed by incrementing or decrementing a average duty cycle by a first predetermined amount ?P1 (0<?P1<0.2%), thereby adjusting an output current of an LED. In this way, the duty cycle of the PWM signal can be configured to increment by the first predetermined amount ?P1 that is smaller than 0.2%. Moreover, when the first threshold is 10%, it can be ensured that each period of the PWM signal with duty cycle value within the range of 0-10% can be identified.

Abstract: A method of operating a circuit includes providing the circuit, the circuit includes an operational amplifier, a plurality of sampling switches, a plurality of holding switches, and a plurality of combined switches. The method further includes: during a first phase, causing the plurality of sampling switches to be closed, the plurality of the holding switches to be open, and the plurality of combined switches to be open; during a second phase, causing the plurality of combined switches to be closed; during a third phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be open; and during a fourth phase, causing the plurality of sampling switches to be open, the plurality of the holding switches to be closed, and the plurality of combined switches to be closed.

Abstract: An amplifying device includes a main amplifier; a first feedback circuit coupled between an input terminal of the main amplifier and an output terminal of the main amplifier; an input coupling circuit coupled between the input terminal of the main amplifier and a first node; and an amplifying feedback circuit coupled between the output terminal of the main amplifier and the first node, wherein the first feedback circuit and the amplifying feedback circuit are negative feedback circuits.

Abstract: Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.

Abstract: Amplifying circuitry configured such that when a detection circuit detects an abnormal state in which the level of signals input to a main amplifying circuit exceeds a normal range, a control circuit sets the state of integration of signals in the integration circuit to a default state. When the detection circuit detects the abnormal state and then detects that an operating state returns to a normal state in which the level of signals input to the main amplifying circuit is included in the normal range, the control circuit cancels the setting of the default state in the integration circuit.

Abstract: In examples of a chopper operational amplifier, a current control circuit comprises a pair of voltage sources, each of which may be varied to generate a voltage signal of a particular value, and multiple inverters, each of which is configured to receive either a clock signal or its complement signal and one of the voltage signals. Based on these inputs, each inverter generates a control signal that is delivered to a corresponding switch in the input stage of the chopper operational amplifier to control the gate voltage of that switch. Based on the difference between the values of the voltage signals, the current control circuit operates to reduce the amplitudes of base currents induced by charge injection at the input terminals of the chopper operational amplifier.

Abstract: A pulse width modulation (PWM) circuit, a method for PWM, and an electronic device are provided. In the PWM circuit, a control word providing circuit can generate, based on an obtained target duty cycle, two target frequency control words with a ratio of the target duty cycle, and output the two target frequency control words to a pulse generation circuit, wherein a ratio of the first target frequency control word to the second target frequency control word is the target duty cycle; and the pulse generation circuit can output a target pulse signal with the target duty cycle under the control of the two target frequency control words.

Abstract: Systems and methods are provided for which a chopper modulator and a chopper demodulator of a chopped apparatus having a variable chopper frequency are described. A feedback path is used to reduce ripples and/or remaining offsets as a result of the variable chopper frequency.

Abstract: A power detector includes a detection circuit and a bias circuit. The detection circuit is used to receive an input signal and output a power indication signal. The bias circuit includes a first impedance unit, a second impedance unit and a transistor. The transistor includes a first terminal and a control terminal coupled to the first impedance unit, and a second terminal. The second impedance unit is coupled between the first terminal of the transistor and an output terminal of the bias circuit, or between the second terminal of the transistor and a second terminal of the bias circuit. The output terminal of the bias circuit is coupled to an input terminal of the detection circuit, and is used to output a bias signal.

Abstract: An ADC includes a plurality of sub ADCs configured to operate in a time-interleaved manner and a sampling circuit configured to receive an analog input signal of the ADC, wherein the sampling circuit is common to all sub ADCs. The ADC includes a test signal generation circuit configured to generate a test signal for calibration of the ADC. The sampling circuit has a first input configured to receive the analog input signal and a second input configured to receive the test signal. The sampling circuit includes an amplifier circuit and a first feedback switch connected between an output of the amplifier circuit and an input of the amplifier circuit. The first feedback switch is configured to be closed during a first clock phase and open during a second clock phase, which is non-overlapping with the first clock phase.

Abstract: Chopper amplifiers with multiple sensing points for correcting input offset are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected in a cascade along a signal path. The chopper amplifier further incudes a multi-point sensed offset correction circuit that generates an input offset compensation signal based on sensing a signal level of the signal path at multiple signal points. Furthermore, the multi-point sensed offset correction circuit injects the input offset compensation signal into the signal path to thereby compensate for input offset voltage of the amplification circuit while suppressing output chopping ripple from arising.

Abstract: In one embodiment, the electronic circuit includes a first amplifying circuit configured to generate a first compensation voltage based on a first reference voltage and an output voltage. The output voltage is from a functional circuit bloc. A second amplifying circuit is configured to generate a control voltage based on an input voltage, a second reference voltage and the first compensation voltage. The second reference voltage is different than the first reference voltage.

Abstract: A sigma-delta analog-to-digital converter includes: a subtractor for subtracting a feedback signal from an analog input signal; a loop filter for processing the output signal from the subtractor to generate a filtered signal; a signal comparing circuit for selectively operating in an offset detection mode or a signal comparison mode, wherein the signal comparing circuit generates an error signal irrelevant to the relative magnitude between the filtered signal and a reference signal in the offset detection mode, and generates a comparison signal corresponding to the relative magnitude between the filtered signal and the reference signal in the signal comparison mode; an offset calibration control circuit for calibrating the offset of the signal comparing circuit and for controlling the signal comparing circuit to alternately switch between the offset detection mode and the signal comparison mode; and a digital-to-analog converter for generating the feedback signal according to the comparison signal.

Abstract: An input current (Iin) is transformed into an output integrated voltage (Vout_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (Tclk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (Tclk_DAC).

Abstract: A semiconductor device includes a signal input circuit configured to select one of the plurality of differential sensor signals according to a channel selection signal; an amplifier circuit configured to amplify an output of the signal input circuit; and an analog-to-digital converter (ADC) configured to convert an output of the amplifier circuit into a digital value, wherein each of the plurality of sensor signals is a differential signals and the signal input circuit changes polarity of an output signal thereof according to a first chopping signal, and wherein the ADC includes a delta-sigma modulator configured to generate a bit stream from an output of the amplifier circuit; an output chopping circuit configured to adjust phase of the bit stream according to the first chopping signal; and a filter configured to filter an output of the output chopping circuit and to output the digital value.

Abstract: A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.

Abstract: A feedback stage for an integrator circuit is provided. The integrator receives a first input current and a second input current that include respective measurement current components and an offset current component. The integrator integrates the first input current and the second input current and generates a first output voltage and a second output voltage. The feedback stage including a transconductance amplifier detects a difference between the first output voltage and the second output voltage and sinks or sources a first output current and a second output current based on the difference between the first output voltage and the second output voltage. The first output current is additively combined with the first input current and the second output current is additively combined with the second input current to mitigate the offset current component at an input of the integrator.

Abstract: A high dynamic range sensing front-end for bio-signal recording systems in accordance with embodiments of the invention are disclosed. In one embodiment, a bio-signal amplifier includes an input signal, where the input signal is modulated to a predetermined chopping frequency, a first amplifier stage, a parallel-RC circuit connected to the first amplifier stage and configured to generate a parallel-RC circuit output by selectively blocking an offset current, a second amplifier stage connected to the parallel-RC circuit that includes a second input configured to receive the parallel-RC circuit output and generate a second output that is an amplified version of the input signal with ripple-rejection. Further, the bio-signal amplifier can also include an auxiliary path configured for boosting input impedance by pre-charging at least one input capacitor. In addition, the bio-signal amplifier can also include a DC-servo feedback loop that includes an integrator that utilizes a duty-cycled resistor.

Abstract: An amplifier including a first routing circuit, an input stage circuit, an output stage circuit, a second routing circuit, and a bias voltage generating circuit is provided. The bias voltage generating circuit generates a first bias voltage and a second bias voltage for respectively supplying a first tail current source and a second tail current source of the input stage circuit. During a first period, the first bias voltage is related to the voltage at a first input terminal of the amplifier, and the second bias voltage is related to the voltage at a second input terminal of the amplifier. During a second period, the first bias voltage is related to the voltage at the second input terminal of the amplifier, and the second bias voltage is related to the voltage at the first input terminal of the amplifier.

Abstract: A gradient amplifier includes N working half-bridge groups. In each of the working half-bridge groups, a first working half-bridge includes a first switch and a second switch, and a second working half-bridge includes a third switch and a fourth switch. An emitter of the first switch is coupled with a collector of the second switch at a first coupling point, and an emitter of the third switch is coupled with a collector of the fourth switch at a second coupling point. A gradient coil is coupled between the first coupling point and the second coupling point in each of the working half-bridge groups, and a current flowing through the gradient coil is a sum of currents flowing through the N working half-bridge groups.

Abstract: An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.

Abstract: A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.

Abstract: A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.

Abstract: Provided is a differential amplification device reduced in DC offset voltage. The amplification device amplifies an input signal, and includes a chopper switch circuit which switches the polarity of the input signal between a normal phase and a reverse phase and outputs the input signal, a V-I conversion circuit which is connected to the chopper switch circuit, a capacitance circuit which is connected to the V-I conversion circuit to store electric charges supplied from the V-I conversion circuit, and an amplification circuit which is connected to the V-I conversion circuit to switch the polarity of an input signal between the normal phase and the reverse phase and amplify the input signal.

Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of Operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.

Abstract: According to an example, discrete-time analog filtering may include receiving an input signal, and sampling the input signal to determine sampled input signal values related to the input signal.

Abstract: A device includes a current source and sampling units. Each of the sampling units includes a transistor and a capacitor electrically coupled to a gate of the transistor. The sampling units are sequentially activated such that the capacitor samples a voltage of a column line of a pixel array and are activated together such that the transistor is turned on according to the sampled voltage of the capacitor, to drain a current from the current source through an output node to generate an output voltage thereat.

Abstract: A method of estimating a junction temperature of a converter for a vehicle includes: calculating, by a vehicle controller, an IGBT power loss value of the converter using an input current and an input voltage between a battery and the converter, an output voltage output from the converter to an inverter, and a duty ratio and an IGBT characteristic value of the converter.

Abstract: A semiconductor circuit comprising an input block having a first chopper providing a chopped voltage signal, a first transconductance converting said chopped voltage signal into a chopped current signal, a second chopper providing a demodulated current signal, a current integrator having an integrating capacitor providing a continuous-time signal, a first feedback path comprising: a sample-and-hold block and a first feedback block, the first feedback path providing a proportional feedback signal upstream of the current integrator. The amplification factor is at least 2. Charge stored on the integrating capacitor at the beginning of a sample period is linearly removed during one single sampling period. Each chopper operates at a chopping frequency. The sample-and-hold-block operates at a sampling frequency equal to an integer times the chopping frequency.

Abstract: Provided are an amplifier circuit capable of reducing DC offset voltage without an increase in chip area and degradation in frequency characteristics, and a multipath nested miller amplifier circuit. The amplifier circuit includes a chopper switching circuit, a sampling circuit configured to sample an output signal from the chopper switching circuit, and a holding circuit configured to hold a signal output from the sampling circuit.

Abstract: An audio amplifier includes an operational amplifier, a replica of an output stage of the operational amplifier, and a feedback circuit configured such that, in a normal mode, an output signal of the operational amplifier is fed back to the input side of the operational amplifier, and such that, in a calibration mode, an output signal of the replica is fed back to the input side of the operational amplifier. The calibration circuit cancels out the offset voltage of the audio amplifier. An adjustment circuit changes the offset of the audio amplifier according to a control signal S1. A control circuit adjusts the control signal such that an output signal VS of the replica is within a predetermined target range in a state in which a predetermined voltage is input to the audio amplifier. Memory stores the control signal S2 acquired in the final stage.

Abstract: An electrical circuit comprising a modulating chopper configured to receive a differential input signal at a first frequency and modulate the differential input signal to a second frequency to form a modulated differential signal, a null amplifier coupled to the modulating chopper and configured to amplify the modulated differential signal to form an amplifier output, wherein amplifying the modulated differential signal causes a ripple in the amplifier output, a demodulating chopper coupled to the null amplifier and configured to demodulate the amplifier output to form a demodulated differential signal having a first portion at the first frequency and a second portion at a third frequency, an integrator coupled to the demodulating chopper and configured to integrate the demodulated differential signal to form an integrated differential signal, and an attenuator coupled to the integrator and configured to attenuate the integrated differential signal to compensate for at least part of the ripple.

Abstract: In a case in which an input offset voltage of a main amplification circuit deviates from a predetermined range, a retaining operation of retaining an output voltage of a low pass filter in a sample and hold circuit stops, and an output voltage of the low pass filter is directly output to a correction signal supply circuit. As a result, for example, negative feedback control is not temporarily performed due to influence or the like of an excessive input voltage on the main amplification circuit, and in a case in which the input offset voltage of the main amplification circuit deviates from the predetermined range, a response delay due to the retaining operation of the sample and hold circuit does not occur, and the response speed of an offset correction circuit increases.

Abstract: Disclosed is a switch control circuit, including an error amplifier, a compensation network and a control circuit, wherein the compensation network is connected to an output end of the error amplifier; and the control circuit includes switches from a first switch to a fifth switch and is configured to control operating states of the error amplifier and the compensation network by controlling on/off states of switches from the first switch to the fifth switch. Further disclosed are switch control method, a regulator including the above switch control circuit as well as a computer storage medium.

Abstract: Aspects of the disclosure provide an amplifier system and a method for dynamically cancelling an offset voltage. The amplifier system includes a chopper amplifier system that includes a differential amplifier with an offset calibration circuit. The chopper amplifier system is configured to generate an output signal including voltage variations indicating an offset voltage of the differential amplifier. The amplifier system also includes a feedback circuit configured to determine a polarity of the offset voltage of the differential amplifier based on the output signal, and to transmit a control signal to the offset calibration circuit to reduce the offset voltage of the differential amplifier.

Abstract: A main amplifier generates an output signal SOUT according to a difference between first and second voltages VP and VN. A first gm amplifier is arranged as a differential input stage. A second, fully differential, gm amplifier amplifies a voltage difference between its non-inverting and inverting input terminals, and outputs a differential current signal I3N/I3P via its inverting and non-inverting output terminals. An integrator integrates a differential input current I4P/I4N input via its non-inverting and inverting input terminals, and samples and holds the signal every predetermined period, to generate a differential voltage signal. A first selector is arranged as an upstream stage of the second gm amplifier, and outputs the differential input signal without change or otherwise after swapping. A second selector is arranged as a downstream stage of the second gm amplifier, and outputs the signal I3N/I3P output from the second gm amplifier without change or otherwise after swapping.

Abstract: A charging control system for charging a secondary battery from a solar battery, including a first path for transmitting power from the solar battery to the secondary battery, a second path for sensing the voltage of the secondary battery, and a comparison unit for comparing the solar battery voltage with the sensed voltage of the secondary battery. The first path includes a first interrupter, controlled by the comparison unit, which interrupts the first path to prevent discharge of the secondary battery through the solar battery when the solar battery voltage falls below the secondary battery voltage. The second path includes a second interrupter that interrupts the second path after the first path is interrupted, to prevent the secondary battery from discharging through the second path when not being charged through the first path.

Abstract: A radio frequency (RF) receiver device may include a receive path including a first amplifier. The device also includes a first mixer coupled to an output of the first amplifier and to an input of a second amplifier. Further, the device may include an auxiliary path including a second mixer coupled between an output of the first mixer and an input of the first mixer.

Abstract: A measuring device, measuring arrangement and a method for determining a measured quantity. The measuring device a sensor device, an evaluation device and an interface. The sensor device generates measurement information which is dependent on the measured quantity and the evaluation device determines a result value for the measured quantity. To devise a measuring device which manages with a limited power demand and storage demand and which also allows a complex evaluation for obtaining the result value for the measured quantity, the evaluation device of the measuring device outputs the measurement information or information dependent on it via the interface to a separate data device of the measuring arrangement, receives intermediate information from the data device which is generated depending on the measurement information or the information dependent on it and determines the result value based on the intermediate information.

Abstract: A fully differential class-D amplifier having a controlled common-mode output voltage is disclosed. The differential class-D amplifier may include a correction circuit to determine the common-mode output voltage associated with differential pulse width modulated output signals and to generate differential correction signals to control the common-mode output voltage. In some exemplary embodiments, the differential class-D amplifier may include a plurality of gain stages to generate the differential PWM output signals. The differential correction signals may be provided to at least one stage of the differential class-D amplifier.

Abstract: A random chopper control circuit is disclosed. The random chopper control circuit is coupled to an operational amplifier. The random chopper control circuit includes a random generator. The random generator is configured to generate a random chopper control signal and output the random chopper control signal to the operational amplifier to control an operation of the operational amplifier.

Abstract: A notch filter is controlled synchronously with a chopper to filter out chopping ripple. In one embodiment, the notch filter is coupled to the differential output of the chopper and includes a sampling capacitor, a hold capacitor, and a second set of switches between the sampling capacitor and the hold capacitor. The second set of switches is temporarily closed once per chopper switching cycle to transfer charge from the sampling capacitor to the hold capacitor such that the ripple from the chopper is not transferred to the hold capacitor. The voltage across the hold capacitor may be coupled to any other circuit, such as to the differential inputs of an amplifier.

Abstract: Switched capacitor circuits and charge transfer methods comprising a sampling phase and a transfer phase. Circuits and methods are implemented via a plurality of switches, a set of at least two capacitors, at least one voltage amplifier, and an operational amplifier. In one example, during the sampling phase at least one input voltage is sampled, and during the transfer phase at least a first reference voltage provided by the at least one voltage amplifier is subtracted from the at least one input voltage using the operational amplifier. The same set of at least two capacitors may be used in both the sampling phase and the transfer phase.

Abstract: A notch filter is controlled synchronously with a chopper to filter out chopping ripple. In one embodiment, the notch filter is coupled to the differential output of the chopper and includes a sampling capacitor, a hold capacitor, and a second set of switches between the sampling capacitor and the hold capacitor. The second set of switches is temporarily closed once per chopper switching cycle to transfer charge from the sampling capacitor to the hold capacitor such that the ripple from the chopper is not transferred to the hold capacitor. The voltage across the hold capacitor may be coupled to any other circuit, such as to the differential inputs of an amplifier.