Abstract: A common operational amplifier for a pipeline circuit is provided. The common operational amplifier is used by the stage circuits of the pipeline circuit by turns according to a predetermined timing. The common operational amplifier comprises an operational amplifier circuit, a multiplexer circuit and a demultiplexer circuit. The multiplexer circuit is provided for selecting a signal set of a stage circuit to be amplified to couple to the operational amplifier circuit, and the demultiplexer circuit is provided for transmitting the amplified signal set to the corresponding stage circuit.

Abstract: A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

Abstract: A chopper comparator includes an input voltage conversion circuit, a reference voltage input circuit and a comparison amplifier. The input voltage conversion circuit is applied to an input voltage. The input voltage conversion circuit converts the input voltage to a converted input voltage that is lower than a first voltage. The reference voltage input circuit provides a reference voltage. The comparison amplifier compares a voltage of the converted input voltage with the reference voltage and amplifies a result of the comparison. The comparison amplifier includes an inverter having a withstand voltage substantially equal to the first voltage.

Abstract: An amplifier (AMP) is provided with a pair of choppers (CHPi,CHPo) in order to reduce the DC-offset and the noise produced by the amplifier (AMP). To obtain an optimal noise reduction the pair of choppers (CHPi,CHPo) operate on a high frequency. As a result the DC-offset cancellation is not optimal because a so-called charge injection of the switches in the pair of choppers (CHPi,CHPo) produces a DC-offset. To overcome this problem the amplifier (AMP) is further provided with further offset cancellation means which are for example formed by a further pair of choppers (CHPfi,CHPfo). This further pair of choppers (CHPfi,CHPfo) operates on a relatively low frequency. The combination of the pair of choppers (CHPi,CHPo) and the further pair of choppers (CHPfi,CHPfo) guarantees an optimal DC-offset cancellation as well as an optimal noise cancellation.

Abstract: A switching regulator circuit is arranged to provide a constant current to a load. The switching regulator circuit is operated in discontinuous current mode such that an inductor stores energy in a first part of an oscillation cycle, and discharges in a second part of the cycle. The trigger mechanism for the oscillator is disabled when the charged inductor couples energy to the load, and enabled after the inductor is detected as discharged. The energy stored in the inductor is proportional to the square of the on-time associated with switching regulator. Constant voltage load devices such as LEDs for a display can be driven by the switching regulator in an open-loop mode such that the current in the load devices is a linear function of the on-time.

Abstract: A method for reducing offset voltage in an operational amplifier without the need for switched-capacitors, includes introducing a tapped resistor chain between the common connected terminals of the transistors of the input differential pair of the operational amplifier and connecting the tail current source/sink of the differential amplifier to a selected tap of the resistor chain. The invention further provides an improved operational amplifier in accordance with the above method.

Abstract: In the hold phase, two negative feedback circuits constituted by the negative feedback capacitors 6p and 6m and two positive feedback circuits constituted by positive feedback capacitors are provided between an input terminal and an output terminal of an operational amplifier. Here, in a sampling phase before a hold phase, charges according an input signal V1p is stored in each of the capacitors, and charges according to an input signal V1p are stored in each of the capacitors. As a result, a gain of the switched capacitor amplifier circuit is derived from (Ca+C)/(Ca?Cx) wherein Ca indicates an electrostatic capacitance of the negative feedback capacitors, and Cx indicates an electrostatic capacitance of the positive feedback capacitors, and thus the gain can be increased without significantly increasing an electrostatic capacitance ratio.

Abstract: A transconductance difference amplifier (300) is described, for providing an output current dependent upon a difference between a first input voltage (302) and a second input voltage (304). The difference amplifier comprises an input sampling capacitor (306) having two conductors; a transconductance amplifier (312) having an input (318) coupled to a first conductor of said input sampling capacitor and a current output (314) for generating said output current; and an input switch (308, 310) for selectively coupling a second conductor of said input sampling capacitor to a first input of said difference amplifier for receiving said first input voltage and to a second input of said difference amplifier for receiving said second input voltage.

Abstract: A system and apparatus for reducing offset voltages in folding amplifiers is disclosed. In one form, a folding amplifier for use in an analog-to-digital converter is provided. The folding amplifier includes a first current source operable to be coupled to a first differential pair and a second differential pair. The folding amplifier further includes a switching network coupled between the first current source and the first and second differential pairs and operable to enable coupling the first current source to at least one of the first differential pair and the second differential pair.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: In one aspect, the present invention provides a method for amplifying a signal including generating an input signal and amplifying the input signal utilizing a chopper-stabilized, silicon carbide NMOS depletion mode operational amplifier to produce an amplified output signal.

Abstract: A switched capacitor amplifier provides high gain and wide bandwidth using dynamic loading. Dynamic loading is used to reduce the capacitive load during a high gain phase (e.g., during a sampling phase) and to increase the capacitive loading during a high feedback factor phase (e.g., during a holding phase). The capacitive load may be provided by an external capacitive load such as a sampling capacitor of a subsequent stage or sampling device. A low feedback factor provides a high voltage gain and the lower capacitive load. A high feedback factor increases the effective bandwidth of the amplifier by compensating for a unit gain bandwidth reduction that is due to high capacitive loading.

Abstract: A single stage switched capacitor programmable gain amplifier uses programmable capacitor values to adjust gain factors. The operation of the amplifier is described by a transfer function having two gain factors: (C1/C2) and (C2/C3). The gain factor of C1/C2 applies during the holding phase and the gain factor of C2/C3 applies during the sampling phase. The transfer function is equal to the product of the two gain factors: (C1/C2)×(C2/C3) such that the transfer function is equal to (C1/C3). The intermediate element C2 can be adjusted to maximize bandwidth because C2 is independent of the total transfer gain. Accordingly, the intermediate element C2 is substantially fixed from the holding phase to the following sampling phase such that the bandwidth of the programmable gain amplifier is maximized in the two phases.

Abstract: The present invention enables an IC to have a fast PWM while maintaining the low frequency clock requirement of the temperature measurement. Methods are presented to increase the resolution of the control using a relatively low input clock. According to one method, the numerator and denominator of the PWM duty cycle equation are adjusted to achieve a desired resolution. According to another method, a determined number of PWM cycles are used to set the PWM duty cycle. For example, an averaging of 1024 duty cycles may be used to achieve an increased resolution of the duty cycle as compared to using only one duty cycle. According to yet another method, an error integrating loop is used to determine the level of the next cycle. The number of cycles used to reach the target PWM duty cycle depends on the desired resolution.

Abstract: A DC offset canceling circuit. The DC offset canceling circuit applied in a variable gain amplifier includes chopper circuits, a transconductance amplifier, and at least one internal capacitor. The transconductance amplifier and at least one capacitor function as a filter for canceling DC offset of the variable gain amplifier. A first chopper circuit is inserted between the output of the variable gain amplifier and the input of the transconductance amplifier. A second chopper circuit is inserted between the output of the transconductance amplifier and the capacitor. The DC offset and low frequency noise of the transconductance amplifier, the undesired signal, is translated up to a chopping frequency by chopper circuits. The chopping frequency is much higher than the desired signal bandwidth, and the amount of the undesired signal in the passband of the signal is thereby greatly reduced.

Abstract: An apparatus and method for adding input voltage signals. First and second input voltage signals are respectively sampled onto first and second capacitors during a first clock phase. In response to a second clock phase, the first sampled input voltage that is held on the first capacitor is coupled to the negative input terminal of an amplifier, and the second sampled voltage held on the second capacitor is coupled to the positive terminal of the amplifier. A feedback voltage is provided from the amplifier output to the negative amplifier input via the first capacitor during the second clock phase. The first and second input voltage signals are added at the amplifier during the second clock phase to output the sum in response to the sampled input voltage signals and the output feedback, whereby the resulting transfer function is independent of capacitor mismatch and non-linearity.

Abstract: A differential amplifier includes first and second outputs and first and second supply rails. The differential amplifier further includes offset cancellation circuitry. The offset cancellation circuitry is operable during a calibration mode to generate an offset cancellation signal when the first and second outputs are both coupled to a voltage between the first supply rail and the second supply rail. The offset cancellation signal is for facilitating at least partial cancellation of an offset voltage associated with the first and second outputs during a normal operation mode of the differential amplifier.

Abstract: The invention relates to an operational amplifier comprising a first transistor amplifier stage at an input of the operational amplifier, which first transistor amplifier stage comprises chopped transistors, a second transistor amplifier stage cascoded to the first transistor amplifier stage, which second transistor amplifier stage is connected between the chopped first transistor amplifier stage and a supply voltage source, wherein the gain at the output of the chopped first transistor amplifier stage is reduced to gm1,2/gm3,4, where gm1,2*Rc is the gain of the first transistor amplifier stage, gm3,42*Rc is the gain of the second transistor amplifier stage and Rc is the resistance of the resistor between an output of the operational amplifier and the supply voltage source.

Abstract: An apparatus and method for an improved chopping mixer (100) having a bipolar mixer stage (140) for mixing signals (Ip, In, LOp, LOn) received thereby; an output chopping stage (160); and an AC coupling stage (150) for coupling the mixed signal to the output chopping stage. The signal prior to the chopping output stage is centered at the chopping clock frequency rather than DC. AC coupling allows removal of common mode signal in a desired frequency range. Also, the second order component present on each single ended output will also be DC blocked by the AC coupling capacitors, resulting in improved second order IP2 performance.

Abstract: A zero bypass apparatus for a low noise amplifier includes a bypass circuit, and a switching circuit coupled with a low noise amplifier and with the bypass circuit. The switching circuit includes one or more solid state devices responsive to absence of a control bias for switching an RF input signal from said amplifier to the bypass circuit with a low insertion loss and high isolation.

Abstract: A chopper type comparator is equipped with an input switching circuit 1 that switches between an input voltage VIN and a reference voltage VRE, a capacitor C1, and an amplification circuit 11 that is formed from amplifiers (CMOS inverters) 12. The input switching circuit 1 is provided with a switch CT1 that turns on and off the input voltage VIN, and a switch CT2 that turns on and off the reference voltage VRE. Rising and falling of control signals to the P channel and N channel transistors of the switches CT1 and CT2 are simultaneously conducted, and an intersection of the rising and falling sections thereof coincide with a center of the amplitude of the drive signals.

Abstract: An amplifier circuit with offset compensation is particularly suited for a Hall element. In addition to the useful signal demodulation that is normally present and connected downstream of an amplifier, an error signal demodulator provides an error signal demodulation. The measured signals that are tapped off at the Hall sensor are coupled out at the input or output of the amplifier, and a demodulated error signal is fed back to the input of the amplifier. This makes it possible to reduce the drive range of the amplifier. The amplifier circuit is suitable in particular for Hall sensors that are operated in chopped mode.

Abstract: The present invention is directed towards a single stage switched capacitor programmable gain amplifier. The operation of the amplifier is described by a transfer function having two gain factors: (C1/C2) and (C2/C3). The transfer function is equal to the product of the two gain factors: (C1/C2)×(C2/C3) such that the transfer function is equal to (C1/C3). The combination of the two different gain factors provides a wider range and finer step programmability of the amplifier. The amplifier does not have an idle phase, which reduces power dissipation. Additionally, the amplifier requires less switching which results in reducing the thermal noise and the switching noise produced by the amplifier.

Abstract: A chopper comparator includes an input voltage conversion circuit, a reference voltage input circuit and a comparison amplifier. The input voltage conversion circuit is applied to an input voltage. The input voltage conversion circuit converts the input voltage to a converted input voltage that is lower than a first voltage. The reference voltage input circuit provides a reference voltage. The comparison amplifier compares a voltage of the converted input voltage with the reference voltage and amplifies a result of the comparison. The comparison amplifier includes an inverter having a withstand voltage substantially equal to the first voltage.

Abstract: An output buffer, a slew-rate control circuit, a break-before-make circuit, and a current limited input amplifier are connected as a digital output driver. This provides a simple apparatus and method of switching current control and slew-rate control that limits power consumption of the digital output driver. To further minimize switching current, capacitors may be added to the break-before-make circuit. A comparator input circuit may be connected to the current limited input amplifier to form a comparator having a low-power-consuming digital output.

Abstract: A nulling amplifier (52A) for an auto-zeroed amplifier includes a first differential stage including first (3) and second (16) input transistors and a second differential stage including first (18) and second (19) nulling transistors coupled to drains of the second and first input transistors and to a folded cascode circuit (48) coupled to an output stage (59). A gain boost circuit increases the output impedance of the nulling amplifier. The gm ratios of the first and second input transistors and the first and second nulling transistors have values which establish a predetermined low input-referred noise level in the nulling amplifier, and the gain boost circuit maintains a low offset voltage.

Abstract: An improved circuit and technique are provided that facilitate residual offset correction during chopper stabilization of an amplifier circuit. A chopper stabilized amplifier can be configured with an additional gain stage configured between input and following stages of the amplifier. Instead of a second switching block being configured on the output of the input stage, the second switching block is coupled to the output of the additional gain stage. As a result, the offset voltage of the additional gain stage appears across the output of the input stage in the same polarity during chopper stabilization. Thus, the offset voltage that appears across the output of the input stage remains constant at the end of each of the chopping phases. Accordingly, any residual offset voltage, for example that due to changes in voltage across parasitic capacitances on the output of the input stage, can be eliminated.

Abstract: A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier (300a-300b) may include a capacitive switching circuit (304a-304b), a capacitive switching circuit (306a-306b), and an operational amplifier (302a-302b). Capacitive switching circuits (304a-304b and 306a-306b) may receive an analog input voltage through sample switches (308a-308b and 310a-310b). Capacitive switching circuit (304a-304b) receives an output from operational amplifier (302a-302b) through feedback switch (312a-312b). The programmable gain amplifier (300a-300b) may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

Abstract: A frequency compensation circuit includes a first and a second compensation capacitor for a frequency-compensated amplifier to which a chopped useful signal can be supplied. In a first clock phase, the useful signal is respectively supplied to the first compensation capacitor, and in a second clock phase the useful signal is respectively supplied to the second compensation capacitor. As a result, a stable, frequency-compensated amplifier is specified in which charge reversal in the frequency compensation capacitors or Miller capacitors is avoided, making possible a configuration with a small chip area. The principle is suited particularly to Hall sensors operated in chopped mode.

Abstract: A number of comparators are provided where each has a differential input coupled to receive a transmission line analog signal level. Each comparator has substantially variable offset that is controllable to represent a respective variable reference level, without requiring a separate input to receive a voltage reference level. An output of each comparator is to provide a value that represents a comparison between the transmission line analog signal level and the respective reference level.

Abstract: Transconveyance amplifiers, and more specifically charge transfer amplifiers, are included in analog-to-digital converters. Transconveyance amplifiers are used in averaging and interpolation circuits that facilitate converting an analog signal into a meaningful digital representation of the analog signal. Due to the characteristics of charge transfer amplifiers power dissipation in averaging and interpolation circuits is significantly reduced. Coupling capacitors associated with charge transfer amplifiers are utilized as analog sample and hold circuits for holding an analog signal while fine reference voltages settle. Thus, the need for separate sample and hold circuits is eliminated. A novel timing scheme allows an increased number of clock partitions for fine reference voltages to settle, thus providing for increased operational frequency.

Abstract: A waveform generator comprising an input terminal connected to one terminal of a first capacitor, a first switch connecting the other terminal of the first capacitor to one terminal of a second capacitor, a second switch connected for operatively discharging the second capacitor, the said one terminal of the second capacitor also being connected to the input of a buffer the output of which is connected to the output of the generator, and a third switch connected so as operatively to feed back the output of the buffer to the other terminal of the first capacitor. The generator can be implemented using polysilicon TFTs. The invention also relates to a display device and to electronic apparatus which include at least one of the described waveform generators.

Abstract: An operational amplifier arrangement (OA) including an operational amplifier (A) and an input offset control circuit (IOCS) is characterized in that said operational amplifier arrangement further includes a current sensing and comparison device (CSCD) adapted to measure and to compare respective output currents on series output branches of an output stage (OS) of said operational amplifier, said current sensing and comparison device (CSCD) being coupled between said output stage (OS) of said operational amplifier and said input offset control circuit (IOCS).

Abstract: An operational amplifier, which generates an output voltage at an output terminal that is equal to an input voltage, comprises: a differential circuit, which compares the input voltage and the output voltage; first and second output transistors, which are controlled by the output of the differential circuit to drive the output terminal; and an offset cancel circuit, connected with the differential circuit, for storing an offset amount of this differential circuit, wherein, in the offset cancel period in which the offset amount is stored by the offset cancel circuit, the output terminal is driven by the second output transistor, and in the operational amplifier operation period following the offset cancel period, the output terminal is driven by the first output transistor.

Abstract: A chopper type comparator includes an input switch circuit which inputs an input voltage and a reference voltage alternately in response to a control signal; and an output terminal which supplies an output voltage, having a level defined based on the difference between the input voltage and the reference voltage. The comparator further a MOS transistor operating in response to a control signal, and a timing control circuit which provide a delay to the control signal to be supplied to the first MOS transistor and the input switch circuit.

Abstract: A charge transfer amplifier that performs amplification without a selective coupling to a precharge reference voltage. In lieu of the selective precharge coupling, the drain of the PMOS transistor is selectively coupled to Vss during the reset and precharge phases. In addition, the drain of the NMOS transistor is selectively coupled to Vss during the reset phase, and is selectively coupled to Vdd during the precharge phase. The drain of the PMOS transistor is capacitively coupled through a first intermediate capacitor to the output terminal of the charge transfer amplifier. The drain of the NMOS transistor is capacitively coupled through a second intermediate capacitor to the output terminal. During the amplify phase, the drains of the NMOS and PMOS transistor are permitted to float except for any charge flow through the respective transistor.

Abstract: A differential amplifier has input and output terminals to generate a second signal at the output terminals for a first signal. The amplifier has feedback switches between the output terminals and the input terminals. Offset capacitors are coupled to the differential amplifier at the input terminals and reference voltages via charging switches to provide offsets for the first signal form the reference voltages via input switches.

Abstract: An amplifier is disclosed including multiple integrator stages. The amplifier includes a low-frequency path from a signal input to a signal output and relatively higher-frequency bypass paths around the first integrator stage. The paths converge at a summing node. To prevent instability when the integrators are saturated by large signals, the circuit includes a saturation detector which disables the relatively low-frequency paths during such saturation conditions.

Abstract: A chopper type comparator is equipped with an input switching circuit 1 that switches between an input voltage VIN and a reference voltage VRE, a capacitor C1, and an amplification circuit 11 that is formed from amplifiers (CMOS inverters) 12. The input switching circuit 1 is provided with a switch CT1 that turns on and off the input voltage VIN, and a switch CT2 that turns on and off the reference voltage VRE. Rising and falling of control signals to the P channel and N channel transistors of the switches CT1 and CT2 are simultaneously conducted, and an intersection of the rising and falling sections thereof coincide with a center of the amplitude of the drive signals.

Abstract: A ping-pong amplifier includes two differential amplifiers A1 and A2 and an error amplifier. The error amplifier has one input connected to a predetermined common-mode reference voltage VCMR, its other input switchably connected to the common-mode outputs of A1 or A2, and an output which is switchably connected to the common-mode reference (CMR) voltage inputs of A1 and A2. Respective memory capacitors CM1 and CM2 are connected to the two CMR inputs. The error amplifier is periodically connected between A1's common-mode output and its CMR input to form a closed-loop which forces A1's common-mode output voltage to be equal to VCMR, with the error amplifier's output voltage stored on CM1. A2's common-mode output voltage is similarly calibrated, with the error amplifier's output voltage stored on CM2. Both common-mode output voltages are thus made equal to VCMR, thereby reducing transients that might otherwise appear in the output as the amplifier ping-pongs between A1 and A2.

Abstract: A ping-pong amplifier employs auto-zeroing and chopping to simultaneously achieve low offset voltage and low frequency noise, as well as low energy at the chopping frequency. The ping-pong amplifier includes respective nulling amplifiers for each of its gain amplifiers, which auto-zero each gain amplifier. In addition, switches are included which allow the inputs and outputs of the active gain amplifier to be chopped. Thus, while one gain amplifier is being auto-zeroed, the other gain amplifier amplifies the input signal and its inputs and outputs are chopped. One of the described embodiments includes circuitry which reduces switching transients that might otherwise appear in the amplifier's output by ensuring that the common-mode output voltage of each gain amplifier is kept equal to a common-mode reference voltage.

Abstract: An auto-calibration circuit minimizes input offset voltage in an integrated circuit analog input device. The auto-calibration circuit may also calibrate a plurality of analog input devices on an integrated circuit die or in a multi-chip package (MCP). The auto-calibration circuit and analog input device(s) may be fabricated in combination with a microcontroller system on an integrated circuit die or in an MCP. The auto-calibration circuit controls input offset voltage compensation circuit that counteracts or compensates for input offset voltage so as to minimize voltage error at the output of the analog input device. A digital control circuit applies a digital word to the input offset voltage compensation circuit for generating the required input offset voltage compensation. A linear search or binary search of various values of the digital word may be used by the digital control circuit.

Abstract: An improved chopped CMOS operational amplifier that includes a modulator having differential input and output connections, an AC amplifier coupled to the modulator output, a demodulator coupled to the AC amplifier output, and an integrator coupled to the demodulator output. The improvement is realized in that the operational amplifier has a gain path comprising at least four inverting amplifiers, wherein three or a greater odd number of the inverting amplifiers comprise an integrator that is rendered stable by incorporating a nested integrating capacitor within the integrator, and at least one of the inverting amplifiers is coupled to the modulator output and configured as the AC amplifier. In another aspect of the invention, a second demodulator is introduced to derive a compensating signal that tends to counteract offset voltage components attributable to modulator switch mismatch.

Abstract: A switched capacitor correlated double sampling circuit includes an op amp, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal.

Abstract: The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.

Abstract: The present invention relates to an offset compensation apparatus in a differential amplifier circuit and an offset compensation method thereof that can compensate an offset in a differential amplifier circuit separately for each input signal. The offset compensation device preferably selectively couples a capacitor to an input of a differential amplifier to store an offset voltage. The offset compensation method preferably can operate by detecting an offset of the differential amplifier circuit, by storing the offset, by directly inputting the result of compensating the offset voltage for an input voltage into the differential amplifier and by outputting the output voltage corresponding to the input voltage without the offset voltage included. The differential amplifier circuit and the offset compensation method can further include an additional output stage coupled to a load.

Abstract: A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the individual operational amplifiers. The length of the off-phase can be adapted to the transient response of the operational amplifiers used. The clock configuration according to the invention can be used for further reducing the power consumption of switched op-amp circuits.

Abstract: A charge transfer amplifier includes a first stage charge transfer amplifier coupled to a positive capacitive feedback mechanism. The positive capacitive feedback mechanism is attached to the output terminal of a first stage charge transfer amplifier. This reduces the capacitance viewed at the output terminal of the first stage charge transfer capacitor thus increasing the overall gain of the charge transfer amplifier. The positive capacitive feedback mechanism includes a second stage amplifier having an output terminal capacitively coupled back to the output terminal of the first stage charge transfer amplifier. The coupling of the positive capacitive feedback mechanism to the charge transfer amplifier allows for enhanced amplifier gain while still retaining the beneficial characteristics of charge transfer amplifiers generally.

Abstract: An offset voltage calibration circuit for use with a digital switching amplifier. The calibration circuit includes an analog-to-digital converter for converting at least one DC offset voltage associated with the digital switching amplifier to digital offset data. A memory stores the digital offset data. Control circuitry controls the analog-to-digital converter. A digital-to-analog converter coupled to the memory receives the digital offset data and generates an offset compensation voltage for applying to an input port of the digital switching amplifier which thereby cancels at least a portion of the at least one DC offset voltage.

Abstract: An output amplifier for a strobed sampling circuit has first and second operational amplifiers coupled to receive the sampled output from the sampling circuit. The operational amplifiers each have a RC circuit having a high ohmic value resistor that is coupled from its inverting input terminal to its output terminal. The non-inverting input terminals receive biasing voltages that are coupled to the sampling circuit. The gating strobes to the sampling circuit produces a DC current through the feedback resistor as a result of strobe pulses being integrated by the RC circuit. Respective electronic switches are coupled in parallel with the RC circuits of the operational amplifiers and are closed at a predetermined time interval after each strobe pulse to discharge the stored charge on the capacitors prior to the next strobe pulse. The output signals from the operational amplifiers are summed in a summing amplifier.