Abstract: An amplifier circuit is disclosed that includes a first input terminal; a second input terminal; a first differential amplifier circuit that samples signals input to the first and second input terminals and outputs signals obtained by applying a gain to the sampled input signals having different voltages; and a second differential amplifier circuit that supplies first and second reference voltages referred to when a sampling operation is performed in the first differential amplifier circuit to the first and second input terminals, respectively. A potential difference between the first and second reference voltages is equal to an offset voltage of the first differential amplifier circuit.

Abstract: A chopper-stabilized amplifier includes a main signal path having first and second chopping circuits at the inputs and outputs of a transconductance amplifier, and an auto-correction feedback loop. The feedback loop includes a transconductance amplifier connected to amplify the chopped output from the main signal path, a third chopping circuit which chops the amplified output, a filter which filters the chopped output to substantially reduce any offset voltage-induced AC component present in the signal being filtered, and a transconductance amplifier which receives the filtered output and produces an output which is coupled back into the main signal path. When properly arranged, the auto-correction feedback loop operates to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in the amplifier's output.

Abstract: A chopper stabilized amplifier has differential inputs, an output, and a low frequency path and a high frequency path from the differential inputs to the output. Chopping occurs, at a chopping frequency, of a differential signal at differential inputs and outputs of an amplifier stage of the low frequency path to thereby produce a chopped differential signal that has a DC offset of the amplifier stage frequency shifted up to the chopping frequency. A continuous time filter embedded between a pair of further amplifier stages of the low frequency path is used to attenuate chopper frequency ripple resulting from the chopping at the chopping frequency. Additionally, a buffer is used to allow feedback through a compensation capacitor for the low frequency path, yet prevent chopper frequency ripple from feeding forward through the compensation capacitor to the output of the amplifier.

Abstract: An embodiment is directed to an instrumentation amplifier. The instrumentation amplifier includes an output stage for generating an output voltage, a low-frequency path coupled with the output stage, and a high-frequency path coupled with the output stage. The high-frequency path dominates the low-frequency path at frequencies above a particular frequency, and the low-frequency path dominates the high-frequency path at frequencies below the particular frequency. The low-frequency path includes an input stage for sensing a differential input and generating an intermediate current based thereon, a feedback stage coupled with the input and output stages, the feedback stage for generating a feedback current based on the output voltage, and an auto-zeroing circuit coupled with the input, feedback, and output stages, the auto-zeroing circuit for generating a nulling current.

Abstract: A first gain stage and a second gain stage having different gains are linked in cascade to construct a wide range and high resolution programmable gain amplifier. The second gain stage can be used only for low gain and low power consumption. Furthermore, two pairs of chopper circuits are used to shift flicker noise when the programmable gain amplifier is operated.

Abstract: An active circuit includes (a) a first chopper circuit that receives an input signal and a chopping signal of a frequency higher than a base band of the input signal, and that provides a modulated input signal; (b) an amplifier that receives the modulated input signal and that provides an amplified signal resulting from amplifying the modulated input signal; and (c) a second chopper circuit that receives the amplified signal and the chopping signal to provide an output signal. The chopping signal has a frequency that may be dynamically adjusted to accommodate changes in impedance and signal spectrum as a result of the operations of the chopper circuits. The active circuit further includes a low pass filter that receives the output signal and that attenuates components of the output signal above the base band of the input signal. In this manner 1/f noise introduced by the amplifier is eliminated or reduced.

Abstract: According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.

Abstract: A frequency-mixing device performing voltage multiplying and low-pass filtering operations in addition to frequency mixing is provided. The three operations may be carried out with the same components by designing the frequency mixer appropriately. The frequency mixer comprises a first capacitance connected in series to the input of the frequency-mixing device, a first switch connected in parallel to the first capacitance, a second switch connected in series to the first capacitance, and a second capacitance connected in parallel to the second switching means. The switches are controlled by a local oscillator signal to close and open alternately according to a change in the voltage level of the first oscillator signal.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: A chopper-stabilized amplifier (1B) having a first output (25) includes an input chopper (9) for chopping an input signal and applying it to the input of a first amplifier (2) and an output chopper (10) for chopping an output signal of the first amplifier and applying it to the input of a switched capacitor notch filter (30-1).

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: An embodiment of the present invention is directed to an instrumentation amplifier. The amplifier includes a first amplification sub-circuit, which includes an input stage for sensing a differential input and generating an intermediate current based thereon, a feedback stage, and an auto-zeroing circuit. The feedback stage is operable to generate a feedback current based on an output voltage of the amplifier. The auto-zeroing circuit is operable to generate a nulling current, which compensates for errors in the intermediate and feedback currents resulting from input offsets in the input and feedback stages. The amplifier further includes a second amplification sub-circuit, an output stage, and a switching circuit. The switching circuit switches the amplifier between first and second configurations. In the first configuration, the first amplification sub-circuit provides a first amplification path for the amplifier.

Abstract: An energy saving driving circuit and method is provided for use with a solid state relay (SSR). The circuit and method reduce the overall energy required to drive a solid state relay by maintaining the SSR in an “on” state with a minimal maintenance or holding current after applying a turn-n current. The driving circuit includes a control circuit configured for outputting a control signal; a turn-on circuit configured for providing an output current at a first current level for a first time period in response to the control signal; and a holding circuit configured for maintaining said output current at a second reduced current level for a second time period. The maintenance or holding current is reduced in respect of that of a conventional driving current, and in some cases may be an order of magnitude or more less in magnitude than a conventional driving currents thereby resulting in less energy consumed by the SSR.

Abstract: According to one embodiment, a system for constant bandwidth DC offset correction in an amplifier includes a number of amplifier stages having an input and an output coupled together in series. The system for constant bandwidth DC offset correction further includes a number of DC offset correction feedback loops which include a variable gain transconductor coupled to an integration capacitor further coupled to a fixed gain transconductor. Each of the DC offset correction feedback loops are coupled to the input and output of each of the number of amplifier stages. The transconductance of the variable gain transconductor in each of the number of DC correction feedback loops is varied in relation to a gain of the number of amplifier stages, such that the DC offset correction feedback loops provide DC offset correction while maintaining a constant bandwidth.

Abstract: Chopper stabilized amplifiers combining low clock noise and linear frequency characteristics. The chopper stabilized amplifiers are used in offset correction circuitry, with the output of the chopper stabilized amplifiers being integrated by an integrator. The integrator operates on alternate cycles, with a sample and hold circuit sampling the integrator output when the integrator is not integrating, with the output of the sample and hold being coupled to the main amplification path to cancel offset after at least some amplification is achieved. Autozeroing of amplifiers in the offset correction circuitry is also disclosed. The invention is applicable to operational amplifiers and instrumentation amplifiers.

Abstract: A dual path chopper-stabilized amplifier (100) includes first (11) and second (11A) chopping/notch-filtering paths, each including an input chopper (9,9A), a transconductance amplifier (2,2A), and a notch filter (15,15A). Chopping and notch filtering in the first path are controlled by first (CHOPCLK) and second (FILTERCLK) clock signals, respectively. Chopping and notch filtering in the second path are controlled by the second (FILTERCLK) and first (CHOPCLK) clock signals, respectively. Outputs of the first (15) and second (15A) switched capacitor notch filters are combined to provide an amplifier output signal (23A,B) that updates a capacitance (C4) at 4 times the frequency of the filter clock signal, to thereby improve amplifier stability without increasing clock frequency.

Abstract: Provided is a dual sampling/pixel gain amplifier (CDS/PxGA) circuit with a shared amplifier, and more particularly, to a dual CDS/PxGA circuit for adjusting a gain of an amplifier based on capacitance. The dual CDS/PxGA circuit comprises: a first sampler for sampling a reset level and a data level of a first pixel; a second sampler for sampling a reset level and a data level of a second pixel; and an operational amplifier for receiving sampling values from the first and second samplers, calculating output signals of the first and second pixels using the sampling values, and amplifying the calculated output signals. Thus, it is possible to reduce a speed of an operational amplifier by using the dual CDS/PxGA structure, reduce power consumption by sharing the operational amplifier, and obtain a variable gain of a wide range by adjusting capacitance using a capacitor array.

Abstract: A double conversion RF tuner includes an up-conversion unit and a down-conversion unit. The up-conversion unit up converts a received radio frequency (RF) signal corresponding to a first frequency band to a first intermediate frequency (IF) signal and up-converts the received RF signal corresponding to a second frequency band higher than the first frequency band to a second IF frequency. The down conversion unit down converts one of the first and second IF signals outputted from the up-conversion unit to a final IF signal.

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a CMOS amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion.

Abstract: An error amplifier for closed loop operation is provided. The error amplifier has a track input and a feedback input. During soft-start, a voltage offset is added to the error amplifier input. In one embodiment, the voltage offset is gradually removed during the soft-start.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: The invention is directed to a solid-state replacement for a variable transformer. The circuit arrangement presented is not placed in series with the load. It can change output voltage quickly, and is able to deliver more current to the load than is drawn from the source while stepping down because the circuit is not placed in series with a load. The output voltage from the driver circuit is a low-frequency sine wave that is “chopped” by a high frequency carrier, yet the end result after the transformer or LC filter is a very clean sine wave. The circuit arrangement is lightweight and inexpensive to fabricate.

Abstract: A chopper circuit has a delay circuit that delays a received control signal and a difference detection circuit that detects a difference between a control signal delayed by the delay circuit and the received control signal. A first threshold based on which the delay circuit checks a change in the received control signal and a second threshold based on which the difference detection circuit checks a change in the received control signal are realized with a common threshold.

Abstract: A circuit for minimizing a voltage offset between inverting and non-inverting input terminals of an operational amplifier circuit is provided. The circuit includes a chopper circuit connected to the inverting and non-inverting input terminals of the operational amplifier circuit, the chopper circuit including: an amplifier having differential outputs; and a switching circuit for periodically reversing the input terminals to the amplifier and periodically reversing the outputs of the amplifier to provide an output signal having an offset adjustment signal to the operational amplifier circuit to adjust the offset of the operational amplifier circuit.

Abstract: A comparator includes: a CMOS inverter constituted by a combination of a first p-channel MOS transistor and a first n-channel MOS transistor; a second p-channel MOS transistor connected in parallel to the first p-channel MOS transistor in an analog input period, and disconnected from the first p-channel MOS transistor in a comparison period; and a second n-channel MOS transistor connected in parallel to the first n-channel MOS transistor in the analog input period, and disconnected from the first n-channel MOS transistor in the comparison period.

Abstract: A DC to DC converter includes a current detecting circuit having a level shift circuit, which includes a resistor and a current source. A first low-pass filter is led out from a node via a signal line and includes a resistor and a capacitor. A first switch is provided after the level shift circuit, a second switch is provided after the low-pass filter, a second low-pass filter, which includes a resistor and a capacitor, an operational amplifier, a third switch is provided between an output terminal and an inverted input terminal of the operational amplifier, and a capacitor is provided between the inverted input terminal of the operational amplifier and GND. An output current is detected with high accuracy without lowering the efficiency by detection resistance.

Abstract: According to one embodiment, a system for constant bandwidth DC offset correction in an amplifier includes a number of amplifier stages having an input and an output coupled together in series. The system for constant bandwidth DC offset correction further includes a number of DC offset correction feedback loops which include a variable gain transconductor coupled to an integration capacitor further coupled to a fixed gain transconductor. Each of the DC offset correction feedback loops are coupled to the input and output of each of the number of amplifier stages. The transconductance of the variable gain transconductor in each of the number of DC correction feedback loops is varied in relation to a gain of the number of amplifier stages, such that the DC offset correction feedback loops provide DC offset correction while maintaining a constant bandwidth.

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a CMOS amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion.

Abstract: In a chopper amplifier circuit operable at a low voltage utilizing a switched operational amplifier, a chopper modulator chopper-modulates an input signal according to a predetermined control signal, and outputs a chopper-modulated signal. An amplifier circuit constituted by the switched operational amplifier amplifies the chopper-modulated signal outputted from the chopper modulator, and outputs an amplified chopper-modulated signal. A chopper-demodulator of the switched operational amplifier chopper-demodulates the amplified chopper-modulated signal outputted from the amplifier circuit according to the control signal, and outputs a demodulated output signal as a chopper-amplified output signal from an output terminal. A chopper modulator chopper-modulates a demodulated signal outputted from the chopper demodulator according to the control signal, and outputs a chopper-modulated signal to an input terminal of the amplifier circuit.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: An amplifying circuit includes an input chopping circuit, an amplifier, and an output chopping circuit. The input chopping circuit is operably coupled to chop an input signal at a chopping rate to produce a chopped input signal. The amplifier has a first input transistor section, a second input transistor section, and a transistor load section. The first and second input transistor sections are operably coupled to receive the chopped input signal, wherein the first input transistor section amplifies the chopped input signal when the chopped input signal is in first signal level range, the second input transistor section amplifies the chopped input signal when the chopped input signal is in a second signal level range, and the first and second input transistor sections amplify the chopped input signal when the chopped input signal is in a third signal level range, wherein the transistor load section is coupled to the first and second input transistors sections to produce an amplified chopped signal.

Abstract: Chopper amplifiers and methods of amplification are provided. A circuit includes an adjustable modulation resistance network, an amplifier, and an adjustable feedback resistance network. The adjustable modulation resistance network receives and modulates an input signal to produce a modulated signal including varying an input resistance, which includes a switch resistance. The amplifier has an input and an output. The adjustable feedback resistance network varies a feedback resistance, which includes a switch resistance. In addition, a suppression circuit is also included that can produce the feedback signal for preventing the direct current offset signal from substantially affecting the output signal.

Abstract: A chopper circuit has a delay circuit that delays a received control signal and a difference detection circuit that detects a difference between a control signal delayed by the delay circuit and the received control signal. A first threshold based on which the delay circuit checks a change in the received control signal and a second threshold based on which the difference detection circuit checks a change in the received control signal are realized with a common threshold.

Abstract: Apparatus (1) for continuous-time application, comprising an operational amplifier (2) and a self-zeroing control unit (3) for reducing an offset of the operational amplifier (2). The self-zeroing control unit (3) provides for a self zeroing operation mode and a normal operation mode. It comprises a comparator (6), a successive approximation register (7), and a digital-to-analog converter (8).

Abstract: An amplifier circuit includes a first amplifier and a second amplifier and sets of switching devices controlled by a bistate control signal. The bistate control signal is in the first state to cause the first and second sets of switching devices to configure the first amplifier and the second amplifier in a positive parallel configuration and the bistate control signal is in the second state to cause the first and second sets of switching devices to configure the first amplifier and the second amplifier in a negative parallel configuration. When the bistate control signal switches states at each sample cycle of the amplifier circuit, the first amplifier and the second amplifier toggle between the positive parallel configuration and the negative parallel configurations to cancel out crosstalk signals stored at the positive and negative input terminals of the first and second amplifier circuit.

Abstract: A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.

Abstract: An amplifier which comprises an operational amplifier, a semiconductor switch that selectively connects at least one circuit to an input terminal of the operational amplifier, and a device for virtual shorting of both terminals of the semiconductor switch in an isolated state.

Abstract: Frequency stabilization of chopper-stabilized amplifiers using multipath hybrid double-nested Miller compensation. The compensation may provide a desired 6 dB/oct roll off for both instrumentation amplifiers and operational amplifiers. Various embodiments are disclosed.

Abstract: The conventional chopper comparator circuit has had high power consumption because the gain thereof used to be set high, so that there has been the need for cutting down on power consumption.

Abstract: Chopper chopper-stabilized instrumentation and operational amplifiers having ultra low offset. The instrumentation amplifiers use current-feedback, and include, in addition to a main chopper amplifier chain, a chopper stabilized loop for correcting for the offset of the input amplifiers for the input signal and for receiving the feedback of the output voltage sense signal. Additional loops, which may include offset compensation and autozeroing loops, may be added to compensate for offsets in the chopper stabilized loop for correcting for the offset of the input amplifiers. Similar compensation is disclosed for decreasing the offset in operational amplifiers.

Abstract: A correlated double sampling pixel gain amplifier includes an operational amplifier, an input sampling capacitor, and a feedback capacitor. The input capacitor samples the input signal during a first time phase and the feedback capacitor receives the signal charge from the input capacitor. No sampling switch is located between the input capacitor and the input terminal. The feedback capacitor may include a capacitor array.

Abstract: Even when an input is small in a current supply capacity, a differential amplifier circuit capable of outputting a high accurate voltage with an offset corrected can be obtained.

Abstract: A BTL amplifier has a resistance element connected to an output reference voltage input terminal of an inverting amplifier. For offset compensation of the BTL amplifier, a variable current source controller controls an input switching circuit to cause application of compensation input voltages sent from an internal reference voltage source to a first input terminal and a second input terminal. The variable current source controller also controls a variable current source in response to an output signal from a comparator to minimize an output offset voltage, whereby a current flowing through the resistance element is adjusted to control the voltage at the output reference voltage input terminal.

Abstract: Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Abstract: A method and apparatus for substantially reducing and virtually eliminating direct current flow through the input transistor(s) of an input buffer circuit for an electret microphone is disclosed. An input transistor is provided and operably connected to an input and an output of the input buffer circuit. The input transistor has a first operating state wherein current flow occurs in a first direction and a second operating state wherein the a current flow occurs in a second direction—opposite that of the first direction. The input transistor is biased to alternately control operation between the first operating state and the second operating state. The alternating, opposing flows of current of the respective operating states cooperate to substantially reduce and virtually eliminate the flow of direct current through the input transistor(s) of the buffer circuit.

Abstract: A switch comprises an input with two input lines and an input stage comprising four current controlled PNP-transistors and four resistors, and an output comprising two output lines, and arranged to receive a constant voltage on the input and on the output produce a variable voltage. The switch further comprises four constant current sources which are connected to the bases of the first, second, third and fourth transistor, respectively so that the transistors are saturated. The switch further comprises four alternating current sources which are connected to the emitters of the first, second, third and fourth transistor, respectively, so that the transistors alternately are conducting current from emitter to collector and from collector to emitter. Furthermore, an amplifier, a comparator and a method for tuning the working point of a power transistor can be provided using such a switch.

Abstract: A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T1, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T2.

Abstract: A write driver circuit for driving a magnetic head applicable to a variety of magnetic heads or magnetic storage media is disclosed. The circuit includes a write current generating section for generating plural types of write current for magnetizing a predetermined area of a magnetic storage medium in a predetermined direction; a switching signal generating section for generating a switching signal for switching among the write currents; a switching section for changing the direction of magnetization through the magnetic head by switching among the write currents based on the switching signal; and an overshoot current generating section for generating an overshoot current for instantaneously increasing the write current when the direction of magnetization is changed by the switching section; wherein the circuit further includes an overshoot current generation signal producing section, and is designed so that the overshoot current is generated based on an overshoot current generation signal produced thereby.

Abstract: A signal processing system utilizes chopping modulation technology to remove 1/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry use direct and cross-over switches to modulate low frequency noise, such as 1/f noise, out of a signal baseband. Chopping circuits are particularly useful with low frequency baseband applications such as audio applications. In one embodiment, the direct switches coupled to respective input and output terminals of a differential amplifier have nonoverlapping conduction phases with cross-over switches coupled to the terminals of the differential amplifier. Additionally, the direct switches coupled to the respective input and output terminals have different duty cycles with respect to each other, and the cross-over switches coupled to the respective input and output terminals of the differential amplifier have different duty cycles with respect to each other to reduce noise transfer to an output of the system.

Abstract: In a pulse generator, a sawtooth-shaped wave generator circuit generates a sawtooth-shaped wave by charging and discharging a capacitor. The sawtooth-shaped wave is fed to a comparator that performs pulse-width modulation on it in accordance with the voltage it receives via a terminal and thereby produces pulses. The comparator has its output grounded through a transistor that is turned on with appropriate timing by the sawtooth-shaped wave generator circuit. Thus, the maximum duty factor of the output pulses is made equal to the duty factor of the sawtooth-shaped wave.