Abstract: An RMS-DC converter includes a chopper-stabilized square cell that eliminates offset, thus enabling high-bandwidth operation. The chopper-stabilized offset requires only a small portion of the circuitry (i.e., a single component square cell) which operates at high frequencies, and is amenable to using high-bandwidth component square cells. Using the chopping technique minimizes required device sizes without compromising an acceptable square cell dynamic range, thereby maximizing the square cell bandwidth. The RMS-DC converter consumes less power than conventional RMS-to-DC converters that requires a high-frequency variable gain amplifier.

Abstract: A method for operating a brushless electric motor, the windings being energized by an inverter with the aid of six switches. A detection unit for detecting defective switches, a unit for measuring voltage at the outputs of the inverter, and a microcontroller for controlling the switch and for generating a pulse width modulated voltage supply for the windings are provided. A short-circuited switch causes a torque in the electric motor opposite the actuating direction of the electric motor. The method proposes that after detecting a short-circuited switch, the windings (U. V. W) are energized to generate a motor torque that is, on the whole, positive. An actuating period of the electric motor is divided into a plurality of sectors, wherein, in accordance with the defective switch, individual sectors are deactivated for the actuation of the windings (U, V, W), while other sectors are used to actuate the windings (V, W).

Abstract: A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.

Abstract: Buffer circuit embodiments are described. A buffer circuit includes an input configured to receive an input signal and a buffer configured to generate an output signal based on the input signal. In one embodiment, the buffer circuit includes a programmable chopping module coupled with the buffer, wherein the programmable chopping module is programmable with a selected configuration from a plurality of configurations, and wherein the programmable chopping modulates the input signal based on the selected configuration. In another embodiment, the buffer circuit further includes a programmable output filter coupled with the buffer, wherein the programmable output filter is programmable with a selected configuration form a plurality of configurations, and wherein the programmable output filter filters a frequency band of the output signal based on the selected configuration.

Abstract: A bioamplifier that includes a high pass filter, open-loop amplifier, and low pass filter in an area efficient design that can be used in implantable neural interfaces. The high pass filter can be implemented by using a switch-capacitance resistor coupled with parasitic capacitance of the electrode. The amplifier can be chopper stabilized and can include a high gain, current-ratio first stage followed by one or more dimension-ratio stages. The low pass filter utilizes the output impedance of the open-loop amplifier to form an embedded gm-C low pass filter.

Abstract: A circuit for generating a voltage waveform at an output node. The circuit includes a voltage rail connected to the output node via a voltage rail switch; an anchor node connected to the output node via an inductor and a bidirectional switch, wherein the bidirectional switch includes two or more transistors connected in series; and a control unit configured to change the voltage at the output node by controlling the voltage rail switch and the bidirectional switch so that, if a load capacitance is connected to the output node, a resonant circuit is established between the inductor and the load capacitance. The circuit may be included in an apparatus for use in processing charged particles, e.g. for use in performing mass spectrometry or ion mobility spectrometry.

Abstract: A signal generator generates a combined signal that is generated only in the period where supply of a pulse signal is effected, a pulse signal whose frequency is of a higher impulse repetition frequency than the frequency of the period setting signal and whose amplitude represents a voltage value that is lower than the high voltage HVDC value. A semiconductor switch accumulates electric charge on a capacitative element by means of the high voltage HVDC from the high voltage generator when the voltage value of the combined signal is lower than the set gate voltage value and generates an impulse voltage whose peak value is the value of the high voltage HVDC, by means of the electric charge that is discharged from the capacitative element when the voltage value of the combined signal exceeds the set gate voltage value.

Abstract: A method for generating a ramp comprises providing a voltage reference source, providing a summing amplifier, providing n switched capacitor elements coupled in parallel between the voltage reference source and the summing amplifier, and selectively activating a predetermined number of the switched capacitor elements to first store charge on each activated switched capacitor element and then to measure the sum of the charges on the activated capacitor switch elements in each of a fixed-integer number of time slots in a cyclical manner, the predetermined number being between 0 and n.

Abstract: Switching is provided in a transducer array of medical diagnostic ultrasound imaging. The switching controls the formation of macro elements or aperture for scanning a plane or volume. The switches are implemented with one or more transistors. The control causes the gates of the transistor to float during the “on” connection. While on, the switch connects, allowing ultrasound signals to pass through the switch.

Abstract: A circuit includes an input, two or more sampling capacitors each in a different channel, means for connecting each sampling capacitor to the input, means for discharging the sampling capacitors to a given voltage in a reset phase, and means to use the voltage across the sampling capacitor for further processing in a hold phase. The two sampling capacitors operate in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in the hold phase.

Abstract: An apparatus includes a capacitance-to-voltage converter circuit configured to be electrically coupled to a micro-electromechanical system (MEMS) sensor circuit. The capacitance-to-voltage converter circuit includes a differential chopping circuit path configured to receive a differential MEMS sensor output signal and invert a polarity of the differential chopping circuit path, and a differential sigma-delta analog to digital converter (ADC) circuit configured to sample the differential MEMS sensor output signal and provide a digital signal representative of a change in capacitance of the MEMS sensor.

Abstract: According to the present invention, a switched capacitor circuit comprises: an inverting amplifier for removing the offset by using a chopper stabilization circuit; a sampling unit which is connected between an input terminal and the inverting amplifier; and a feedback unit which is connected to the inverting amplifier in parallel.

Abstract: The invention provides a switching system. The switching system comprises an H bridge, a current router, and a control circuit. The H bridge comprises a first switch and a second switch coupled to a first output node and a third switch and a fourth switch coupled to a second output node, wherein a load is coupled between the first output node and the second output node. The current router comprises a first shunt switch and a second shunt switch coupled between the first output node and the second output node. The control circuit generates a first control signal to control the first switch and the fourth switch, generates a second control signal to control the second switch and the third switch, generates a third control signal to control the first shunt switch, and generates a fourth control signal to control the second shunt switch.

Abstract: Apparatus and methods for notch filtering are provided. In certain implementations, an amplifier includes amplification stages for providing signal amplification, chopper circuitry for generating a chopped signal by chopping an amplified signal associated with the amplification stages at a chopping frequency, and a time-interleaved finite impulse response (FIR) notch filter for notching frequency components of the chopped signal near the chopping frequency. The time-interleaved FIR notch filter includes a plurality of FIR filters configured to sample the chopped signal at a sampling rate of about twice the chopping frequency. The FIR filters are interleaved in time to reduce sampling error. Additionally, the time-interleaved FIR notch filter includes an infinite impulse response (IIR) filter configured to average samples taken by respective ones of the FIR filters and to integrate the averaged samples to generate the time-interleaved FIR notch filter's output signal.

Abstract: A method for generating a signal is provided, the method including: providing a first signal having a first signal frequency; providing a second signal having a second signal frequency or a third signal frequency, wherein the second signal frequency is higher than the third signal frequency; switching the second signal having the second signal frequency to the third signal frequency based on a predefined first signal event of the first signal; and returning the second signal having the third signal frequency to the second signal frequency in response to a predefined second signal event.

Abstract: A signal processing apparatus is provided that comprises a signal path including first and second signal processing stages for processing a signal. A switch, in a first state couples and in a second state de-couples an output of the first signal processing stage to an input of the second signal processing stage. An auxiliary stage coupled to the output of the first signal processing stage generates a control signal dependent to a DC level at the output of the first signal processing stage, on a DC level in the auxiliary stage, and indicates a DC offset at an output of the second signal processing stage. A calibration circuit, responsive to the control signal, adjusts a DC level in the signal path preceding the output of the first signal processing stage when the switch is in the second state.

Abstract: A switched amplifier circuit arrangement comprises a main amplifier (Amp) having an input terminal (In) and an output terminal (Out) and a regulating amplifier (rAmp) to set an input and an output operating point of the main amplifier (Amp). The regulating amplifier (rAmp) exhibits an auxiliary amplifier (A) having a first input terminal coupled to a reference level (Vref), a second input terminal (Ain) coupled to the output terminal (Out), and an output terminal (Aout) which is connected via a first switch (S1) to the input terminal (In). Moreover, the switched amplifier circuit arrangement comprises a cancellation capacitor (Cc) coupled to the input terminal (In), a second switch (S2) which is coupled between the output terminal (Out) and the cancellation capacitor (Cc) at a first circuit node (n1), and a third switch (S3) connected between the circuit node (n1) and the reference level (Vref).

Abstract: The present invention relates to an electrical device for charging accumulator means (5), said electrical device comprising: a motor (6) connected to an external mains (11); an inverter (2) connected to the phases of said motor (6); and switching means (4) integrated into the inverter (2), said switching means (4) being configured to permit said motor (6) to be supplied and to permit the accumulator means (5) to be charged by the inverter (2). According to the invention, said electrical device further includes, for each phase of said motor (6), an RLC low-pass filter (18) connected, on the one hand, to the mid-point (16) of the phase of said motor (6) and, on the other hand, to ground.

Abstract: A multi-input differential amplifying device of the present invention includes: a differential amplifier having an inverting input terminal and a non-inverting input terminal; and an input portion configured to apply a first input voltage to a first input terminal that is one of the inverting input terminal and the non-inverting input terminal and apply a second input voltage to a second input terminal that is the other input terminal, the first input voltage corresponding to first input signals that are a plurality of input signals for the first input terminal, the second input voltage corresponding to a second input signal that is one input signal for the second input terminal. The input portion is configured to correct an offset voltage between the first input voltage and the second input voltage.

Abstract: The present invention relates to a parallel light emitting diode (“LED”) drive circuit and provides a drive circuit configured to drive a parallel array of LEDs. The drive circuit comprises: a plurality of switches, a plurality of sampling resistors, and a plurality of chopper amplifiers. Each switch is coupled to a respective LED in the LED array. Each chopper operational amplifier configured to receive a reference voltage and a switching control signal and generate an input offset voltage. Each chopper operational amplifier includes a differential amplifier including an input transistor pair and a current mirror transistor pair, of which the electrical positions can be reserved when the switching control signal is switched between a first state and a second state, wherein the offset voltage, which causes the lightness mismatching in a parallel LED circuit, can be cancelled.

Abstract: A source driver and a receiver thereof are disclosed. A two-stage amplifier of the receiver includes a first-stage circuit and a second-stage circuit. The second-stage circuit includes a first switch, a second switch, a third switch, a first node, and a second node. The first switch is coupled between the first node and a ground end; the second switch is coupled between the second node and the ground end; the third switch is coupled between the first node and the second node. When the receiver wants to wake up from a power-saving mode to a normal operation mode, the first switch and the second switch are switched to the off-state according to a control signal at first; after a period of delay time, the third switch is also switched to the off-state according to a delayed control signal.

Abstract: Disclosed are systems and methods to achieve a low noise, fully differential amplifier with controlled common mode voltages at each stage output but without the requirement of a common mode feedback loop. Common mode voltages are adjusted by adjusting the currents flowing through the load impedances (bias currents) wherein the currents are derived from one or more voltage-to-current converters based on an impedance that matches to the load impedances of the stages of the amplifier. The amplifier invented is primarily used for amplification of low frequency signals. The amplifier has one or more gain stages applying only one conduction type of transistors of an IC technology that has the lowest transition frequency between 1/f noise and white noise to achieve a low chopping or autozeroing frequency.

Abstract: A differential amplifier amplifies the difference between a signal input to the non-inverting terminal via a capacitor and a signal input to the inverting terminal. A switch switches whether to input the signal to the non-inverting terminal via the capacitor. A resistance is connected between the non-inverting terminal and the inverting terminal. An offset voltage corrector corrects the offset voltage of the differential amplifier based on the output signal of the differential amplifier during a correction period in which the switch is controlled not to input the signal to the non-inverting terminal via the capacitor.

Abstract: An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.

Abstract: The present invention quickly detects an offset and prevents cutoff of low frequency signals. Offset detection circuits smooth an output of a variable gain amplifier at a predetermined time constant and detects the offset, which is a DC component. The detected offset is added to the input of the variable gain amplifier by an adder and the offset in the output of the variable gain amplifier is corrected. The time constant in the offset detection circuit is changed by the resistance values of the variable resistors. Then, the time constant is changed to a small time constant when the gain of the variable gain amplifier is changed and thereafter to a large time constant.

Abstract: A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode.

Abstract: A liquid-crystal display panel includes: gate lines each serving as a row-direction line which is one of the rows of a two-dimensional matrix; data signal lines each serving as a column-direction line which is one of the columns of the two-dimensional matrix; a plurality of liquid-crystal pixel sections which are laid out to form the two-dimensional matrix and each placed at the intersection of one of the gate lines and one of the data signal lines; chopper-type comparators each connected to one of the data signal lines and each used for converting the value of a sensor signal read out from one of the liquid-crystal pixel sections connected to the data signal lines into a binary value; and a shift register for converting outputs of the chopper-type comparators from parallel data into serial data and outputting the serial data.

Abstract: A bias potential generating circuit includes a clock supply circuit that generates a clock signal having a predetermined frequency; a rising sine wave generating circuit that generates a rising wave form signal having a wave form of a rising portion of a sine wave; a ?? conversion circuit that generates a pulse width modulation signal by pulse width modulating the rising wave form signal; a first resistor, one end connected to a reference potential input terminal of an operational amplifier; a second resistor, one end connected to the first resistor and to the reference potential input terminal of the operational amplifier, and the other end being grounded; and a switch connected to a power supply and to the other end of the first resistor, the switch being turned ON and OFF by the pulse width modulation signal.

Abstract: A system includes a sensing system, a first chopped circuit, a second chopped circuit, and a multiplexer. The sensing system is configured to provide input signals. The first chopped circuit is configured to switch in response to the input signals crossing a first limit and to provide a first output signal that is valid during some chopping phases. The second chopped circuit is configured to switch in response to the input signals crossing a second limit and to provide a second output signal that is valid during other chopping phases. The multiplexer is configured to switch between the first output signal and the second output signal to provide a valid output signal during all chopping phases.

Abstract: A semiconductor device includes a variable resistor that sets a resistance value as a first resistance value in an emphasis mode, and as a second resistance value smaller than the first resistance value in a de-emphasis mode, a first driver that sets an output impedance as a third resistance value in the emphasis mode, and as a fourth resistance value larger than the third resistance value in the de-emphasis mode, a second driver that sets the output impedance as a fifth resistance value in the emphasis mode, and as a sixth resistance value larger than the fifth resistance value in the de-emphasis mode, and a controller that controls conductive states of the first and second drivers according to an input signal, and switches the output impedances of the first and second drivers and the resistance value of the variable resistor between the emphasis mode and the de-emphasis mode.

Abstract: The present invention relates to a parallel light emitting diode (“LED”) drive circuit and provides a drive circuit configured to drive a parallel array of LEDs. The drive circuit comprises: a switching control signal generator, a plurality of switches, a plurality of sampling resistors, and a plurality of chopper amplifiers. Each switch is coupled to a respective LED in the LED array. Each chopper operational amplifier configured to receive a reference voltage and a switching control signal generated by the switching control signal generator and generate an input offset voltage. Each chopper operational amplifier includes a differential amplifier including an input transistor pair and a current mirror transistor pair, of which the electrical positions can be reserved when the switching control signal is switched between a first state and a second state, wherein the offset voltage, which causes the lightness mismatching in a parallel LED circuit, can be cancelled.

Abstract: A system includes a sensing system, a first chopped circuit, a second chopped circuit, and a multiplexer. The sensing system is configured to provide input signals. The first chopped circuit is configured to switch in response to the input signals crossing a first limit and to provide a first output signal that is valid during some chopping phases. The second chopped circuit is configured to switch in response to the input signals crossing a second limit and to provide a second output signal that is valid during other chopping phases. The multiplexer is configured to switch between the first output signal and the second output signal to provide a valid output signal during all chopping phases.

Abstract: Embodiments of switched-capacitor gain stage circuits and methods of their operation are provided. The circuit includes an operational amplifier, parallel sampling capacitors, an offset storage capacitor coupled to an amplifier input, and multiple switches that are configurable to place the gain stage circuit in a sampling state, a gain state, and an output state. In the sampling state, the switches are configured so that a first charge component representing an input signal is stored on the sampling capacitors, and a second charge component representing an amplifier offset voltage is stored on the offset storage capacitor. In the gain state, the switches are configured so that a third charge component representing a finite gain of the amplifier is stored on the offset storage capacitor. In the output state, the switches are configured so that the first, second, and third charge components contribute to an output signal produced at the output node.

Abstract: A system including a sensing system, a first chopped circuit, a second chopped circuit, and a clock generator. The sensing system is configured to provide sensed input signals. The first chopped circuit is configured to provide a switched output signal that switches in response to values of the sensed input signals crossing a limit. The second chopped circuit is configured to provide a high resolution output signal that corresponds to the sensed input signals and has a higher resolution than the switched output signal. The clock generator is configured to provide clock signals that synchronize chopping of the first chopped circuit and the second chopped circuit.

Abstract: A chopper stabilized amplifier may include a modulation circuit that performs a digital conversion on an input signal so as to convert the input signal into a first modulated signal by using a modulation signal, the modulation signal being a rectangular wave having a predetermined frequency, an operational amplifier circuit that amplifies the first modulated signal so as to convert the first modulated signal into a second modulated signal, and a demodulation circuit that performs analog conversion on the second modulated signal so as to convert the second modulated signal into an output signal by using a demodulation signal, the demodulation signal having a waveform that corresponds to the differences between frequency components of the first modulated signal and the second modulated signal.

Abstract: Transmitters and waveform generators are provided for ultrasound imaging. Low-voltage transistors are connected in cascode with the high-voltage transistors used to generate the ultrasound pulses. The low-voltage transistors trim the high-voltage transistors, adjusting the drive strength of the high-voltage transistors. By trimming, the rise and fall time of the pulses generated by the high-voltage transistors may be more closely matched.

Abstract: The invention provides a capacitive touching apparatus, which includes at least an equivalent capacitor module, a first comparator, a first reference current generator, a first detection capacitor module and a selection switch module. The equivalent capacitor module receives a periodic driving signal and produces an output voltage according to the driving signal. The first comparator compares the output voltage with a first reference voltage and thereby produces a first comparison result. The first reference current generator produces a first reference current and a second reference current according to a base current, in which the first reference current generator decides whether to respectively output the first reference current and the second reference current according to the first comparison result, and the first reference current is output to the equivalent capacitor module. The first detection capacitor module produces a first detection output signal according to the second reference current.

Abstract: Embodiments for at least one method and apparatus of a wireless transceiver are disclosed. For one embodiment, the wireless transceiver includes a transmit chain, wherein the transmit chain includes a power amplifier. The wireless transceiver additionally includes a receiver chain that is tunable to receive wireless signals over at least one of multiple channels, wherein the multiple channels are predefined. Further, the wireless transceiver includes a voltage converter. The voltage converter provides a supply voltage to the power amplifier, and operates at a single switching frequency, wherein the single switching frequency and all harmonics of the single switching frequency fall outside of the multiple channels.

Abstract: An operational amplifier with two pairs of differential inputs for use with an input switch capacitor network. The operational amplifier has reset devices for resetting the second pair of differential inputs while amplifying the first pair of differential inputs, and for resetting the first pair of differential inputs while amplifying the second pair of differential inputs for reducing memory effect in electronic circuits. In an embodiment, the amplifier has an additional reset device for resetting the outputs during a prophase of amplifying the first pair of differential inputs and a prophase of amplifying the second pair of differential inputs.

Abstract: Ripple reduction loop for chopper amplifiers and chopper-stabilized amplifiers. The ripple reduction loop includes a first chopper, a first amplifier having an input coupled to an output of the first chopper, a second chopper having an input coupled to an output of the first amplifier, a second amplifier having an input coupled to an output of the second chopper, a third chopper, an output of the second amplifier having its output capacitively coupled to an input of the third chopper as the only input to the third chopper, a third amplifier coupled as an integrator having an input coupled to an output of the third chopper, an output of the integrator being coupled to combine with the output of the first amplifier as the input of the second chopper, and at least one Miller capacitor coupled between an output of the second amplifier and the input of the second amplifier. Various embodiments are disclosed.

Abstract: Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed.

Abstract: A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

Abstract: A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

Abstract: A system comprises a switched capacitor amplifier including an operational amplifier (opamp). A switching circuit comprises a first switch connected across inputs of the opamp. A second switch is connected across outputs of the opamp. An overdrive detect circuit communicates with the first and second switches and selectively shorts the inputs and the outputs of the opamp when the input voltage is greater than a first predetermined overdrive voltage or when the input voltage is less than a second predetermined overdrive voltage.

Abstract: A system including a sensing system, a first chopped circuit, a second chopped circuit, and a clock generator. The sensing system is configured to provide sensed input signals. The first chopped circuit is configured to provide a switched output signal that switches in response to values of the sensed input signals crossing a limit. The second chopped circuit is configured to provide a high resolution output signal that corresponds to the sensed input signals and has a higher resolution than the switched output signal. The clock generator is configured to provide clock signals that synchronize chopping of the first chopped circuit and the second chopped circuit.

Abstract: A semiconductor apparatus includes a signal source 7 that outputs a signal of predetermined frequency, a frequency divider 15 that receives the output signal of the signal source and is capable of switching the output signal to two or more frequency division ratios, a delta-sigma modulator 16 that controls the frequency division ratio of the frequency divider, and a bandpass filter 17 that receives an output of the frequency divider. The frequency of the input signal of the frequency divider is divided by the frequency division ratio controlled by the delta-sigma modulator, and quantization noise appearing in the output of the frequency divider generated by the delta-sigma modulator is attenuated with the bandpass filter. The semiconductor apparatus easily can convert a signal output by a single signal source to a signal of predetermined frequency and supply a plurality of signals of predetermined frequency using a simple configuration with reduced chip size.

Abstract: An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.

Abstract: Chopper stabilized operational amplifiers are in common use. One drawback of these amplifiers, however, is that there is an inherent tone present at the chopper frequency. Conventional circuits have attempted to reduce the effects of this tone by using various filtering schemes, such as a notch filter. Here, however, a track-and-hold circuit is used in conjunction with matched amplifiers to compensate for this tone.

Abstract: An apparatus includes a plurality of amplifier stages configured to receive an input voltage and generate an amplified output current. Each amplifier stage includes a transconductance stage configured to receive the input voltage and generate a first intermediate output current. Each amplifier stage also includes an auto-zeroing loop configured to generate a second intermediate output current that at least partially corrects for an offset of the transconductance stage, where the auto-zeroing loop operates at a first frequency. Each amplifier stage further includes chopping circuitry configured to reverse a polarity of the input voltage and a polarity of the amplified output current at a second frequency, where the second frequency is less than the first frequency. Each amplifier stage is configured to operate in auto-zeroing and amplification phases. At least one amplifier stage operates in the auto-zeroing phase when at least one other amplifier stage operates in the amplification phase.

Abstract: Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed.