Abstract: An amplifier (AMP) is provided with a pair of choppers (CHPi,CHPo) in order to reduce the DC-offset and the noise produced by the amplifier (AMP). To obtain an optimal noise reduction the pair of choppers (CHPi,CHPo) operate on a high frequency. As a result the DC-offset cancellation is not optimal because a so-called charge injection of the switches in the pair of choppers (CHPi,CHPo) produces a DC-offset. To overcome this problem the amplifier (AMP) is further provided with further offset cancellation means which are for example formed by a further pair of choppers (CHPfi,CHPfo). This further pair of choppers (CHPfi,CHPfo) operates on a relatively low frequency. The combination of the pair of choppers (CHPi,CHPo) and the further pair of choppers (CHPfi,CHPfo) guarantees an optimal DC-offset cancellation as well as an optimal noise cancellation.

Abstract: A multistage comparator is calibrated to remove quasi-autozero voltages derived from the native comparator offset and autozero switch charge injection offsets. A multistage comparator includes a plurality of series connected amplifiers each having a programmable source, and further including a latch. A calibration method for a multistage comparator includes calibrating the first of a series of amplifiers first for both voltage offset and charge injection errors thereby to remove the quasi-autozero voltage and charge injection offsets.

Abstract: A circuit arrangement for generating an output signal at an output by combining at least a first and a second input signal, includes controllable switches for applying a respective one of the input signals to the output, in which, for the purpose of switching the output from one of the input signals to the other, a first one of the controllable switches is gradually switched from the blocked to the conducting state and a second one of the controllable switches is switched complementarily thereto from the conducting to the blocked state. To implement such a circuit arrangement in such a way that distortions produced by tolerances and inaccuracies in matching the characteristics of the components used for switching can be avoided, while using a small number of components, the controllable switches are switched oppositely to each other between their completely conducting and their completely blocked state with a mutually complementary, gradually changed duty cycle.

Abstract: A differential-mode charge transfer amplifier receives a differential input voltage and produces a proportional differential output voltage. The amplifier includes two CMOS charge transfer amplifiers. The two CMOS charge transfer amplifier share two charge transfer capacitors such that the CMOS charge transfer amplifiers are mirrored about the capacitors. The positive charge transfer capacitor terminal (i.e., the terminal that is precharged to a high voltage) of one CMOS charge transfer amplifier is capacitively coupled to the negative charge transfer capacitor terminal (i.e., the terminal that is precharged to a low voltage) of the other CMOS charge transfer amplifier. In addition, the negative charge transfer capacitor terminal of one CMOS charge transfer amplifier is capacitively coupled to the positive terminal of the other CMOS charge transfer amplifier. The amplifier has a significantly increased common-mode rejection, significantly reduced voltage amplification error, and an increased linearity range.

Abstract: In a pulse generator, a sawtooth-shaped wave generator circuit generates a sawtooth-shaped wave by charging and discharging a capacitor. The sawtooth-shaped wave is fed to a comparator that performs pulse-width modulation on it in accordance with the voltage it receives via a terminal and thereby produces pulses. The comparator has its output grounded through a transistor that is turned on with appropriate timing by the sawtooth-shaped wave generator circuit. Thus, the maximum duty factor of the output pulses is made equal to the duty factor of the sawtooth-shaped wave.

Abstract: A switched capacitor voltage amplifier having at least one signal input, at least one reference input, an output and a plurality of clock inputs, comprising a high voltage gain (e.g.

Abstract: A plurality of low-voltage, series-connected input dc-dc converters provide the input to a low-frequency, high-voltage dc-ac output bridge converter suitable for driving a gradient coil in an MRI system. The relatively low-voltage, series-connected dc-dc converters, or choppers, control the gradient coil current, while the dc-ac converter bridge steers the current to the proper coil polarity. A binary weighting of the voltage ratings of the input choppers results in the lowest voltage unit doing most of the high-frequency switching. Such an amplifier configuration is modular and allows for different gradient coil requirements to be met with a common approach by applying a predetermined number of choppers and bridges.

Abstract: An amplifier circuit for amplifying a difference between first and second input signals which is capable of precharge a node at which the second input signal is present thereby enhancing the speed of operation. The circuit includes a first amplifier stage and a capacitor having one terminal coupled to the amplifier stage input. Switching circuit, typically in the form of various transistor switches, operates to switch the first input signal to the second terminal of capacitor. The amplifier stage output is then coupled to the second node thereby charging the node to a voltage approximately equal to input signal voltage. The second input signal is then coupled to the precharged second node. Assuming that the second signal magnitude is related to the magnitude of the first input signal, as it would be in certain Analog-To-Digital Converter applications, the second signal will be able to rapidly change the voltage from the first input signal voltage level to the second input voltage level.

Abstract: The chopping frequency driving a chopper-stabilized amplifier (CSA) is dynamically varied between an upper and lower frequency limit to reduce the intermodulation distortion, clock noise and low-frequency noise found in prior art designs. The upper limit is set to accommodate the settling times required by the CSA's memory capacitors, and the lower limit is set to a non-zero frequency significantly greater than DC to reduce low frequency noise. The two limits permit IMD and clock noise to be widely scattered and enable a near optimum trade off between IMD and chopping noise on one hand, and low frequency noise on the other. The chopping frequency is preferably generated digitally with a loadable counter which divides down a fixed frequency master clock, with the binary value presented at the counter's load inputs periodically varied to dynamically vary the division ratio and thus frequency modulate the chopping frequency.

Abstract: A switched capacitor amplifier useful in integrated circuits and capable of low power operation, wherein the amplifier comprises at least one first hold capacitor, at least one second hold capacitor, a transconductance amplifier, first switching circuit for either (a) allowing the first hold capacitor to retain an input voltage, or (b) outputting retained input voltage through the transconductance amplifier, and a second switching circuit for either (a) feeding a voltage obtained by reversing the polarity of voltage retained by the second hold capacitor back to the transconductance amplifier for outputting as output voltage, or (b) allowing voltage retained by the first hold capacitor to be held by the second hold capacitor.

Abstract: An amplifier circuit having a reset capability for use in analog-to-digital converter comparator stages and the like. First and second amplifier stages include first and transistor second switches, respectively, which are coupled between the amplifier inputs and outputs. A capacitor is coupled intermediate the output of the first amplifier stage and the input of the second amplifier stage. A third transistor switch is coupled between the output of the second amplifier stage and the output of the first amplifier stage. In an initialize state, a switch controller operates to render the first and second switches conductive and the third switch non-conductive. In a typical application, this will cause a charge to be stored on the capacitor indicative of any offset between the virtual grounds of the amplifier stages. In a reset state, the third switch is conductive and the first and second switches are made non-conductive.

Abstract: Circuitry in an amplifier (1) provides both auto-zeroing of offset errors and finite gain compensation. The circuitry includes a differential main amplifier (3) and a differential auxiliary amplifier (13). During a first phase (.phi.1), a previously sampled input voltage is amplified by the main amplifier to produce an output voltage on a first capacitor (C3). A stored prior offset correction voltage stored on a second capacitor (C4A) is applied between the inputs of the auxiliary amplifier, an output of which is coupled to an auxiliary input of the main amplifier to auto-zero its offset voltage. During a second phase (.phi.2) the inputs of the main amplifier are short-circuited together, causing it to produce a voltage change on one terminal of the first capacitor (C3), the other terminal of which is switched from ground to one terminal of a second capacitor (C4). This stores updated offset correction voltage on the second capacitor (C4).

Abstract: To minimize noise generation a chopper switch for a chopper stabilized operational amplifier includes a balanced bridge circuit with two pairs of high-side and low-side transistors connected in parallel. The transistors are not turned completely off but operate in the manner of variable resistors between a high-resistance level and a low-resistance level. One or more additional transistors are include to provide a parasitic capacitance in the break-before-make interval when all of the other transistors are turned off. To provide rail-to-rail operation, complementary circuits contain N-channel and P-channel transistors are connected in parallel between the input and output terminals of the chopper switch.

Abstract: A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.

Abstract: An AM-modulated carrier signal is converted to a lower carrier frequency through mixing with a square wave local oscillator signal. A field-effect transistor chops the modulated signal according to the square wave signal so that a chopped or sampled version of the modulated signal is created without passing the signal through a semiconductor junction. A filter then selects the desired mixing product. Thus, a distortion free mixing of the signal is obtained using low cost components including a JFET switch and a square wave output from a microcontroller.

Abstract: A monolithic microwave semiconductor integrated circuit including a bias stabilizing circuit of a current mirror type formed of a bias control transistor formed of an enhancement mode compound semiconductor field effect transistor and a biased transistor formed of an enhancement mode compound semiconductor field effect transistor.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: A sample and hold circuit to reduce hold error when analog data is held and transferred. The circuit includes a plurality of capacitors and inverters for guaranteeing level, selectively holds an input voltage at one capacitor by a first switching means, transfers charged voltage to a second capacitance by a second switching means and reduces data transfer time.

Abstract: A discrete-time signal processing system includes a signal sampling circuit controlled by a sampling signal generator in which a clock signal is derived from an oscillation signal having a higher frequency by means of a switchable frequency divider which is driven by a sigma-delta modulator. By alternately switching from one dividend n to the other dividend n+1 and vice versa, an effective dividend m, where n.ltoreq.m.ltoreq.n+1, is realized, so that a very fine frequency tuning can take place. The use of the .SIGMA.-.DELTA. modulator is advantageous in that the frequency spectrum of the sampled signal is not corrupted by the frequency spectrum of the sampling signal (clock signal) generated by way of the switching frequency divider.

Abstract: A signal integration circuit having a first MOSFET including a drain connected to a power source and a gate connected to a plural number of the first capacitances in parallel; and an input means connected to each capacitance; in which each input means comprises; the second MOSFET whose source is connected to the first capacitance through a resistance, which receives an input pulse signal, and whose gate is grounded through the second capacitance, and the third MOSFET whose source is connected to a gate of the second MOSFET, whose drain is connected to a power source, and whose gate receives a pulse signal for setting weight; a gate of the first MOSFET receiving a reference saw-tooth signal, a source of the first MOSFET grounded through the third capacitance, and an output pulse signal being output from this source of said first MOSFET.

Abstract: An improved back gate switched sample and hold circuit includes a sample and hold channel including a sample switch having a back gate and a storage element; a back gate circuit for controlling the back gate of the sample switch; and a first attenuator circuit for scaling the input signal from a low impedance source for delivery to the sample switch and a second attenuator circuit responsive to the input signal from the low impedance source to independently drive the back gate circuit and isolate any distortion of the input signal in the back gate circuit from affecting the input signal in said sample and hold channel.

Abstract: A pulse shaping circuit of the clock stretcher/chopper type which is sufficiently simplified to be included on an integrated circuit chip with other circuits without significantly reducing the chip area on which such other circuits may be formed achieves a fast recovery time by developing differential delays in response to each of two different characteristics of a signal input to a delay line. Pulse stretching is accomplished by a latch circuit and pulse chopping is accomplished by a delay arrangement which controls the latching action and the output signal. The delay arrangement may also be made programmable. By controlling the latching and the output signal in response to the delay line, a wide range of duty cycles of input and output signals may be accommodated, even at extremely high frequencies.