Abstract: A controller capable of detecting input power and generating a protection signal for a power converter, including: a high voltage start-up pin for connecting with an output terminal of an external start-up circuit; a sample-and-hold circuit for periodically sampling a voltage signal at the high voltage start-up pin to generate a detected signal; a brownout detector for generating a first power-fault signal according to the detected signal; an AC-off detector for generating a second power-fault signal according to the detected signal; and an OR gate having a first input end coupled with the first power-fault signal, a second input end coupled with the second power-fault signal, and an output end providing a third power-fault signal.

Abstract: A server system and controlling method for an operation timing after being powered up are disclosed. The sever system controls a reset signal to have a voltage lower than a first voltage value by introducing a voltage monitoring module when a work power lower than a voltage threshold. On the other hand, when the work power voltage increases to higher than the voltage threshold of the voltage monitoring module, the voltage monitoring module controls the reset signal voltage to be higher than a second voltage value, whereby achieving in a technical efficacy of stable initialization and reset of the server.

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage bias to a second delay circuit, wherein the voltage bias controls a delay of the second delay circuit, and to update the voltage bias at an update rate. The delay system also comprises an update controller configured to adjust the update rate of the first delay circuit. For example, the update controller may adjust the update rate based on timing requirements of a memory interface incorporating the delay system. The update rate may be reduced when the timing requirements are more relaxed to reduce power, and may be increased when the timing requirements are tighter.

Abstract: A high voltage start-up circuit with adjustable start-up time, wherein, the drain electrode of the first NMOS transistor is connected with a first terminal of the first resistor, a gate electrode of the second NMOS transistor and a negative terminal of the diode; a source electrode of the first NMOS transistor, together with a positive terminal of the diode, is connected to the power ground; a drain electrode of the second NMOS transistor, together with a second terminal of the first resistor, is connected with a port SW of a chip; a source electrode of the second NMOS transistor, together with a first terminal of the second resistor, is connected with a power port VDD of the chip. The circuit can adjust the start-up time and the restart time of the chip flexibly.

Abstract: A device for controlling a power-on reset signal can include a constant current source, for controlling a reference current that is independent of a supply voltage, and a trip point detector circuit driven by the reference current. The trip point detector circuit detects when the supply voltage of the device exceeds a first trip point voltage, and de-asserts the power-on reset signal when the supply voltage exceeds the first trip point voltage. The first trip point voltage can be controlled by a sum of a threshold voltage of a first n-type metal-oxide-semiconductor transistor, a voltage drop across a first resistor, and a threshold voltage of a first p-type metal-oxide-semiconductor transistor. The device may further include a hysteresis circuit, for detecting when the supply voltage falls below a second trip point voltage and causing the trip point detector circuit to reassert the power-on reset signal.

Abstract: A reconfigurable DC-DC converter including a controller is disclosed which automatically adjusts the mode of operation (buck mode or boost mode) depending on the system requirements and is able to achieve the maximum efficiency and the lowest inductance current. The method of switching between buck and boost mode allows the converter to operate to 100% duty cycle for buck mode and 0% duty cycle for boost mode. This maximizes efficiency since the buck-boost mode of operation is eliminated and improves the stability and reliability of the system. A converter output voltage is processed and compared to a control voltage to generate buck and boost comparator output signals. The buck and boost comparator output signals are provided to control logic, which generates switch control signals, which are provided to the DC-DC converter to establish buck mode, boost mode, or pass-through mode.

Abstract: A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.

Abstract: A power-on reset circuit of one embodiment includes first and second power supplies, first and second detecting circuit, a differentiation circuit, a current mirror circuit and a latch circuit. The second power supply is generated from a voltage of the first power supply and supplies a voltage lower than the first power supply. The first detecting circuit detects rise of a voltage of the second power supply. A current corresponding to a change in potential of the first power supply flows through the differentiation circuit. The current mirror circuit multiplies the current flowing through the differentiation circuit. The second detecting circuit senses stoppage of output current of the current mirror circuit and detects completion of the rise of the voltage of the first power supply. The latch circuit is reset by an output signal of the first detecting circuit and set by an output signal of the second detecting circuit.

Abstract: Methods, devices and circuits are provided for power-on-reset circuits with low static power consumption. One such circuit includes a detector that draws current from a supply voltage. The detector detects that the supply voltage has exceeded a trip-point voltage level and then disables current draw from the detector. The detector responds to an enable signal by enabling current draw from the detector. A pulse generator generates a reset signal in response the supply voltage transitioning from a voltage below the trip point voltage level to above the trip point voltage level. A monitor detects that the supply voltage has dropped and provides, in response thereto, the enable signal to the detector to enable current draw from the portion of the detector.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a depletion mode transistor coupled to a power supply and a current path coupled with the depletion mode transistor in series to provide a current to charge a capacitor. The current path has a first resistance during a first stage, such as when the circuit initially receives power, and has a second resistance during a second stage when the capacitor is charged to have a predetermined voltage level.

Abstract: A system having a power on reset circuit including a voltage divide), a multiplexer coupled to two outputs of the voltage divider, a first comparator coupled to the multiplexer and a reference, a logic gate coupled to the first comparator, a second comparator coupled to one of the two outputs of the voltage divider, and an emulation gate coupled to the second comparator.

Abstract: A power management circuit for integrated circuits operating systems where the power supply may be marginal includes a supply voltage characterization circuit and a clock synthesis circuit. The supply voltage characterization circuit determines the strength of the supply voltage applied to the IC and provides information to the synthesis circuit that is used to adjust the clock frequency of the IC to insure the IC does not draw too much current and force the IC into reset. A counter is used to determine the time between when the supply voltage reaches a first level and a second higher level, the time being representative of the slope of the supply voltage. Knowledge of the characteristics of a portion of the circuit under certain operating or benchmark conditions may be used to adjust the characterization.

Abstract: A power-up circuit of a semiconductor apparatus using a plurality of external power voltages is configured to determine a stableness of the plurality of external power voltages through relative comparison of the plurality of external power voltages, and to activate a power-up signal.

Abstract: Embodiments described herein relate to a device operable to process input for a picture password for proof of knowledge. In some embodiments, the device includes a display, an input subsystem, processor(s), and memory containing instructions executable by the processor(s) such that the device is operative to display, on the display of the device, an image for the picture password proof of knowledge. The image is associated with an overlaid grid comprising a plurality of elements, and each element corresponds to a distinct area of the image. The device is further operative to, determine an offset to be used and, in response to receiving an input via the input subsystem at a first location of the display, highlight an element of the overlaid grid at a second location on the first image on the display. The second location is offset from the first location by the offset.

Abstract: A power supply circuit and display apparatus, comprising power source (1), charging/discharging module (2), detecting module (3), the detecting module detects detecting parameter on power-supply path, feeds back corresponding mode signal to the power source according to the detected detecting parameter, and outputs preset operation voltage to load (4); the power source receives the mode signal fed back from the detecting module, outputs power supply voltage corresponding to the mode signal, and charges the charging/discharging module when the mode signal is the low power signal; and the charging/discharging module is discharged to the detecting module when the power source outputs the supply voltage corresponding to the high power signal, and is charged when the power source outputs the supply voltage corresponding to the low power signal.

Abstract: A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Abstract: A reference voltage generating device including a reference voltage source, a charge supplying source, a first switch, a second switch, a charge storage unit and a logic unit is provided. First terminals of the first and second switches are respectively coupled to the output terminal of the reference voltage source and the charge supplying source. When a power on reset signal is received, the first switch is turned off and the second switch is turned on, such that the charge supplying source quickly charges the charge storage unit. When the output voltage is greater than or equal to the reference voltage, the first switch is turned on and the second switch is turned off, such that the reference voltage source maintains the output voltage to the reference voltage.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) power switching circuit and a method for operating a CMOS power switching circuit are described. In one embodiment, a CMOS power switching circuit includes a voltage selection circuit configured to output the highest output voltage between an output voltage of a primary power supply and an output voltage of a backup power supply and a control circuit configured to connect a load circuit to either the primary power supply or the backup power supply by comparing the output voltage of the primary power supply with a power supply switchover level that is set as a function of the highest output voltage. The backup power supply serves as a voltage reference to set the power supply switchover level only when the output voltage of the primary power supply is lower than the output voltage of the backup power supply. Other embodiments are also described.

Abstract: A power on reset circuit including: a startup circuit keeping an operation signal in an operating state during a power supply rises; a bias circuit keeping the operation signal in the operating state; a BGR circuit being activated during the operating state, and outputting a fixed voltage after a predetermined time elapses; a power supply divided voltage generation circuit outputting a reference voltage; an activation detection circuit generating a control signal which becomes inactive when a power supply rises and becomes active when the fixed voltage reaches a predetermined level; a comparator circuit outputting a power on signal and detecting as the power on signal when the reference voltage is greater than the fixed voltage; and a switch turning on and fixing an output of the comparator circuit to an inactive logical value while the control signal is inactive, and turning off while the control signal is active.

Abstract: A microcontroller has a plurality of peripherals, and at least one control bit, wherein the control bit controls a reset of at least one peripheral such that in a first mode any type of reset resets the at least one peripheral of said plurality of peripherals and in a second mode only a power supply reset resets the at least one peripheral.

Abstract: Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.

Abstract: A leakage-current start-up reference circuit is provided which includes a reference circuit unit, a trigger unit, a leakage-current generator and a disable control unit. The trigger unit includes a first transistor. The drain terminal of the trigger unit is connected to a start-up terminal of the reference circuit unit. The leakage-current generator includes a second transistor which is a gate-drain-tied transistor. The disable control unit includes a third transistor. The gate terminal of the disable control unit is connected to a control terminal of the reference circuit unit. The drain terminal of the leakage-current generator, the gate terminal of the trigger unit and the drain terminal of the disable control unit are joined at a node. The reference circuit unit is started up by the trigger unit to generate a reference current. A leakage-current start-up reference circuit having a current mirror is also provided.

Abstract: In a semiconductor integrated circuit having a power domain and a mechanism for a power supply shutoff, when a power supply to the power domain is started, if a clock for an initialization operation is supplied in a state where a voltage to the power domain is unstable, power consumption during the initialization operation increases. Thus, the clock for the initialization operation of the power domain is supplied after detecting that the voltage supplied to the power domain is stabilized.

Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.

Abstract: A power-supply device has a first power supply circuit adapted to generate from an input voltage a first output voltage and a second power supply circuit adapted to generate from the first output voltage a second output voltage. The second power supply circuit monitors the first output voltage to check if it is higher than a first threshold voltage, and also monitors the first power-supply circuit to check if it has started operation for generating the first output voltage, so that the second power supply circuit stays on stand-by, even when the first output voltage is higher than the first threshold voltage, until the first power supply circuit starts operation for generating the first output voltage.

Abstract: In some embodiments, a reset circuit for an electronic circuit equipped with a backup power capacitor includes a first detector arranged to detect a predetermined first voltage of the backup capacitor, a second detector arranged to detect a predetermined second voltage of the backup capacitor, the second voltage being lower than the first voltage, and a controller arranged to control an output of a reset request signal based on detection results of the first detector and the second detector. The controller is configured to output the reset request signal when the first detector detects the first voltage after the second detector detected the second detector.

Abstract: Provided is a wheel speed sensor interface. The wheel speed sensor interface includes: a speed pulse detection circuit configured to receive a plurality of sensor signals including wheel speed information of a vehicle, detect a plurality of speed pulses on the basis of the plurality of the received sensor signals, and transmit the plurality of the detected speed pulses to an external device; and a comparison speed detection circuit configured to generate a plurality of counting values by counting each of the detected speed pulses, generate comparison speed information by multiplexing the plurality of the generated counting values through a time division method, and transmit the generated comparison speed information to the external device.

Abstract: Embodiments of the invention include an IC that includes a core used for ordinary operation and a thin power circuit. The thin power circuit can be configured to use very little power. The IC can also include a digital interface and a connection thereto. The IC can initiate transition to low power mode during which the core and various I/O pads can be shut down. However, the thin power circuit can be kept powered up. The thin power circuit can monitor the digital interface for a predefined wake up signal. When the wake up signal is detected, the thin power circuit can power up the core and any powered down I/O pads. The thin power circuit can also include a dedicated power on reset (POR) cell. This POR cell can be distinct than other POR cells used for the IC and can be specifically designed to for efficient operation.

Abstract: An internal voltage generation circuit including a drive control signal generator and an internal voltage driver. The drive control signal generator generates a drive control signal in response to an active pulse signal and a drive signal. The internal voltage driver, electrically coupled to the drive control signal generator, divides a level of an internal voltage signal in response to the drive control signal to generate a division voltage signal, compares a level of the division voltage signal with a level of a reference voltage signal to generate the drive signal, and drives the internal voltage signal in response to the drive signal.

Abstract: A control logic unit generates a control signal which is activated while a power supply normally operates. A charge circuit is connected to a first node on a voltage control line supplied with a voltage generated by a voltage generation circuit, so that its capacitive element is charged with electric charge. A first discharge circuit is connected to a charge storage node of the charge circuit and discharges the stored electric charge when the control signal is activated. A second discharge circuit discharges the first node when the charge storage node has a potential exceeding a predetermined potential.

Abstract: An electronic circuit includes an illustrative low voltage CMOS power on reset circuit. The electronic circuit can comprise a power on reset circuit coupled between a supply voltage terminal and a signal node. The illustrative power on reset circuit comprises a voltage detector coupled to the supply voltage terminal which is configured to track CMOS thresholds and deactivate when supply voltage reaches a level for proper operation of CMOS logic.

Abstract: A switching circuit may include: the switching circuit includes a switching circuit unit including a first transistor and a second transistor connected to each other in series, the second transistor receiving a first control signal through a control terminal thereof, and an inverter connected between a control terminal of the first transistor and a first terminal of the first transistor. The inverter receives a second control signal and maintains a gate-source voltage level of the first transistor to a threshold voltage level of the first transistor or less, and levels of the first and second control signals are logically complementary to each other.

Abstract: An external circuit is connected to a polarity detection terminal of a switching control IC. An increased value of the voltage of a pulse signal input to the polarity detection terminal at the time of the activation of a power supply changes in response to this external circuit. Accordingly, owing to the external circuit connected to the polarity detection terminal, the validity/invalidity of a standby mode is set. When the standby mode is validated, a blanking frequency changes in response to the voltage of a feedback terminal, and a switching loss in a light load is reduced. Accordingly, a switching control circuit and a switching power supply apparatus are configured that are able to set the validity/invalidity of the standby mode or select the method of the standby mode without using a dedicated terminal.

Abstract: An integrated power-on reset circuit comprises a resistor and a capacitor, wherein the resistor is arranged to pass a current by quantum tunneling in order to charge the capacitor.

Abstract: A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage.

Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

Abstract: A semiconductor device comprises a plurality of circuit blocks, each of which performs an assigned operation, and performs a reset operation when recovering from a shutdown state of power supply, and a power control unit configured to control power supply to a power domain comprising at least one circuit block. The reset operation parameters of the plurality of circuit blocks as reset operation targets, for which power supply is resumed by the power control unit, are controlled so as to meet a power condition that makes the power dissipation of the semiconductor device by the reset operation not more than a predetermined power.

Abstract: There is provided an integrated circuit controlling a power supply, the integrated circuit including: an HV pin obtaining startup power; a voltage dividing unit connected to the HV pin; and an input voltage detecting unit detecting an input voltage through voltage distribution by the voltage dividing unit. The integrated circuit may be capable of reducing manufacturing costs by omitting a separate voltage sensing pin.

Abstract: A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area.

Abstract: This document discusses, among other things, apparatus and methods for a detection circuit. In an example, the detection circuit can include a voltage divider configured to receive a first supply voltage from an external device coupled to the detection circuit, first and second transistors configured to receive a control voltage from the voltage divider and to couple an output to ground when the control voltage exceeds a first threshold, and a bias circuit configured to bias the first transistor to set the first threshold.

Abstract: A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.

Abstract: A low power State Retention Power Gating (SRPG) cell has a retention component and a non-retention component, and is operable in a run state, a first retention state, and a second retention state. In the run state, the retention and non-retention components are powered with a supply voltage. In the first retention state, the retention component is powered at the same supply voltage as in the run state, and the non-retention component is powered down. In the second retention state, the retention component is powered at a lower supply voltage than in the run state, and the non-retention component is powered down.

Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.

Abstract: An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

Abstract: A system method of initializing operation of a semiconductor device including detecting de-assertion of an external reset signal while the semiconductor device in a reset state, monitoring a temperature level of the semiconductor device, and while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level, keeping the semiconductor device in the reset state and asserting at least one operating parameter on the semiconductor device at an elevated level to generate heat on the semiconductor device, and releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level. The operating parameter may be clock frequency or supply voltage level or a combination of both. Different elevated clock frequencies and/or different minimum operating temperature levels are contemplated.

Abstract: An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output pin of the integrated circuit. The integrated circuit includes a latch that is coupled between the analog-to-digital converter and the storage component. The latch is arranged to open when the comparison circuit trips, such that, when the comparison circuit trips, the storage component continues to store a digital value such that the digital value corresponds to the voltage associated with the power supply signal when the comparison circuit tripped.

Abstract: An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.

Abstract: An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.

Abstract: A voltage reset method may include: acquiring a voltage that is changed with time by using an input photon; determining a timing for resetting the acquired voltage by using time information in a period where the acquired voltage increases; and/or resetting the acquired voltage on a basis of the determined voltage reset timing. A voltage reset apparatus may include: an acquisition unit configured to acquire a voltage that is changed with time by using an input photon; a determination unit configured to determine a timing for resetting the acquired voltage by using time information in a period where the acquired voltage increases; and/or a reset unit configured to reset the acquired voltage on a basis of the determined voltage reset timing.

Abstract: According to one embodiment, a first pull-down transistor, a mode switching circuit, and a leak-cut circuit are provided. The first pull-down transistor pulls down an input/output terminal. The mode switching circuit controls on and off of the first pull-down transistor based on an enable signal. The leak-cut circuit turns off the first pull-down transistor when a power supply of the mode switching circuit is shut down.