Abstract: Power-on reset circuits and methods for providing a power-on reset signal are provided. A first branch is configured to receive the power supply voltage. The first branch comprises a first current generator configured to generate a first current having a positive relationship with a power supply voltage. A second branch receives the power supply voltage and comprises a second current generator that is configured to generate a second current. A relationship between the first and second currents indicates whether the power supply voltage exceeds a threshold voltage of the power-on reset circuit. A current comparator circuit compares the first current to the second current and generates an output based on the comparison. The power-on reset signal is asserted when the output indicates that the second current is greater than the first current.

Abstract: A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

Abstract: A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.

Abstract: The present disclosure relates to an image display apparatus including a battery and a method for controlling the same, and the image display apparatus, which receives an input signal for channel selection from an external input device, comprising: an antenna; a tuner for selecting a broadcast signal corresponding to a specific channel, among signals received through the antenna, on the basis of the input signal and converting the selected broadcast signal into an image signal; a display unit for outputting an image associated with the specific channel by using the converted image signal; a power supply unit which includes a battery, charges the battery while electric energy from the outside is received and supplies power to the display unit using the electric energy received from the outside; a power failure detection unit for detecting whether power failure corresponding to a cut off of the electric energy supplied from the outside occurs; and a control unit for supplying power to the display unit using the

Abstract: A mobile power supply terminal and a power supply method is presented. For the mobile power supply terminal, a trigger circuit and a control circuit are added to a conventional device. After a to-be-charged device is connected to the mobile terminal, one end of a power supply interface generates a level signal, to make the trigger circuit generate a trigger signal; and then the control circuit controls, according to the trigger signal, the mobile power supply terminal to enter a power supply mode, and controls a power supply source to charge the to-be-charged device using the power supply interface.

Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

Abstract: The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

Abstract: A method of operating a power up circuit is disclosed. The method includes receiving an input voltage and creating a plurality of sample voltages from the input voltage. One of the sample voltages is selected and compared to a reference voltage. The power up circuit produces a brown-out signal in response to the step of comparing.

Abstract: A particular apparatus includes a magnetic tunnel junction (MTJ) device and a transistor. The MTJ device and the transistor are included in a comparator that has a hysteresis property associated with multiple transition points that correspond to magnetic switching points of the MTJ device.

Abstract: A reference voltage generating device including a reference voltage source, a charge supplying source, a first switch, a second switch, a charge storage unit and a logic unit is provided. First terminals of the first and second switches are respectively coupled to the output terminal of the reference voltage source and the charge supplying source. When a power on reset signal is received, the first switch is turned off and the second switch is turned on, such that the charge supplying source quickly charges the charge storage unit. When the output voltage is greater than or equal to the reference voltage, the first switch is turned on and the second switch is turned off, such that the reference voltage source maintains the output voltage to the reference voltage.

Abstract: A Schmitt trigger circuit having an input coupled to a current summing junction. A trickle current source generates a trickle current applied to the current summing junction. A bandgap current source generates a bandgap current applied to the current summing junction (wherein the bandgap current is fixed when a supply voltage exceeds a threshold). A variable current source generates a variable current applied to the current summing junction (wherein the variable current varies dependent on the supply voltage). At the current summing junction, the variable current is offset against the trickle and bandgap currents with respect to generating a voltage that is sensed at the Schmitt trigger circuit input.

Abstract: A semiconductor device for controlling a power-up sequence is provided. The semiconductor device includes a plurality of chips. Each of the chips includes a power-up sequence controller configured to differently control generation sequences of internal source voltages. The power-up sequence controller changes the generation sequences of the internal source voltages in response to a power stabilization signal which is generated according to an external source voltage applied thereto in powering up the semiconductor device. Accordingly, a power-up current which is generated according to the internal source voltages being generated has a peak current distribution where a peak current may be equally distributed.

Abstract: A voltage supply circuit for an electronic circuit includes a switch configured to selectively connect a supply input of the electronic circuit with a main supply voltage source. An auxiliary voltage supply unit has an auxiliary voltage output coupled to the supply input of the electronic circuit. The auxiliary voltage supply unit is configured to at least temporarily output an auxiliary voltage to the supply input. The auxiliary voltage has a voltage level lower than a voltage level of a main supply voltage supplied by the main supply voltage source.

Abstract: A microprocessor comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event, determine if at least one reset condition has been met upon detection of the reset event, and cause at least a part of the microprocessor to remain in a reset state upon determining that the at least one reset condition has been met.

Abstract: A control device includes: an input unit to which a first signal is input from a detection unit detecting an operation for an opening-closing body; and a control unit generates a second signal for operating the opening-closing body, based on the first signal, wherein the control unit can be switched between a first power consumption mode and a second power consumption mode in which less power is consumed, and the control unit can be switched between a first state where the second power consumption mode is switched to the first power consumption mode, based on a first condition, and a second state where the second power consumption mode is switched to the first power consumption mode, based on a second condition on which the second power consumption mode is less likely to be switched to the first power consumption mode.

Abstract: A circuit can include a signal section that includes a first signal transistor configured to operate in a subthreshold region to maintain the signal node at about VCC as VCC rises from a low level; a high threshold section that enables a current path from the signal node to the low power supply node only after a voltage at the detect node exceeds a level greater than a threshold voltage (Vt); and an output section having transistors with relatively long channels, for reduced crowbar current.

Abstract: A circuit is provided, the circuit including: a first power supply terminal connected to a first p-type metal oxide semiconductor transistor; a second power supply terminal connected to a second p-type metal oxide semiconductor transistor; an output node connected between the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor; and a decision circuit connected to the first power supply terminal and the second power supply terminal, wherein the decision circuit is powered by the output node and wherein gate terminals of the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor are complementarily and actively controlled by the decision circuit.

Abstract: The present disclosure provides a semiconductor circuit including: a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied; an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain; a constant current source connected to the first drain; and an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied.

Abstract: An initialization signal generation device may be provided. The initialization signal generation device may include a power supply circuit configured to provide one of an external voltage and an internal voltage in response to an initialization signal. The initialization signal generation device may include an initialization signal generator configured to sense the level of the voltage outputted from the power supply circuit and generate the initialization signal.

Abstract: A start-up circuit for a bandgap reference circuit include an operational amplifier and a diode coupled to a second input terminal of the operational amplifier. The circuit includes a first current branch including a first transistor and a second transistor in series, for generating a first current in response to an output voltage at an output terminal of the operational amplifier and a second current branch including a third transistor and a fourth transistor in series, for generating a second current in response to the output voltage. The circuit further includes a resistor coupled in parallel to the fourth transistor, an inverter coupled to a connection node between the third and fourth transistors, for inverting a voltage at the connection node and generating an inversion voltage, and a fifth transistor for controlling a switching element flowing a reference current proportional to the voltage with the negative temperature coefficient in response to the inversion voltage.

Abstract: There is described a driver circuit for a single wire protocol slave unit, the driver circuit comprising (a) at least one current mirror comprising a first transistor (MP1, MN3) and a second transistor (MP2, MN4), wherein the gate of both transistors is connected to a bias node (PBIAS, S2BIAS), and wherein the second transistor is adapted to conduct a mirror current (I2, IOUT) equal to a current (I1, I2) conducted by the first transistor multiplied by a predetermined factor, (b) a bias transistor (MP3, MN5) for selectively connecting and disconnecting the bias node to and from a predetermined potential (VDD, GND) in response to a control signal (ABUF, AN), and (c) a current boosting element for providing a boost current (I1P, I2P) to the bias node for a predetermined period of time when the control signal causes the bias transistor to disconnect the bias node from the predetermined potential. There is also described a universal integrated circuit card device comprising a driver circuit.

Abstract: A low power reset circuit includes a bias generator for receiving an operating voltage generated by a power supply and generating a bias voltage in response to the received operating voltage. The operation speed of a shaper for generating a shaped signal for indicating the operating voltage and the operation speed of a comparator for comparing a threshold reference voltage with the shaped signal are both controlled in response to the generated bias voltage. The comparator also generates a comparison signal for indicating a result of the comparison. In response to the comparison signal, a reset signal generator generates a reset signal for resetting protected circuitry powered by the operating voltage generated by the power supply.

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

Abstract: Described is a processor comprising: a plurality of radiation detectors; a first logic unit to receive outputs from the plurality of radiation detectors, the logic unit to generate an output according to the received outputs, the output of the first logic unit indicating whether the processor was exposed to incoming radiations; and a second logic unit to receive the output from the first logic unit, and to cause the processor to perform an action according to the output from the first logic unit.

Abstract: A semiconductor device includes: an internal voltage generation block suitable for generating an internal voltage based on first and second external voltages whose power-up sections are different from each other; and a control block suitable for fixing the internal voltage to a predetermined voltage level during a control section including a first power-up section of the first external voltage and a second power-up section of the second external voltage.

Abstract: An integrated circuit device comprises a system reset controller. The system reset controller includes a clock signal input, a reset signal input, a clock signal output, and a reset signal output. The system reset controller is arranged to receive distributed clock and reset signal inputs and output modified clock and reset signal outputs such that asynchronous reset inputs in downstream system components can be replaced by logic elements not requiring asynchronous reset inputs with no change in externally-visible behavior except the length of reset sequences as measured by clock pulses.

Abstract: An electronic device is configured to perform a power cycle reset in response to a change in charging power applied to the device. The device includes an electrical load with a microprocessor, a battery, a charging circuit that receives power from an external power source and uses the received power to charge the battery, and a control circuit that regulates the power cycle reset operation. The power supply circuit selectively uses the battery to power the device by coupling the load to a power supply path and discharges the load by coupling the load to a discharge path. The control circuit receives, from the charging circuit, an indication of a change in power applied to the charging circuit and responsively generates a control signal and applies the control signal to the power supply circuit, which causes the power supply circuit to temporarily couple the load to the discharge path.

Abstract: A bias generator may include: an operational amplifier, a resister string, and a control circuit. The operational amplifier includes a first input terminal suitable for receiving a bandgap reference voltage, a second input terminal with an offset voltage and an output terminal. The resister string includes at least one resister coupled between a ground terminal and the output terminal of the operational amplifier, suitable for generating bias voltages. The control circuit is coupled between the second input terminal and the resister string, swaps the offset voltage, and selectively provides the offset voltage and the swapped offset voltage to the second input terminal of the operational amplifier.

Abstract: A power-on-reset (POR) circuit for a system-on-chip (SOC) includes a biased switching element having a source, drain, and gate, with the source being connected to a supply voltage and the drain and gate being connected to a control line. The POR circuit further includes a first delay switching element having a source connected to a reduced supply voltage, a gate connected to the control line, and a drain, and an inverter having an input and an output, with the input being connected to the drain of the first delay switching element. The inverter includes a first CMOS inverter coupled between the supply voltage and a reference voltage. A first capacitor is coupled between the inverter input and the reference voltage. A second capacitor coupled between the inverter input and an output of the first CMOS inverter.

Abstract: An apparatus and method for initializing electrical devices based on a voltage level. The voltage level may be modified to a particular setting based on the availability of power supply components, such as AC to DC rectifiers. Depending upon the availability of the power supply components, a control system may alter output voltage to a particular level. The components receiving power may be coupled to voltage dividers, where the voltage dividers are configured to modify an input voltage to cause or prevent the input voltage from rising above an initialization level for the particular component. The output voltage may be set by the control system such that a number of components that experience a voltage rise above an initialization threshold correspond to the number of available power supply components.

Abstract: Described is an apparatus which comprises: an input for providing a first voltage signal; a level translator, coupled to the input, to translate the first voltage signal to a second input voltage, the second input voltage having a voltage level higher than a voltage level of the first voltage signal; and an open loop reference core coupled to the level translator, the open loop reference core to receive the second input voltage and to generate an output indicating whether the first voltage signal is above or below a reference level.

Abstract: Provided herein is a power on reset circuit including a voltage dividing unit suitable for dividing an external power supply voltage according to a resistance ratio to output a divided voltage, a signal generating unit suitable for outputting a power on reset signal when the divided voltage has a set level or higher, and a resistance adjusting unit suitable for adjusting the resistance ratio of the voltage dividing unit in response to the power on reset signal.

Abstract: A power-on reset circuit includes a voltage detector unit to output an electrical signal in response to a power supply voltage received from a power supply terminal, an inverter to output a reset signal according to a level of the electrical signal from the voltage detector unit, a first switch unit to be turned on or off in response to the reset signal from the inverter; a first discharge unit to discharge the electrical signal in response to the power supply voltage from the first switch unit, a second switch unit to be turned on according to a start pulse signal from an external device and to receive the power supply voltage from the power supply terminal, and a second discharge unit to discharge the electrical signal in response to the power supply voltage from the second switch.

Abstract: A power drop detector circuit includes a detect element, for coupling to a first source voltage, for detecting a voltage level of the first source voltage, and a memory element coupled to the detect element and switchable between a first memory state and a second memory state based on the voltage level of the first source voltage.

Abstract: An integrated circuit (IC) and associated method support using a pre-use configuration for determining an initial/preferred operational mode for the IC from plural operational modes that may be entered following power-up cycles of the IC. The initial/preferred operational mode can be determined after the design phase of the IC so that, during IC operation, wasted power or delay are not incurred by first requiring that the IC power up in a default operational mode and subsequently run executive code to reprogram the IC to enter an operational mode that is preferred for the application for which the IC is being used by the IC integrator/user. The configurations determine clock frequencies and/or power levels for core processing and/or peripheral modules and allow the same IC design/die to be targeted to a spectrum of different power usage/performance applications by the integrator/user.

Abstract: By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.

Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.

Abstract: A power optimization device and method thereof for energy harvesting apparatus are disclosed. The power optimization device includes a charge pump, a voltage comparator, an output switch, a counter and a frequency control module. By detecting the voltage outputted from the power optimization device under various operating frequencies to obtain a calculation result and increase or decrease an operating frequency of the charge pump according to the calculation result, so as to dynamically adjust the operating frequency to optimize the power outputted from the power optimization device according to the voltage outputted from the energy harvesting apparatus to an electricity storage unit and energy loss caused by the change of the operating frequency.

Abstract: Disclosed are a power on reset circuit, a power on reset method and an electric device using the same. In the power on reset circuit and method, a first voltage detecting circuit and a second voltage detecting circuit detect the voltage of a power supply and output a first voltage signal and a second voltage signal respectively. A logic circuit receives the first voltage signal and the second voltage signal to turn no or off the first voltage detecting circuit for detecting the voltage of the power supply. Specifically, merely when the voltage value of the power supply is less than a rising threshold voltage value of the first voltage detecting circuit or a falling threshold voltage value of the second voltage detecting circuit, the first voltage detecting circuit is turned on to detect the voltage value of the power supply.

Abstract: A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.

Abstract: A method and flow for implementing an ASIC using sub-threshold technology with optimized selection of voltage and process for a given application performance. An embodiment may also implement concurrently used multiple voltage domains inside a single place and route block. The voltage domain is dynamically changed between the cells at the placement time based on the timing path requirements.

Abstract: A power supply monitoring circuit for monitoring a voltage at a power supply node compared to a reference node, the power supply monitoring circuit comprising a first field effect transistor and first and second voltage dropping components arranged in current flow communication between the power supply node and the reference node and each having first and second nodes, and wherein a first node of the first voltage dropping component is connected to one of the first and second nodes of the field effect transistor, and a gate of the field effect transistor is connected to the second node of the first voltage dropping component, and an output signal is taken from a connection made with the first field effect transistor.

Abstract: A power-up signal generation circuit includes a control signal generation unit suitable for generating first and second control voltages based on a power-up signal, a level tracing voltage generation unit suitable for generating a level tracing voltage whose voltage level varies based on the first and second control voltages, and a power-up signal generation unit suitable for generating the power-up signal based on the level tracing voltage, and providing a feedback on the power-up signal to the control signal generation unit.

Abstract: A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area.

Abstract: A circuit for generating a bias current is provided, including: a loop unit, which includes a first current mirror structure constituted by a first PMOS transistor and a second PMOS transistor, and a second current mirror structure constituted by a first NMOS transistor and a second NMOS transistor, where the first and second NMOS transistors operate in a sub-threshold region; an output unit, adapted to output the bias current; and an amplifying unit, which includes a first input terminal and an output terminal, where the first input terminal is connected with a source of the first NMOS transistor or a source of the second NMOS transistor, and the output terminal is connected with gates of both the first and the second PMOS transistors. The bias current output from the circuit may be not sensitive to temperatures.

Abstract: A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).

Abstract: Various implementations described herein are directed to an integrated circuit for power-on-reset detection. The integrated circuit may include a first stage configured to receive an input voltage signal and provide a triggering signal during ramp of the input voltage signal. The integrated circuit may include a second stage configured to receive the triggering signal from the first stage and provide an output voltage signal during ramp of the input voltage signal via gate leakage through at least one transistor.

Abstract: The present invention discloses a method for backing up data in a case of a power failure of a storage system including: when a power failure is detected, acquiring current refresh progress of a buffer in a storage system, an address, in the buffer, of data that is in the buffer and needs to be backed up to a non-volatile memory in the storage system, and a first time required for backing up the data; calculating, according to the current refresh progress of the buffer and the address of the data in the buffer, a second time for which the data can at least keep being not lost since a last refresh; and stopping refreshing the buffer, and backing up the data to the non-volatile memory, if the second time is greater than the first time.

Abstract: A scaled voltage supply to supply voltage biases to circuits in voltage zones. The scaled voltage supply includes a master voltage corresponding to a voltage drop across a master-upper rail having a voltage Vdd and a master-lower rail having a voltage Vss=0. Further, the supply includes a voltage-divider network dividing the master voltage Vdd into intermediate voltages ?Vdd, ?Vdd, etc., wherein ? and ? are predetermined constants. These intermediate voltages scale with the master voltage and are supplied to the voltage zones using non-invasive soft rails. In one implementation the soft rails use voltage mirrors to supply the intermediate voltages to the circuits within voltage zones.

Abstract: A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.