Abstract: A welding device includes a laser irradiation unit that irradiates a workpiece with a laser light while scanning along an intended weld line of the workpiece, an upper jig arranged on a side of the laser irradiation unit with respect to the workpiece, and a lower jig arranged on an opposite side of the laser irradiation unit side. The upper jig includes an exposed portion that exposes the intended weld line of the workpiece to the laser irradiation unit side, an introduction path that is disposed in a downstream side in a scanning direction of the laser light and introduces an inert gas to the exposed portion, and a discharge path that is disposed in an upstream side in the scanning direction of the laser light and suctions the inert gas introduced to the exposed portion to discharge the inert gas to an outside.

Abstract: The present disclosure relates generally to semiconductor devices, and, in particular, to monitoring circuitry configured to monitor a signal for an overcurrent, undercurrent, overvoltage, and/or undervoltage condition. The monitor circuit may utilize pull down transistors to generate a local voltage level. The local voltage level is then used to generate an indication of whether the monitored value has diverged from an operating region and/or has crossed a threshold of operation.

Abstract: It is presented a power converter for transferring electric power provided on an input terminal to an energy storage element. The power converter comprises: an inductor; a switch connected to selectively control a connection between the inductor and the input terminal; and a comparator, wherein an output of the comparator controls the switch, a first input of the comparator is supplied with a voltage being proportional to a voltage of the input terminal, and a second input of the comparator is supplied with a voltage being proportional to a current from the input terminal; wherein the energy storage element is connected to a point between the inductor and the switch.

Abstract: A power on and power down reset circuit includes a reference voltage generation module, a monitoring voltage generation module, and a voltage comparator. The reference voltage generation module is utilized to generate a reference voltage with a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistance, and a second resistance. The monitoring voltage generation module is utilized to generate a monitoring voltage. The voltage comparator is utilized to generate a reset voltage by comparing the reference voltage to the monitoring voltage. Thus, the power on and power down reset circuit can achieve the effect of power savings and decreasing error rate of the reset voltage.

Abstract: According to one embodiment, a memory system is disclosed. The system includes a nonvolatile memory, a controller which controls the nonvolatile memory and to which a first voltage is supplied, and a circuit to which first and second signals from a host device are input, or the first signal is not input and the second signal is input from the host device, when the memory system is connected to the host device. The circuit converts a second voltage of the second signal into the first voltage when the first and second signal have the second voltage and the second voltage is lower than the first voltage, and does not convert a voltage of the second signal into the first voltage when the first signal is not input and the voltage of the second signal is the first voltage.

Abstract: Provided is a reference voltage circuit including a Zener diode having a cathode connected to a current source via a first node, and an anode connected to a ground point; a first resistor having one end connected to the first node; a second resistor having one end connected to another end of the first resistor; a first diode having an anode connected to another end of the second resistor via a second node, and a cathode connected to the ground point; and a current control circuit configured to generate a control current corresponding to an anode voltage of the first diode so that the current source supplies a reference current corresponding to the control current to the first diode.

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.

Abstract: Systems, devices, and methods are provided for enabling turbo mode for static random access memory (SRAM) devices. A cell circuit is coupled between a bit line pair and configured to perform read or write operations of a memory device. A sense amplifier circuit is coupled between the bit line pair and configured to sense a voltage differential between the bit line pair. A tracking circuit includes a tracking bit line (DBL) and is configured to monitor operation of the cell circuit and send a sense amplifier enable signal to the sense amplifier at a predetermined frequency rate based on a voltage level of the DBL. A turbo circuit is coupled to a turbo signal and configured to modify the voltage of the tracking bit line enabling sending of the sense amplifier enable signal at a rate faster than the predetermined frequency rate.

Abstract: A power-supply detection-circuit control method is a method for a first microcomputer to control operation of a power-supply detection circuit, the first microcomputer being connected to the power-supply detection circuit and controlling a fan motor, the power-supply detection circuit detecting a voltage to be applied from a power supply to the fan motor, wherein the first microcomputer switches the power-supply detection circuit between an operating state and a non-operating state on the basis of information indicating whether a predetermined condition is satisfied.

Abstract: As a scanning line drive circuit of a display device, a shift register having a configuration in which a plurality of unit circuits are connected to each other in multiple stages is used. The unit circuits each include: a plurality of control transistors; an internal node connected to a terminal of one of the plurality of control transistors; and a depletion mode initialization transistor having a first conduction terminal connected directly or through a resistor to the internal node, a second conduction terminal, and a control terminal. One of a power supply voltage and a ground voltage is applied to the second conduction terminal, and the other voltage is applied to the control terminal. The initialization transistor is turned on in a power-off state.

Abstract: An information handling system includes an identification resistor, calibration circuitry, and a system-on-a-chip (SOC). The SOC sets the calibration line to a first digital state to place the calibration circuitry in an inventory mode. While the calibration circuitry is in the inventory mode, the SOC determines an inventory amount of time to charge the capacitor to a voltage substantially equal to a threshold voltage. The SOC then sets the calibration line to a second digital state to place the calibration circuitry in a calibration mode. While the calibration circuitry is in the calibration mode, the SOC determines a calibration amount of time to charge the capacitor to the voltage substantially equal to the threshold voltage. The SOC determines a resistance of the identification resistor based on the inventory amount of time and the calibration amount of time. The SOC also determines bit strapping information corresponding to the determined resistance.

Abstract: A voltage detection circuit includes a first transistor and a first resistor connected in series between a power supply voltage node and a reference voltage node, a second transistor and a second resistor connected in series between the power supply voltage node and the reference voltage node, a third transistor and a third resistor connected in series between the power supply voltage node and the reference voltage node, and a signal generator that outputs a signal corresponding to a voltage of a connection node between the third transistor and the third resistor. The second transistor is first turned on among the first to third transistors and a voltage level of the power supply voltage node increases, turning off the third transistor, and then a current flows through the first transistor and the first resistor. When the third transistor is turned on, the signal generator changes a logic of the signal.

Abstract: A power-on reset signal generating device includes a reference voltage generator, a signal driver, and a stabilization circuit. The reference voltage generator generates a power-on reference voltage based on a voltage level of a power supply voltage. The signal driver drives the power-on reference voltage to generate a power-on reset signal. The stabilization circuit receives the power-on reset signal to keep a voltage level of the power-on reference voltage staying during a predetermined amount of time.

Abstract: A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function (Vtp, Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp, Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.

Abstract: A power sequence monitoring system is disclosed, and comprises: a microprocessor and a control module. The microprocessor comprises a first conversion unit and a second conversion unit. The first conversion unit is used for converting a power-on signal received from a power management chip to a first digital signal, and the second conversion unit is adopted for converting a power-off signal received form the power management chip to a second digital signal. After receiving the first digital signal and the second digital signal from the microprocessor, and the control module outputs a plurality of power monitoring data to an electronic device, such that a user easily knows the power signal state of the host computer by the system of the present invention.

Abstract: A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

Abstract: An electronic device includes an interface with a first terminal, a second terminal, and a power supply. A voltage divider includes series-connected resistors, between the first terminal and ground voltage. A first programmable fuse is provided and the voltage divider converts the first signal to a different voltage level according to the state of the first programmable fuse. A first transistor has a gate receiving the converted first signal and a second transistor has a gate electrically connected to the second terminal and a source-drain terminal of the first transistor. The second transistor is off when the first transistor is on. A fuse-type switching element is connected between the power supply terminal a power supply circuit. A control terminal of the fuse-type switching element is connected to a source-drain terminal of the second transistor switches conduction state according to whether the second transistor is on or off.

Abstract: The present disclosure discloses a shift register and a driving method therefor, a gate drive circuit, and a display device. An input circuit is configured to respond to a signal of an input signal end and provide a signal of a first reference signal terminal to a first node; a reset circuit is configured to respond to the signal of the second node and provide a signal of a second reference signal end to the first node; and an output circuit is configured to respond to the signal of the first node and provide the signal of the clock signal end to an output signal end and is configured to respond to the signal of the third node and provide the signal of the second reference signal end to the output signal end.

Abstract: A device (1) for delivering a signal switching from a first state to a second state, comprising: a primary circuit (4) generating a primary signal; and a secondary circuit (6) configured to: when the primary signal is initialized to the second state upon power-up, initialize a ring counter (16) to a random value in a finite sequence including a reference value, change the value of the first ring counter (16) by running through the first finite sequence in a circular fashion, and deliver at an output (3): i) a secondary signal in the first state, when the value of the first counter is different from the reference value, and ii) the primary signal, when the value of the first counter is equal to the reference value.

Abstract: An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a transistor and a diode. The transistor includes a first gate region electrically coupled to a gate driver, and a first source region and a first drain region on two sides of the first gate region. The diode includes two terminals coupled between the first drain region of the transistor and a reference voltage. The transistor has a threshold voltage greater than that of the diode.

Abstract: The disclosure provides a multi-voltage chip, including a regulator circuit, a high-voltage domain controller, a low-voltage domain controller, and a digital logic circuit. The regulator circuit receives and responds to a feedback signal, a regulating start signal, and a reference voltage to convert a system high voltage into a regulated voltage. The high-voltage domain controller receives a power signal and the system high voltage to provide the reference voltage and the regulating start signal. The low-voltage domain controller is coupled to the high-voltage domain controller and receives the regulated voltage to provide a system start signal in response to the regulating start signal. The digital logic circuit is coupled to the regulator circuit to receive the regulated voltage and provide the feedback signal, and is coupled to the low-voltage domain controller to operate in response to the system start signal.

Abstract: A power-on-reset (POR) circuit includes an NFET branch and a PFET branch. The NFET branch includes: an n-channel field effect transistor (NFET) having a first threshold voltage; and a first quiescent bias current source coupled between a supply terminal and the NFET. The PFET branch includes: a p-channel field effect transistor (PFET) having a second threshold voltage; and a second quiescent bias current source coupled between a ground terminal and the PFET. The POR circuit is configured to provide a POR signal at an output terminal based on: the first threshold voltage or the second threshold voltage, whichever is larger; and a voltage margin. The output terminal is coupled between the PFET branch and the second quiescent bias current source.

Abstract: A circuit for generating a protection signal and a protection apparatus are provided. The circuit includes: a first flip flop, wherein the first flip flop is configured for receiving an enabling signal and an external signal input to the first flip flop and outputting a first level according to the enabling signal and the external signal; a second flip flop, wherein the second flip flop is in connection with the first flip flop and the second flip flop is configured for outputting a protection signal according to the first level and the external signal; and a feedback device, wherein the feedback device is connected between an output terminal of the second flip flop and an input terminal of the first flip flop and the feedback device is configured for outputting the enabling signal.

Abstract: A memory device includes a memory array powered between a virtual supply and virtual ground nodes. A dummy memory array is powered between first and second nodes. A virtual supply generation circuit generates a virtual supply voltage at the virtual supply node as a function of a first control voltage. A virtual ground generation circuit generates a virtual ground at the virtual ground node as a function of a second control voltage. A first control voltage generation circuit coupled between the first node and a power supply voltage generates the first control voltage as tracking retention noise margin (RNM) of the memory array, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between the second node and ground generates the second control voltage as tracking RNM of the memory array, the second control voltage rising as the RNM decreases.

Abstract: A circuit that includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

Abstract: An electronic device includes a starting circuit configured to compare a value representative of the power supply voltage with a threshold, wherein the circuit includes a generator of a current proportional to temperature.

Abstract: A power-on reset (POR) circuit includes first, second and third resistors. A first transistor has a first control terminal and first and second voltage terminals. A second transistor has a second control terminal and third and fourth voltage terminals. A third transistor has a third control terminal and fifth and sixth voltage terminals. The first control terminal is coupled via the first resistor to the second voltage terminal. The third voltage terminal is coupled via the second resistor to the first voltage terminal. The second control terminal is coupled via the third resistor to the fourth voltage terminal. The third control terminal is coupled to the third voltage terminal. The fifth voltage terminal is coupled to the first control terminal. A voltage buffer is coupled to the fifth voltage terminal.

Abstract: A switching control circuit that controls switching of a switching device of a bridge circuit for driving a load. The switching control circuit includes a control circuit that outputs, on a signal line, a control signal at first and second logic levels for turning on and off the switching device based on a set signal and a reset signal, respectively, a setting circuit that is connected to the signal line, and that sets the logic level of the signal line to the second logic level for a period after the reset signal is inputted to the control circuit and before the set signal is inputted to the control circuit, a holding circuit that is connected to the signal line, and that holds the logic level of the signal line, and a drive circuit that is connected to the holding circuit, and that drives the switching device based on the output of the holding circuit.

Abstract: A power-on clear circuit includes a bias current generation circuit having one end connected to a first line supplied with a first power supply voltage, the other end connected to a second line kept at a fixed potential, and configured to generate a bias current, and to transmit the bias current to a first node; a first transistor having a first terminal connected to the second line, a second terminal connected to the first node, and a control terminal for receiving application of a second power supply voltage which varies to follow the first power supply voltage; an inverter unit configured to operate on the basis of the first power supply voltage, and to which a potential of the first node is input; and a signal outputting unit configured to output a power-on clear signal in accordance with an output of the inverter unit.

Abstract: An image generator is configured to generate display light. A first waveguide is configured to generate wide-field image light from a first portion of the display light. A first outcoupling element of the first waveguide extends to a boundary of the frame to provide the wide-field display to substantially all of the augmented FOV of the user. A second waveguide is configured to generate inset image light from a second portion of the display light received from the image generator.

Abstract: A system can include a voltage generator configured to generate a reference voltage, a power-up voltage, and a replicated voltage based on a power supply voltage. The system can further include a logic sub-component coupled to the voltage generator and configured to output a reset signal based on a comparison of the reference voltage to the power-up voltage and an indication that the reference voltage that has entered a steady state and is reliable as a measurement with respect to a voltage level of the power supply voltage. The indication can be determined based on a comparison of the replicated voltage to a particular threshold voltage level.

Abstract: Circuits and methods for providing at least a startup voltage for reversed-operation unidirectional power converters or bi-modal power converters sufficient to power at least an auxiliary circuit of such power converters while the normal supply voltage to at least the auxiliary circuit is insufficient to enable operation of the auxiliary circuit. Embodiments of the invention utilize an initial startup charge pump circuit to create a suitable startup voltage while the normal supply voltage to the auxiliary circuit is less than a specified voltage VMIN. Embodiments of the present invention also provide additional benefits, including small size since the initial startup charge pump circuit omits the use of an inductor, and high efficiency since the initial startup charge pump circuit may be disabled when the normal supply voltage to the auxiliary circuit is equal to or greater than VMIN.

Abstract: A semiconductor device includes a latch signal generation circuit and a training result signal generation circuit. The latch signal generation circuit latches a first internal control signal and a second internal control signal to generate a first latch signal and a second latch signal. The first internal control signal is generated based on a first internal clock signal and a control signal, and the second internal control signal is generated. The training result signal generation circuit is synchronized with a first alignment pulse and a second alignment pulse generated based on the first latch signal and the latch signal, thereby generating a training result signal from the first and second latch signals.

Abstract: A power on ready (POR) signal generating apparatus and an operation method thereof are provided. The POR signal generating device includes a detection circuit and a control circuit. The detection circuit detects a target voltage. When the target voltage is ready, the detection circuit sets a POR signal to a ready state. The control circuit is coupled to the output terminal of the detection circuit to receive the POR signal. After the POR signal transitions from a not ready state to the ready state, the control circuit maintains the POR signal in the ready state, and the control circuit disables the detection circuit.

Abstract: A comparing circuit and a comparing module with hysteresis are provided. The comparing module includes a first resistor, a second resistor, and the comparing circuit, which are electrically connected to each other. A comparison voltage is determined according to an input voltage and the resistances of the first resistor and the second resistor. The comparing circuit includes an input circuit, an eternal circuit, and a coupling module. The coupling module includes a first coupling transistor, a second coupling transistor, a third transistor, and a fourth coupling resistor. Control terminals of the first coupling transistor and the second coupling transistor are selectively electrically connected to either one of a first terminal and a second terminal. The second terminals of the third coupling transistor and the fourth coupling transistor are selectively electrically connected to either one of the first terminal and the second terminal.

Abstract: An oscillator apparatus includes an oscillator circuit and a protection circuit. The oscillator circuit has an input and an output for generating a clock signal. The protection circuit is coupled to the input or the output of the oscillator circuit and is used for generating a second power switch control signal to the input of the oscillator circuit according to a signal edge of the clock signal and a first power switch control signal which is provided to the oscillator apparatus, to protect circuit element(s) included within the oscillator circuit.

Abstract: A switch-mode power supply and control circuitry that reduces variation in the switching frequency of the power supply with changes in loading. In one example, a switch-mode power supply includes an inductor, a transistor, and control circuitry. The transistor is coupled to the inductor, and configured to charge the inductor. The control circuitry is coupled to the transistor. The control circuitry is configured to turn off the transistor for a first time period. The first time period is a function of voltage across the inductor during the first time period. The control circuitry is also configured to determine whether the switch-mode power supply is operating in continuous conduction mode or discontinuous conduction mode. The control circuitry is further configured to add a predetermined fixed interval to the first time based on the switch-mode power supply operating in discontinuous conduction mode.

Abstract: A power supply voltage monitoring circuit includes a power supply switching circuit, a series circuit including a first series resistor connected to an input power supply line, a second series resistor connected to a ground potential, and a third series resistor connected between the first series resistor and the second series resistor, a first parallel circuit including a first switching element and connected in parallel to the first series resistor, a second parallel circuit including a second switching element and connected in parallel to the second series resistor, a first determination circuit configured to determine whether a first divided voltage between the first series resistor and the third series resistor is in a normal range, and a second determination circuit configured to determine whether a second divided voltage between the second series resistor and the third series resistor is in a normal range.

Abstract: Level-shifting circuits including a plurality of p-type metal oxide semiconductor (PMOS) devices and n-type metal oxide semiconductor (NMOS) devices may be used to level-shift an input voltage signal between a low voltage domain having a low voltage level and a high voltage domain having a high voltage level, to obtain an output voltage signal having an output voltage level at an output node. A current-controlled tie circuit may be connected between the output node and the output voltage level, to conduct a current that causes the output node of the level-shifting circuit to be in a pre-defined logic state during a power-up sequence of the level-shifting circuit. Accordingly, spurious, non-deterministic output levels are avoided during the power-up sequence.

Abstract: A reset circuit includes: an output circuit that outputs a reset release signal for releasing reset of a reset target circuit that is to be applied with a power supply voltage, when a first voltage that rises with a rise in the power supply voltage reaches a first reference voltage that rises with a rise in the power supply voltage until the first reference voltage reaches a target level; and an inhibit circuit that inhibits the reset release signal from being output to the reset target circuit until the power supply voltage reaches a third level, the third level being higher than a first level at a time when the first reference voltage exceeds the first voltage, the third level being lower than a second level at a time when the first voltage reaches the target level.

Abstract: A timing controller resetting circuit including: a resistor connected to an output node from which a reset signal is output and a first voltage source which supplies a first voltage; a capacitor connected to the output node and a second voltage source which supplies a second voltage that is lower than the first voltage; a reference voltage source configured to generate a reference voltage that is lower than the first voltage and higher than the second voltage; a comparator including a first input terminal which receives the first voltage, a second input terminal which receives the reference voltage, and an output terminal which outputs a comparison result signal generated by comparing the first voltage with the reference voltage; and a transistor including a first terminal which is connected to the output node, a second terminal which receives the second voltage, and a gate terminal which receives the comparison result signal.

Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.

Abstract: Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage.

Abstract: A circuit device has a first mode in which the circuit device outputs a clock signal and a second mode in which the circuit device does not output the clock signal. The circuit device includes an oscillation circuit, a non-volatile memory in which characteristic adjustment data of the oscillation circuit is stored, a reset circuit generating a reset signal, and a storage circuit into which the characteristic adjustment data is loaded from the non-volatile memory when the reset signal transitions from active to inactive. When the circuit device shifts from the second mode to the first mode, the reset circuit causes the reset signal to transition from active to inactive.

Abstract: A comparator circuit is implemented using a simple comparator core having two gain stages integrated in a single circuit block. The circuit operates with improved speed and resolution in comparison to a conventional continuous-time comparator. Offset trimming allows for the crossing time of the comparator to be adjusted close to an ideal crossing time.

Abstract: A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.

Abstract: A tag includes: a housing configured for coupling the tag to a physical object to organize activities regarding the physical object; and coupled to the housing: a wireless communication component; circuitry electrically coupled to the wireless communication component, the circuitry having a reset port and a switch port; a power source electrically coupled to the wireless communication component and the circuitry; a first switch between the power source and the reset port; a second switch between the reset port and ground, the second switch controlled by the switch port; and a capacitor between the reset port and the ground.

Abstract: A semiconductor apparatus includes a first voltage detection circuit configured to generate a first voltage detection signal in response to the voltage level of a first voltage, a current control signal and a second voltage detection signal; and a storage and output circuit configured to generate a power control signal and the current control signal in response to the voltage detection signal.

Abstract: A gate drive circuit includes a signal generation unit configured to generate a first gate drive signal, a signal isolation unit configured to produce, at an output side thereof in response to the first gate drive signal, a second gate drive signal electrically isolated from the signal generation unit, an output stage device configured to receive the second gate drive signal at an input side thereof and to produce a third gate drive signal at an output side thereof in response to the second gate drive signal, a first path connecting the output side of the signal isolation unit and the input side of the output stage device; and a second path connecting the output side of the signal isolation unit and the output side of the output stage device.