Abstract: A dual phase-locked loop (PLL) clock synthesizer is disclosed for generating clock signal in synchronization with the data input signal received over a network environment. The dual PLL clock synthesizer is suitable for processing data streams of any bit sequence without data error caused by interference due to clock signal jittering phenomena. The dual PLL clock synthesizer is particularly suitable for application to high-speed Ethernet network environment such as for decoding to obtain the original data conveyed over the network through selected encoding scheme.

Abstract: A charge pump circuit has a first transistor connected to a first power source and having a control electrode to receive a first control signal; a second transistor connected to a second power source and having a control electrode to receive a second control signal; a third transistor and a current source connected in series between the first and second transistors, a node between the third transistor and the current source providing a signal, which is passed through a low-pass filter to provide a VCO input signal; and a control voltage generator for generating a control voltage according to the VCO input signal and applying the control voltage to a control electrode of the third transistor. This charge pump circuit realizes a stable PLL operation for a wide range of VCO input voltages, has little data rate dependency, and operates at high speed.

Abstract: An effective signal detection circuit for serial transmission apparatuses using bi-phase code is provided, which effective signal detection circuit facilitates reducing variation of characteristics, current consumption, and dimensions thereof. The effective signal detection circuit comprises a shift register further comprising three D-FFs connected in a series input and parallel output circuit; and a determining circuit further comprising an AND element, an NOR element, and a NOR element. A clock pulse having a frequency twice as high as the bit frequency of a bi-phase coded input signal RX is fed to the clock terminals of the D-FFs. The shift register obtains, based on the clock pulse, a parallel signal bundle Q.sub.1, Q.sub.2, Q.sub.3 corresponding to three consecutive half bits of the input signal RX. The parallel signals Q.sub.1, Q.sub.2, Q.sub.3 are input to the input terminals of the AND element and the NOR element connected in parallel.

Abstract: A delay lock loop having an improved delay element which results in a two-fold improvement in the operation of the delay lock loop. Firstly, it guarantees that the phase detector portion of the delay lock loop will yield the correct phase differential. Secondly, it eliminates the possibility of a harmonic lock condition from occurring.

Abstract: A multiple stage tracking filter includes a self-calibrating RC oscillator, a resistor connected to the self-calibrating RC oscillator and a capacitor connected to the self-calibrating RC oscillator. The filter further includes a switched capacitor filter element connected to the self-calibrating RC oscillator. The switched capacitor filter elements include a switch which is controlled by a timing signal from the self-calibrating RC oscillator. A method of filtering a signal includes the steps of operating a self-calibrating RC oscillator to generate a timing signal, tuning a plurality of cascaded filter elements with the generated timing signal and passing a signal through the plurality of tuned cascaded filter elements.

Abstract: A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase.

Abstract: A band-pass filter system comprises a band-pass filter, and a frequency band controller for controlling a frequency band of the band-pass filter by generating a corresponding up pulse voltage and a down pulse voltage according to a pre-controlled center frequency obtained from an output frequency of the band-pass filter to produce a control frequency for obtaining a desired center frequency of the band-pass filter.

Abstract: A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the damping circuit is an digital circuit which generates adequate phase and frequency damping without a damping resistor. Damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.

Abstract: A transceiver integrated circuit including a transmitter section having a phase-locked loop with an oscillator to provide an output at a predetermined transmission frequency, and a receiver section having a phase-locked loop with an oscillator used to provide a recovered clock from an incoming data signal. In a second mode when no incoming data is being received, the receiver oscillator is controlled in accordance with the transmitter oscillator to operate the receiver oscillator at the expected frequency of future data. Therefore, when data is received, the receiver oscillator is at the same approximate frequency as the incoming data thereby enabling fast acquisition by merely adjusting the phase of the receiver oscillator to the incoming data.

Abstract: A timing acquisition circuit using a phase locked loop with programmable damping for either Type A or Type B phase detectors is described. In the damping scheme for a Type A phase detector, a resistance (R1) is simulated by adding an equivalent voltage Veff to the capacitor voltage. The equivalent voltage Veff is generated internally, so that programmable damping is made possible. In Type B phase detectors, a variable gain amplifier is used to control the effective resistance (R1) of the loop filter.

Abstract: In a phase synchronization circuit including a digital phase comparator, a synchronism discrimination circuit, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a frequency-division circuit, the charge pump circuit comprises a level comparator comparing the output voltage of the loop filter with a predetermined reference voltage, for outputting a level discrimination signal, a first AND circuit for outputting a logical product of an output UP of the phase comparator and the level discrimination signal, an inverter for outputting an inverted signal of an output DOWN of the phase comparator, and a second AND circuit for outputting a logical product of an output signal of the inverter and the level discrimination signal.