Abstract: A ballast according to the present invention operates in an ignition state, a warm-up state, and a steady state for igniting and powering a lamp. The ballast comprises an igniter that ignites the lamp during the ignition state and a switching power inverter, for example, a full bridge DC-AC inverter implemented with MOSFET switching transistors, that powers the lamp during the warm-up and steady states. The switching power inverter, which drives the igniter, operates at a first switching frequency during the ignition state and operates at a second switching frequency during the steady state. Preferably, the first switching frequency, which in one exemplary embodiment is in the kHz range, is higher than the second switching frequency.

Abstract: The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS)technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.

Abstract: A differential charge pump circuit has two current paths and generates a differential current in accordance with currents inputted to the two current paths. The two current paths have a pair of current sources respectively and form a differential pair. The differential charge pump circuit has controlling means for detecting an output potential difference between the two current paths and controlling current values of the current sources in accordance with the output potential difference.

Abstract: An output signal is generated with a predetermined phase shift with respect to an input signal using a closed loop control. The input and output signal of the closed loop control are logically combined in accordance with first and second combinatory logic to generate first and second control signals. The first and second control signals selectively activate first and second current sources, respectively. The current supplied by the first current source charges a capacitance controlling the closed loop control, while the current supplied by the second current source discharges the capacitance. By selecting the types of the combinatory logics as well as the ratio of the currents supplied by the first and second current sources, the phase shift of the output signal with respect to the input signal can be variably adapted to individual requirements.

Abstract: A charge pump circuit is provided which outputs a high voltage by using a boosting circuit with a smaller number of stages. A diode is used to give a back-gate voltage for a MOS transistor composing the charge pump circuit, thereby minimizing a reduction in a boosted voltage due to an increase in the threshold voltage of the MOS transistor. In addition, a second MOS transistor is provided between the back gate of the MOS transistor and the ground (GND) such that in-phase clock signals are inputted to the gate of the second MOS transistor and the capacitor thereof.

Abstract: A charge pump is proposed. The charge pump is integrated in a chip of semiconductor material and includes a plurality of capacitive elements each one connected to a corresponding circuit node of the charge pump, the circuit nodes being arranged in a sequence from an input node to an output node, a plurality of field effect transistors each one for selectively connecting a corresponding first circuit node with a second adjacent circuit node, each transistor being made in a corresponding insulated body region, and for each transistor first biasing means for equalizing the body region with the first circuit node when the transistor is closed, wherein for each transistor the charge pump further includes second biasing means for equalizing the body region with the second circuit node when the transistor is opened.

Abstract: A current mirror with selectable filter poles provides a selected low pass filtering function to a DC bias signal generated by the current mirror. Coupled between a first MOSFET and second MOSFET of the current mirror, a low pass filter with selectable filter poles comprises a plurality of resistor-configured MOSFETs coupled to at least one capacitor-configured MOSFET to provide one of a fast settle time and improved filtering for the current mirror in one embodiment of the invention. A first resistor-configured MOSFETs, biased by logic and bias circuitry, provides a low frequency filter pole that provides an improved filtering for the current mirror. A second resistor-configured MOSFET provides a high frequency filter pole that provides a fast charge time to meet a settle time requirement.

Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Abstract: The clock generator of this invention saves a buffer memory for the data transfer interface, which has conventionally been required, when using a spectrum spread clock in circuits and devices inside a system. The clock generator can easily be applied as the operational clock in a system, and enhances the performance of the system. In the clock generator, the variable delay circuit controls the phase of the reference clock generated by an oscillator. The delay setting circuit is able to vary the setting of the control voltage to the variable delay circuit at each clock cycle, and modulates the phase of the reference clock. The phase modulation means of the delay setting circuit fluctuates the cycle of the output modulation clock to thereby spread the spectrum.

Abstract: A charge pump circuit has a charge pump having at least two switched current sources arranged in series. The difference between the currents produced in the two switched current sources contributes to the output current from the charge pump. At least one of the two current sources is controlled by means of a control signal. A control circuit produces the control signal for the at least one controlled current source such that the currents produced in the two current sources are regulated to the same value.

Abstract: The invention includes a phase locked loop which has a voltage-controlled oscillator, a phase comparator and a charge pump. The charge pump is coupled to a setting input of the voltage-controlled oscillator via a loop filter. A feedback input of the phase comparator is connected to the output of the voltage-controlled oscillator via a frequency divider, and the phase comparator is designed to output an actuating signal to the charge pump. The loop filter has a first charge store and at least one tunable element that alters a filter characteristic of the loop filter. In addition, there is a trimming circuit which is coupled to the at least one further element in order to alter the filter characteristic of the loop filter and which is designed to compare a time period for a charging operation in a loop filter with a reference time period.

Abstract: The present invention provides for compensation of leakage charge in a PLL. A first plurality and second plurality of charge pumps has a source charge pump and a sink charge pump, and each charge pump has its own switch. A first node is coupled between at least one source charge pump and at least one sink charge pump. A second node coupled between at least one source charge pump and at least one sink charge pump. A PLL filter is coupled to the first node. A dummy filter is coupled to the second node. A first input of a differential mode sensor is coupled to the PLL filter. A second input of a differential mode sensor is coupled to the dummy filter. A first input of a common mode sensor is coupled to the dummy filter. A second input of a common mode sensor coupled to the PLL filter.

Abstract: In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input and a second control input, wherein the first control input and the second control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump and the second charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

Abstract: A system and method for reducing a transient response in a phase lock loop (PLL) (100) is disclosed. The system includes an adapt mode charge pump (204), a normal mode charge pump (206) and the use of controlled trickle currents (208), (210) applied to those charge pumps to minimize a transient response of the PLL (100).

Abstract: A charge pump and loop filter circuit of a phase locked loop includes a resistor, a capacitor, first and second input current sources for supplying first and second currents to the circuit, a first output current source for outputting the first current from the circuit, and a second output current source for receiving the second current from the circuit. The charge pump also contains a plurality of up pulse switches and down pulse switches for controlling current flow through the circuit such that only a fraction of the current that flows through the resistor flows into and out of the capacitor for charging and discharging the capacitor. The size of the capacitor can be reduced accordingly based on the amount of current used to charge and discharge the capacitor.

Abstract: A phase lock loop circuit 60 has a phase frequency detector 62, a charge pump 64, an active filter 87 and a voltage-controlled oscillator 100. The phase detector generates UP and DN signals indicative of the relative frequency of FR, a reference signal, and FV, a signal controlled by the voltage-controlled oscillator. A charge pump using logic gates (buffer 66 and inverter 68) to produce a voltage drop over resistors 74 and 84 to generate a voltage at a node coupled to the input of transmission gate 76 according to the values of the UP and DN signals. When the transmission gate 76 is closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier 86 of the active filter 86. When the transmission gate is open (high impedance state) the inverting input is electrically isolated from the node.

Abstract: In a parameter correction circuit in an LSI, a reference resistor element with high precision having a resistance value set to a target value is connected to an external terminal of the LSI. A constant current from a mirror circuit connected to a current supply flows through the reference resistor element. A voltage value generated in the reference resistor element is measured by a voltage measuring circuit. The constant current also flows through a variable resistor element. The resistance value of the variable resistor element is adjusted so that a voltage generated in the variable resistor element corresponds to the voltage generated by the reference resistor element.

Abstract: A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A semiconductor device that includes an adaptive phase locked loop with improved loop stability and a faster locking rate. In one embodiment, this is accomplished in a manner that does not require an additional second charge pump for loop stability, and therefore the resulting phase locked loop of the present invention consumes less chip die area. In another embodiment, multiple charge pumps are used and the resulting response time for locking is improved over that which can be achieved by conventional embodiments.

Abstract: In a PLL circuit including a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and the voltage controlled oscillator, wherein one channel processes the useful signal components and the other channel processes the disturbance signal components of the synchronization pulses. Each channel has two tracks, for generation of a potential difference, wherein each track is connected to a capacitor plate.

Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.

Abstract: A charge pump includes a current source capable of generating a reference current. The charge pump also includes a first current mirror capable of conducting a first current. The charge pump further includes a second current mirror capable of conducting a second current and the reference current. In addition, the charge pump includes an output coupled to the first and second current mirrors and capable of providing one of the first and second currents as an output of the charge pump. The first current mirror may be capable of conducting the first current and a second reference current. The second current mirror may be capable of conducting the second current, the reference current, and the second reference current.

Abstract: A synchronization circuit including a plurality of samplers, the plurality of samplers sampling an input signal with a plurality of respective clock signals and producing a plurality of respective sampled output signals. The synchronization circuit also includes at least one phase detector coupled to the plurality of samplers, the at least one phase detector determining whether the plurality of sampled output signals are different and producing at least one control signal, the at least one control signal indicating whether the plurality of sampled output signals are different. In addition, the synchronization circuit includes a delay adjuster coupled to the at least one phase detector, the delay adjuster adjusting a delay of the input signal according to the at least one control signal output by the at least one phase detector.

Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

Abstract: A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic. Moreover, it provides a frequency-scalable circuit that unlike a conventional phase-and-frequency detector (PFD), does not rely on asynchronous elements.

Abstract: The switching time of a phase-locked loop circuit is improved by switching a direct frequency control section, into and out of, the circuit.

Abstract: A method for internally resetting a charge pump is provided that includes receiving an up signal and a down signal simultaneously. A feedback signal is generated based on the up and down signals. The feedback signal is provided internally to the charge pump. The charge pump is reset based on the feedback signal.

Abstract: A CMOS switching circuit that includes a charge reservoir and a multiplexer connected to the charge reservoir. The multiplexer receives control signals from a delay line and a control signal line, and it delivers a switching signal to an output terminal. A first set of signals delivered to the control terminals of the multiplexer causes the charge reservoir to deliver charge to the output terminal, and a second set of signals delivered to the control terminals causes charging of the charge reservoir. With the charge reservoir, charge from falling signals is conserved and used to help rising signals at the output, reducing the power required to provide an output switching signal.

Abstract: A charge pump including a differential pair of transistors for controlling a current at a charge pump output node and a replica bias generator for selectively driving a first transistor of the differential pair of transistors into a fully-on state and a second transistor of the differential pair of transistors into a weak inversion state.

Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

Abstract: A switching control signal generating circuit for reducing glitches from occurring in a charge pump during switching. Additionally, a phase locked loop including the charge pump is provided. The switching control signal generating circuit obtains a time difference in output signals based upon the signals input to the generating circuit. Combining the switching control signal generating circuit with a charge pump reduces glitches during switching. Similarly the jitter in the output signal of a phase locked loop, using the charge pump, can be reduced.

Abstract: A method and apparatus for jitter reduction in a Phase Locked Loop (PLL) that includes determining a size of a original charge pump adequate to generate an appropriate control voltage to a Voltage Controlled Oscillator (VCO) of a PLL based on the charge pump receiving a single up signal or down signal within one cycle of a PLL input reference clock. N number of the up signal or down signal are generated to a second charge pump 1/N the size of the original charge pump. The N number of the up signal or the down signal occurs within one cycle of the PLL input reference clock. The second charge pump generates N second control voltage corrections each being 1/N the amplitude of the appropriate control voltage glitch, thus minimizing glitches on the second control voltages and reducing jitter to the VCO.

Abstract: A dual path frequency synthesizer is disclosed which includes a controlled oscillator and a phase detector that determines the phase difference between an output signal of the controlled oscillator and a reference signal. The synthesizer also includes a charge pump that is coupled to the phase detector. The synthesizer includes a direct path loop filter which is coupled to a charge pump output. The synthesizer also includes an integrating path loop filter which is coupled to another charge pump output and which has substantially the same topology as the direct path loop filter. The direct path loop filter and the integrating path loop filter are substantially matched with one another. The charge pump pumps charge into the direct and integrating path loop filters in response to the phase difference between the reference signal and the output signal of the controlled oscillator as determined by the phase detector.

Abstract: A phase control loop circuit for tuning to a reference frequency signal having a phase lock loop (PLL) circuit being responsive to a reference frequency signal having a reference frequency, said PLL circuit including a voltage control oscillator (VCO) for generating a VCO output, said PLL circuit for generating a PLL output, said phase control loop circuit processing said VCO output to generate an output frequency signal having an output frequency, in accordance with an embodiment of the present invention.

Abstract: A charge pump is disclosed which generates higher and more symmetric source and sink currents that prior designs and reduces the multiple frequency sidebands that occur in a voltage controlled oscillator of a phase-loop synthesizer. Other improvements are the reduction in reference frequency feed-through, charge sharing and noise transient coupling and phase noise in the phase-locked loop. Possible applications include but are not limited to charge pump phase-locked designs for single chip CMOS multi-band and multi-standard radio frequency integrated circuits.

Abstract: A clock recovery circuit for generating an output signal that is synchronized with an input signal. The clock recovery circuit includes a charge pump, a first filter, an oscillator, a switch circuit, and a second filter. When the charge pump operates, the switch circuit will disconnect the first filter from the oscillator. Additionally, when the charge pump stops operating, the switch circuit will connect the first filter and the oscillator such that the oscillator adjusts a frequency or phase of the output signal according to the output voltage of the first filter.

Abstract: A current steering charge pump that receives control signals and sources and sinks current in response to the control signals. One embodiment includes a main current source, secondary current source, main current sink, and secondary current sink, and three different current paths between various of the current sources and current sinks. One embodiment includes buffers operative to maintain the node voltages of central nodes at the same voltage as the output node of the charge pump, where each buffer is coupled between two of the three current paths.

Abstract: A phase-locked loop circuit provides an output signal having a frequency depending on the frequency of a reference signal. The circuit includes a feedback circuit that derives a feedback signal from the output signal, a phase frequency detector that provides a control signal indicative of a phase difference between the reference signal and the feedback signal, a control circuit that controls the frequency of the output signal according to the control signal, and a conditioning circuit that conditions the control signal through a conditioning signal. The conditioning circuit includes a storage circuit that stores energy provided by the control signal and the conditioning signal during a first phase and transfers the accumulated energy to the control circuit during a second phase.

Abstract: A phase locked loop circuit includes a phase comparator and a charge-pump circuit. The phase comparator and the charge-pump circuit are configured to satisfy the relationship of Kp2>Kp1 in an Io??? characteristic, where Kp1 indicates a slope Kp in the case where |??|>??o, Kp2 indicates a slope Kp in the case where |??|???o, Kp being defined by Kp=dIo/d??, and ??o being a constant indicating a predetermined phase error.

Abstract: A circuit for phase detection includes two current sources controlled by a phase detector. One of the current sources has a reference current input that is connectable to a first or second reference current source in response to the phase detector.

Abstract: The present invention is to provide a charge pump circuit for improving switching speed and compensating mismatch between a source and a sink currents flowing to output terminal. A charge pump circuit according to the first embodiment of the present invention comprises a first and second switching elements, a discharging and charging elements, a biasing unit, a first and second compensating unit, a charge pumping unit, a current mirror unit, a control unit, and a biasing unit. The compensating circuit removes the deterioration owing to the parasitic capacitance, and the control circuit controls the charge that is flowed or emitted from the parasitic capacitance. A charge pump circuit according to the second embodiment of the present invention comprises a charge pumping unit, a current mirror unit, a control unit a biasing unit. The charge pump circuit decects the mismatch between the output currents via the control unit, and compensates the mismatch by the biasing unit.

Abstract: A reference signal and a voltage controlled oscillator (VCO) output are compared for relative phase and frequency differences. A lead error signal is generated if the reference signal leads the VCO output and a lag error signal is generated if the reference signal lags the VCO output the lead and lag error may result from a combination for phase and frequency differences between the reference signal and the VCO output. A time window is used to sample the polarity of the lead and lag error signals by incrementing and decrementing a phase error signal. If the phase error signal reaches a threshold value within the time window, a Reset Delta pulse is generated and if the phase error signals does not reach the maximum delta value within the time window a Reset Total pulse is generated. A variable first gain signal is increased on each Reset Delta pulse and decreased on each Reset Total pulse and limited to a value between predetermined maximum and minimum values.

Abstract: A phase lock loop circuit (60) has a phase frequency detector (62), a charge pump (64), an active filter (87) and a voltage-controlled oscillator (100). The phase detector generates signals responsive to reference signal FR and VCO output signal FV. A charge pump generates a voltage at the input of a first transmission gate (76) according to the values of the phase detector signals. A predetermined voltage is generated at the input of a second transmission gate (112). When the transmission gates (76, 110) are closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier (86) of the active filter 86 and the predetermined voltage is applied to the non-inverting input. When the transmission gates are open (high impedance state) the inverting input is electrically isolated from the node and the non-inverting output is isolated from the power supply.

Abstract: A multimode clock recovery circuit for providing constant bit rate services in a cell relay network has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services.

Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a first input to receive a control voltage, one or more second inputs to receive one or more tuning range control signals, and an output to provide an oscillation output signal, a phase detector having inputs to receive the oscillation output signal and a reference signal, a charge pump having an input coupled to the output of the phase detector and having an output to generate the control voltage, a loop filter having an input to receive the control voltage and having a control terminal, and a controller having inputs to receive the control voltage, a high reference voltage, a low reference voltage, and one or more mode signals, and having a first output connected to the control terminal of the loop filter and second outputs to generate the tuning range signals.

Abstract: A structure and associated method for varying an effective capacitance within a phase lock loop circuit. The phase lock loop circuit comprises a first charge pump circuit, a second charge pump circuit, and a loop filter circuit. The loop filter circuit comprises a filter capacitor with a constant capacitance value. The first charge pump circuit is electrically connected to the loop filter. The first charge pump circuit to controls a flow of current for the loop filter. The loop filter provides a voltage for a voltage controlled oscillator. The second charge pump circuit is electrically connected to the loop filter circuit in parallel with the filter capacitor. The first charge pump circuit and the second charge pump circuit vary an effective capacitance value of the filter capacitor.

Abstract: A test circuit for connecting a high-impedance node to an external test point when a test signal is enabled. The test circuit comprises: a first transmission gate switch for coupling the high impedance node to a first internal node of the test circuit when the test signal is enabled, the first transmission gate switch comprising a first N-channel transistor having a drain coupled to the high impedance node, a gate coupled to a Logic 1 when the test signal is enabled, and a source coupled to the first internal node. The test circuit also comprises a second transmission gate switch capable of coupling the first internal node to the external test point when the test signal is enabled and a biasing circuit for generating a negative Vgs bias on the first N-channel transistor when the test signal is disabled to thereby reduce leakage current in the first N-channel transistor.

Abstract: A pulse width modulated common mode feedback technique for a differential charge pump includes averaging the output of a differential charge pump to determine the common mode voltage; generating from the pump up and pump down pulses a set of up source pulses and down source pulses and a set of up sink pulses and down sink pulses and adjusting, in response to a difference between a reference voltage and the common mode voltage, the width of at least one of the sets of source and sink pulses to match the reference common mode voltages.

Abstract: A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

Abstract: A fast acting charge pump is provided which is suitable for use in a locked loop circuit where very short duration first and second adjustment pulses are produced by a phase detector. The first complement of the second adjustment pulses are used to switch the output of the charge pump through respective pairs of switching and associated biasing transistors, while a complement of the first and second adjustment pulses are respectively capacitively coupled to interconnection nodes of the pairs of switching and biasing transistors.