With Variable Delay Means Patents (Class 327/149)
  • Patent number: 10862488
    Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marius Moe, Tarjei Aaberge
  • Patent number: 10812057
    Abstract: A time detection circuit and a time detection method are provided. The time detection circuit includes an input signal processor and a time signal amplifier. The input signal processor receives a first input signal and a second input signal, calculates a time difference value between the first input signal and the second input signal, adjusts the time difference value by comparing the time difference value with a set reference value, and provides the adjusted time difference value. The time signal amplifier receives the adjusted time difference value, and amplifies the adjusted time difference value to generate an amplified time signal. The time signal amplifier operates in a linear operation region between a first time value and a second time value, and the set reference value is set according to the first time value and the second time value.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: October 20, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Pei-Yuan Chou, Jinn-Shyan Wang, Chuen-Shiu Chen
  • Patent number: 10797707
    Abstract: A delay locked loop detection system (10), the system can be used for detecting the working state of a delay locked loop (400) and comprises: a signal generator (300), which is used for generating a reference clock and providing the reference clock to the delay locked loop (400); and a testing instrument (500), which is used for acquiring the clock signals output from the delay locked loop (400) and measuring whether the time delays thereof are consistent with expectations; the detection system (10) further comprises at least one of the following circuits: a pre-receiving circuit (100), which is used for receiving the reference clock from the signal generator (300) and amplifying and shaping the reference clock and then providing the reference clock to the delay locked loop (400); and a multiphase multiplexing circuit (200), which is used for receiving the clock signals output from the delay locked loop (400) and synthesizing and then providing a plurality of clock signals with different delay to the testing
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 6, 2020
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Xueyan Wang, Ying Yang, Jingjia Yu
  • Patent number: 10783940
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 10778233
    Abstract: A method for Phase Locked Loop (PLL) lock detection includes determining a phase error by comparing a feedback phase to a reference phase. A frequency error is determined by comparing a feedback frequency to a reference frequency. A lock signal is determined in response to the phase error being less than an upper phase threshold and greater than a lower phase threshold, and the frequency error being less than an upper frequency threshold and greater than a lower frequency threshold.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: September 15, 2020
    Assignee: NXP B.V.
    Inventor: Ulrich Moehlmann
  • Patent number: 10778405
    Abstract: Disclosed is a clock generating circuit capable of operating in an analog clock data recovery (ACDR) mode to reduce the loop latency or a clock multiplication unit (CMU) mode to suppress reference jitter. The circuit includes a filter and an oscillator. The filter receives an input signal to determine voltages of a first node and a second node respectively and includes a first filtering circuit and a second filtering circuit coupled in parallel between the first node and a reference voltage terminal. The second filtering circuit includes a switch and a capacitor connected in series, wherein the second node is between the switch and capacitor, and the switch is turned off in the ACDR mode and turned on in the CMU mode. The oscillator outputs a clock according to the first node's voltage in the ACDR mode or according to the second node's voltage in the CMU mode.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: September 15, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jian Liu, Weixiong He, Jianing Lou
  • Patent number: 10762937
    Abstract: According to one embodiment, in a semiconductor device, the first pull-up circuit is connected to a third node and to a fourth node. The third node is a node between a drain of the first transistor with a first conductivity type and a source of the second transistor with the first conductivity type. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with a second conductivity type and a source of the second transistor with the second conductivity type.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yohei Yasuda
  • Patent number: 10748586
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 10727826
    Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hun-Dae Choi, Hwa-Pyong Kim
  • Patent number: 10712770
    Abstract: Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: July 14, 2020
    Assignee: XILINX, INC.
    Inventors: Ping-Chuan Chiang, Kee Hian Tan, Arianne B. Roldan, Nakul Narang, Yipeng Wang, Yohan Frans, Kun-Yung Chang
  • Patent number: 10707848
    Abstract: An apparatus for interpolating between a first and a second signal is provided. The apparatus includes a plurality of interpolation cells coupled to a common node of the apparatus. Further, the apparatus includes a control circuit configured to supply, based on a control word, respective selection signals to each of the plurality of interpolation cells. At least one of the plurality of interpolation cells is configured to couple the common node to a first potential if the first signal and the second signal are both at a first signal level, couple the common node to a second potential, which is different from the first potential, if the first signal and the second signal are both at a second signal level, which is different from the first signal level, and to decouple the common node from at least one of the first potential and the second potential if the first signal and the second signal are at different signal levels.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 7, 2020
    Assignee: Apple Inc.
    Inventors: Georgios Palaskas, Sebastian Sievert
  • Patent number: 10680591
    Abstract: An example delay circuit is described that includes an input node to receive a first signal, a first circuit path, a second circuit path, an output buffer, and an output node. The first circuit path includes at least one first buffer and a first array of switches. The second circuit path includes at least one second buffer and a second array of switches. The output buffer receives a mixed output of the first circuit path and the second circuit path. The output node transmits a second signal equivalent to the first signal with a programmed delay.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 9, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Chris Schiller, Adam Johnson
  • Patent number: 10651834
    Abstract: An apparatus of performing a clock skew adjustment between N clock signals. 2(N?1) skew sensors are configured as successive pairs k, each pair k having a first skew sensor and a second skew sensor. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. A skew controller performs the clock skew adjustment based on the first and second information.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
  • Patent number: 10644813
    Abstract: A method and system for time domain calibration to compensate for signal phase impairment in transmit paths in a transmitter configured to drive an antenna array are disclosed. According to one aspect, a base station is configured to compensate for signal impairment in transmit paths feeding an array of antenna elements in which the compensation is performed in the time domain. The base station includes a combiner configured to combine signals output from the transmit paths to form a feedback signal. An impairment estimator is configured to receive the feedback signal and outbound traffic signals and to determine a phase compensation value for each impairment path. A multiplier is provided for each transmit path, the multipliers configured to multiply the outbound traffic signals by respective phase compensation values.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 5, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Neil McGowan, Slim Ben Ghalba, Marthinus Willem Da Silveira
  • Patent number: 10636463
    Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
  • Patent number: 10622981
    Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
  • Patent number: 10623004
    Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dan Shi, Tyler J. Gomm, Michael J. Allen
  • Patent number: 10623044
    Abstract: An apparatus for phase and frequency detection (PFD) includes a first circuit to receive a first input pulse and to generate a first output pulse, the rising edge of which is triggered by a first rising edge of the first input pulse, and a second circuit coupled to the first circuit and configured to receive a second input pulse and to generate a second output pulse, the rising edge of which is triggered by a second rising edge of the second input pulse. The second output pulse has a falling edge carrying first information related to a first rising edge of the first input pulse. The first output pulse has a falling edge carrying second information related to a second rising edge of the second input pulse.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: April 14, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Zhiyu Ru, Jun Cao
  • Patent number: 10600459
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 10560106
    Abstract: A clock recovery circuit includes a delay line circuit configured to output a plurality of first clocks having different phases obtained by delaying an input data signal, a register circuit configured to determine and write received data in the input data signal based on the first clocks, and a control circuit configured to control the writing of the data in the register circuit based on transitions of the input data signal.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 11, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kouichi Kanda
  • Patent number: 10552169
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for on-die signal calibration. A calibration circuit on an integrated circuit device receives data from an active data path of the integrated circuit device and detects a variation in the received data from a calibration data pattern. An adjustment circuit on an integrated circuit device reduces a delay of an active data path of the integrated circuit device in response to detecting a first variation in received data. An adjustment circuit on an integrated circuit device increases a delay of an active data path of the integrated circuit device in response to detecting a second variation in received data.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: February 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ravindra Arjun Madpur, Amandeep Kaur
  • Patent number: 10551869
    Abstract: This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: February 4, 2020
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Sarma Vrudhula, Aykut Dengi, Niranjan Kulkarni
  • Patent number: 10545530
    Abstract: An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: January 28, 2020
    Assignee: MEDIATEK INC.
    Inventors: You-Ming Tsao, Chun-Liang Chen, Chen-Chia Lee
  • Patent number: 10547294
    Abstract: This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 28, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Andrew Nathan Mort, Christopher C. McQuilkin
  • Patent number: 10474110
    Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Gil Horovitz, Aryeh Farber, Nisim Machluf, Evgeny Shumaker, Igal Kushnir
  • Patent number: 10469063
    Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
  • Patent number: 10454484
    Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dan Shi, Tyler J. Gomm, Michael J. Allen
  • Patent number: 10419006
    Abstract: A enhanced DLL includes a delay chain, a phase detector and a delay control unit. The delay chain is arranged to delay a reference clock signal to generate a delayed reference clock signal and reflect the delay control setting on the delayed reference clock signal, wherein the delay chain is periodically reset according to a period of the reference clock signal. The phase detector is coupled to the delay chain, and arranged to detect a phase shift between the delayed reference clock signal and the reference clock signal, thereby to generate a control value. The delay control unit is coupled to the delay chain and the phase detector, and arranged to adjust the delay control setting based on the control value.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 17, 2019
    Assignee: Brocere Electronics company limited
    Inventors: Yu-Hong Yang, Jou-Hung Wang, Chih-Hao Lai
  • Patent number: 10411718
    Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Karthik Nagarajan, Chenling Huang, Debesh Bhatta
  • Patent number: 10403340
    Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
  • Patent number: 10367634
    Abstract: A clock and data recovery device includes a data analysis circuitry, a loop filter circuitry, a phase rotator circuitry, a multiplexer circuitry, and a phase interpolator circuitry. The data analysis circuitry analyzes input data according to a first clock signal and a second clock signal to generate an error signal. The loop filter circuitry updates an adjustment signal according to the error signal. The phase rotator circuitry adjusts rotation signals according to the adjustment signal and limit values if the adjustment signal is updated. The multiplexer circuitry outputs one of the rotation signals as a phase control signal according to third clock signals. The phase interpolator circuitry adjusts the first and the second clock signals according to the phase control signal and fourth clock signals.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 30, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Po-Shing Yu
  • Patent number: 10361689
    Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
  • Patent number: 10355698
    Abstract: Clock circuits and apparatus containing such are useful in clock synchronization and skew adjustment. Such clock circuits may include a delay line coupled to receive an input signal, wherein the delay line comprises a plurality of delay elements, and wherein at least two delay elements of the plurality of delay elements differ in unit time delay. Such clock circuits may further include a phase detector coupled to receive the input signal and a signal generated from an output signal of the delay line. The phase detector may be configured to compare the input signal to the generated signal and to adjust a length of the delay line to synchronize the input signal and the generated signal.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tyler Gomm, Gary Johnson
  • Patent number: 10340902
    Abstract: Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 2, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Justin L. Fortier, Rachel Katumba
  • Patent number: 10326404
    Abstract: A time amplifier includes a first signal regeneration circuit, a second signal regeneration circuit, a first delay circuit configured to receive the second input signal and output the delayed second input signal by a predetermined delay time, and a second delay circuit configured to receive the first input signal and output the delayed first input signal by the predetermined delay time. A corresponding signal regeneration operation is stopped when at least one of the first and second output signals is high. The at least one output signal remains high.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 18, 2019
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Min Jae Lee, Min Uk Heo
  • Patent number: 10270455
    Abstract: Multi-phase clock generation employing phase error detection between multiple delay circuit outputs in a controlled delay line to provide error correction is disclosed. A multi-phase clock generator is provided that includes a controlled delay line and a phase error detector circuit. Tap nodes are provided from outputs of one or more delay circuits in the controlled delay line. To detect and correct for phase errors in the controlled delay line, a phase detection circuit is provided that includes at least two phase detectors each configured to measure a phase offset error between tap nodes from the delay circuit(s) in the controlled delay line. These phase errors are then combined to create an error correction signal, which is used to control the delay of the delay circuit(s) in the controlled delay line to lock the phase of the output of the final delay circuit to an input reference clock signal.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: April 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Bo Sun
  • Patent number: 10263627
    Abstract: A delay-locked loop (DLL) includes a delay line configured to receive a reference clock signal and a control signal, and generate a first plurality of clock signals. Each clock signal of the first plurality is configured to have a different phase delay relative to the reference clock signal. A phase frequency detector is coupled to the delay circuit and is configured to receive a first clock signal and a second clock signal of the first plurality, and generate up and down control signals. A charge pump is coupled to receive the up and down control signals and generates a charge pump current based on the up and down control signals. An output of the charge pump is coupled to the delay line at a voltage control node. An initialization circuit is coupled to the voltage control node and is configured to generate an initialization voltage based on the reference clock signal frequency.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 16, 2019
    Assignee: NXP USA, INC.
    Inventors: Deependra Jain, Krishna Thakur, Gaurav Agrawal
  • Patent number: 10242736
    Abstract: An example device includes a first module, a second module, and a third module. The first module is to compare an input current to a first reference current, and provide a first output. The second module is to compare the input current to a second reference current, and provide a second output. The third module is to compare the first output to the second output, and provide a third output indicative of a state associated with the input current.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: March 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Brent Buchanan
  • Patent number: 10224939
    Abstract: A circuit device includes a DLL circuit and an adjustment circuit. The DLL circuit has a plurality of delay elements, and a first clock signal generated using a first resonator and having a first clock frequency is input to the DLL circuit. Delayed clock signals from the delay elements of the DLL circuit, and a second clock signal generated using a second resonator and having a second clock frequency lower than the first clock frequency are input to the adjustment circuit, and the adjustment circuit adjusts delay amounts of the delay elements of the DLL circuit using a frequency difference between the first clock frequency and the second clock frequency.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 5, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Akio Tsutsumi, Katsuhiko Maki
  • Patent number: 10200046
    Abstract: A delay-locked loop includes multiple inverters coupled together, wherein the inverters receive an input clock signal and output a first clock signal and a second clock signal. The input clock signal passes through a first set of inverters having a first number of inverters to generate the first clock signal. The input clock signal also passes through a second set of inverters having a second number of inverters one inverter greater than the first number of inverters to generate the second clock signal. The delay-locked loop also includes a polarity matching block that receives the first clock signal and the second clock signal and changes polarity of one of the first clock signal and the second clock signal.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Chee Seng Leong, Tat Hin Tan
  • Patent number: 10176885
    Abstract: A semiconductor memory apparatus includes a comparison circuit generating a detection code in response to stored data and expected data, a counting circuit generating a counting code in response to the detection code, a selection code output circuit outputting one of a plurality of expected codes as a selection code in response to a selection signal, and a plurality of signal storage circuits. A comparison result output circuit including a plurality of signal storage circuits which stores a comparison result of a comparison between the counting code and the selection code in one signal storage circuit among the plurality of signal storage circuits according to the selection signal, and a value stored in one signal storage circuit among the plurality of signal storage circuits is output as a result signal in response to an output enable signal.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 8, 2019
    Assignee: SK hynix Inc.
    Inventor: Jae Seok Kang
  • Patent number: 10171091
    Abstract: A phase interpolator includes a control circuit configured to generate a selection control signal that corresponds to a selected coarse phase interval, and generate a weight setting signal for generating a phase interpolation clock signal with an interpolated phase within the coarse phase interval; a phase selector configured to receive a plurality of inversion delay clock signal pairs, select at least two inversion delay clock signal pairs from the plurality of inversion delay clock signal pairs based on the selection control signal, select and output a selection delay clock signal pair corresponding to the coarse phase interval from the selected at least two inversion delay clock signal pairs; and a phase mixer configured to receive the selection delay clock signal pair from the phase selector and generate the phase interpolation clock signal based on the weight setting signal.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-seok Song, Byoung-joo Yoo, Chang-kyung Seong
  • Patent number: 10162376
    Abstract: Operation of a charge pump is controlled to optimize power conversion efficiency by using an adiabatic mode with some operating characteristics and a non-adiabatic mode with other characteristics. The control is implemented by controlling a configurable circuit at the output of the charge pump.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: December 25, 2018
    Assignee: pSemi Corporation
    Inventors: Gregory Szczeszynski, Oscar Blyde
  • Patent number: 10141940
    Abstract: A delay-locked loop includes a voltage control delay line and a phase detector. The phase detector includes: a sampler unit generating multiple samples obtained by sampling a data signal in a time interval corresponding to a half of a unit interval based on a clock; a mode selection unit selecting a series of samples among the multiple samples in such a way that the mode selection unit selects the series of samples starting from an odd-numbered sample, or selects the series of samples starting from an even-numbered sample, according to a mode selection signal; and an XOR unit performing an XOR operation on the samples that are adjacent to each other and outputting an operation result, the output operation result is used for controlling the voltage-controlled delay line. The delay-locked loop can greatly reduce power consumption and an area of the voltage control delay line.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: November 27, 2018
    Assignee: Seoul National University R&DB Foundation
    Inventors: Deogkyoon Jeong, Woorham Bae
  • Patent number: 10128853
    Abstract: A delay-locked loop (DLL) circuit and an integrated circuit (IC) including the same are provided. The DLL circuit includes a pre-processing circuit configured to generate a first pulse signal and a second pulse signal based on a clock signal input, the first pulse signal and the second pulse signal having a phase difference of (s/2) times a clock period of the clock signal (where s is a positive integer), a delay line configured to generate a delay signal by delaying the first pulse signal by a delay amount corresponding to a selection value, a phase detector configured to detect a phase difference between the delay signal and the second pulse signal, and a control logic configured to adjust the selection value based on the phase difference between the delay signal and the second pulse signal as detected by the phase detector, so as to synchronize the delay signal with the second pulse signal.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan-yeob Chae, Shin-young Yi, Hyung-kweon Lee
  • Patent number: 10103721
    Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: October 16, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Albert Martinez, Michel Agoyan
  • Patent number: 10090828
    Abstract: A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, and generating an up/down signal according to the lengths of a second section of the target clock and the first section of the selected delayed clock, a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal, a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock, and a control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction period.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 2, 2018
    Assignee: SK Hynix Inc.
    Inventor: Yo-Han Jeong
  • Patent number: 10072976
    Abstract: An optical sensor arrangement (10) comprises a light sensor (11), a current source (41), an analog-to-digital converter (12) and a switch (44) which selectively couples the light sensor (11) or the current source (41) to an input (14) of the analog-to-digital converter (12).
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: September 11, 2018
    Assignee: ams AG
    Inventor: Gonggui Xu
  • Patent number: 10075175
    Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Young Min Park, Mark Elzinga
  • Patent number: 10056912
    Abstract: A circuit for phase locked loop (PLL) multiple spur cancellation includes multiple spur cancellation circuits and a number of multiplexers that are coupled to respective input ports of the spur cancellation circuits. The circuit further includes a number of demultiplexers that are coupled to respective output ports of the spur cancellation circuits. Each spur cancellation circuit can cancel a spur associated with a spur source, and input nodes of the multiplexers and output nodes of the demultiplexers are coupled to different connection points of a PLL circuit.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 21, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Long Bu, David Christopher Garrett, Dandan Li