With Variable Delay Means Patents (Class 327/149)
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Patent number: 12034448Abstract: Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A card include first transmit (Tx) component configured to connect to a second receive (Rx) component in a second card; a first Rx component configured to connect to a second Tx component in the second card; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to compensate for differences between i) the first Tx component and the second Rx component, and ii) the first Rx component and the second Tx component.Type: GrantFiled: September 14, 2022Date of Patent: July 9, 2024Assignee: Ciena CorporationInventors: Jerry Yee-Tung Lam, Sadok Aouini, Naim Ben-Hamida
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Patent number: 11799463Abstract: A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.Type: GrantFiled: June 17, 2022Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hundae Choi, Garam Choi
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Patent number: 11423963Abstract: An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.Type: GrantFiled: November 18, 2019Date of Patent: August 23, 2022Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Deog-Kyoon Jeong, Han-Gon Ko, Chan-Ho Kye, So-Yeong Shin
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Patent number: 11405041Abstract: A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock.Type: GrantFiled: February 15, 2021Date of Patent: August 2, 2022Assignee: Shenzhen Goodix Technology Co., Ltd.Inventors: Amr Abuellil, Ahmed Emira, Janakan Sivasubramaniam
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Patent number: 11381246Abstract: A time-to-digital converter and a converting method are provided. The time-to-digital converter includes: a phase locked loop unit configured to multiply an input reference clock by using a phase locked loop (PLL); a counting unit configured to count the multiplied input reference clock and record an edge position of an input signal; a delay locked loop unit configured to decompose the multiplied input reference clock into a multi-phase clock using a delay locked loop (DLL), and sense the recorded edge position of the input signal among the decomposed multi-phase clock and record a fine edge position; and a control unit configured to calculate a time difference in time of flight (ToF) between a start signal and a stop signal of the input signal by using the recorded edge position and the recorded fine edge position.Type: GrantFiled: December 2, 2020Date of Patent: July 5, 2022Assignee: HYUNDAI MOBIS CO., LTD.Inventors: Jung Dae Oh, Hee Hyun Lee
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Patent number: 11294443Abstract: A sensor circuit in a computer system measures a frequency of an oscillator circuit and uses the measured frequency to determine an operating condition of the computer system. The accuracy of the operating condition is limited by various sources of noise, including device noise, that introduce error into frequency measurements, limiting the accuracy to which the frequency of the oscillator signal may be measured. To improve the accuracy of the frequency measurement of the oscillator signal, the sensor circuit disables the oscillator between successive measurements, in order to reduce the correlation of error between the successive measurements. The sensor circuit combines the multiple measurement results to determine the frequency of the oscillator signal to a higher degree of accuracy, thereby improving the accuracy to which the operating condition is determined.Type: GrantFiled: September 11, 2020Date of Patent: April 5, 2022Assignee: Apple Inc.Inventors: Jafar Savoj, Robert S. Brandt, II, Bruno W. Garlepp
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Patent number: 11269372Abstract: A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.Type: GrantFiled: September 6, 2019Date of Patent: March 8, 2022Assignee: RAMBUS INC.Inventors: Robert Wang, Zhuobin Li, Navid Yaghini, Hemesh Yasotharan, Clifford Ting
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Patent number: 11265009Abstract: A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.Type: GrantFiled: December 30, 2019Date of Patent: March 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Keliu Shu, Gary Franklin Chard, William Robert Krenik
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Patent number: 11239834Abstract: An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.Type: GrantFiled: December 11, 2020Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Abishek Manian
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Patent number: 11200931Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.Type: GrantFiled: January 22, 2021Date of Patent: December 14, 2021Assignee: Micron Technology, Inc.Inventor: Kang-Yong Kim
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Patent number: 11003203Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.Type: GrantFiled: July 22, 2019Date of Patent: May 11, 2021Assignee: XILINX, INC.Inventors: Chi Fung Poon, Asma Laraba, Parag Upadhyaya
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Patent number: 10972085Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.Type: GrantFiled: November 14, 2017Date of Patent: April 6, 2021Assignee: Intel IP CorporationInventors: Sebastian Sievert, Sarit Zur, Ofir Degani, Rotem Banin
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Patent number: 10938395Abstract: An electronic device including: a delay circuit configured to adjust a delay of an input for generating an output signal; and an input selection circuit coupled to the delay circuit, the input selection circuit configured to control a phase for a clock input based at least in part on a measurement of a delay corresponding to the delay circuit in generating the input.Type: GrantFiled: March 4, 2020Date of Patent: March 2, 2021Assignee: Micron Technology, Inc.Inventors: Dan Shi, Tyler J. Gomm, Michael J. Allen
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Patent number: 10924121Abstract: A DLL circuit is disclosed. The DLL circuit includes a delay line, configured to receive a delay line input clock, and to generate a plurality of output clocks each having a phase based on a delay of the delay line. The DLL circuit also includes a control circuit, configured to selectively cause the delay line input clock to be equal to one of a DLL input clock and an inverted one of the output clocks of the delay line, and an edge combiner, configured to generate a DLL output clock based on the output clocks of the delay line.Type: GrantFiled: February 11, 2020Date of Patent: February 16, 2021Assignee: Shenzhen Goodix Technology Co., Ltd.Inventors: Amr Abuellil, Ahmed Emira, Janakan Sivasubramaniam
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Patent number: 10902897Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.Type: GrantFiled: August 17, 2020Date of Patent: January 26, 2021Assignee: Micron Technology, Inc.Inventor: Kang-Yong Kim
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Patent number: 10862488Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.Type: GrantFiled: December 26, 2018Date of Patent: December 8, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marius Moe, Tarjei Aaberge
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Patent number: 10812057Abstract: A time detection circuit and a time detection method are provided. The time detection circuit includes an input signal processor and a time signal amplifier. The input signal processor receives a first input signal and a second input signal, calculates a time difference value between the first input signal and the second input signal, adjusts the time difference value by comparing the time difference value with a set reference value, and provides the adjusted time difference value. The time signal amplifier receives the adjusted time difference value, and amplifies the adjusted time difference value to generate an amplified time signal. The time signal amplifier operates in a linear operation region between a first time value and a second time value, and the set reference value is set according to the first time value and the second time value.Type: GrantFiled: December 26, 2019Date of Patent: October 20, 2020Assignee: Faraday Technology Corp.Inventors: Pei-Yuan Chou, Jinn-Shyan Wang, Chuen-Shiu Chen
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Patent number: 10797707Abstract: A delay locked loop detection system (10), the system can be used for detecting the working state of a delay locked loop (400) and comprises: a signal generator (300), which is used for generating a reference clock and providing the reference clock to the delay locked loop (400); and a testing instrument (500), which is used for acquiring the clock signals output from the delay locked loop (400) and measuring whether the time delays thereof are consistent with expectations; the detection system (10) further comprises at least one of the following circuits: a pre-receiving circuit (100), which is used for receiving the reference clock from the signal generator (300) and amplifying and shaping the reference clock and then providing the reference clock to the delay locked loop (400); and a multiphase multiplexing circuit (200), which is used for receiving the clock signals output from the delay locked loop (400) and synthesizing and then providing a plurality of clock signals with different delay to the testingType: GrantFiled: May 10, 2016Date of Patent: October 6, 2020Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.Inventors: Xueyan Wang, Ying Yang, Jingjia Yu
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Patent number: 10783940Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.Type: GrantFiled: February 24, 2020Date of Patent: September 22, 2020Assignee: Micron Technology, Inc.Inventor: Kang-Yong Kim
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Patent number: 10778405Abstract: Disclosed is a clock generating circuit capable of operating in an analog clock data recovery (ACDR) mode to reduce the loop latency or a clock multiplication unit (CMU) mode to suppress reference jitter. The circuit includes a filter and an oscillator. The filter receives an input signal to determine voltages of a first node and a second node respectively and includes a first filtering circuit and a second filtering circuit coupled in parallel between the first node and a reference voltage terminal. The second filtering circuit includes a switch and a capacitor connected in series, wherein the second node is between the switch and capacitor, and the switch is turned off in the ACDR mode and turned on in the CMU mode. The oscillator outputs a clock according to the first node's voltage in the ACDR mode or according to the second node's voltage in the CMU mode.Type: GrantFiled: July 10, 2019Date of Patent: September 15, 2020Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Jian Liu, Weixiong He, Jianing Lou
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Patent number: 10778233Abstract: A method for Phase Locked Loop (PLL) lock detection includes determining a phase error by comparing a feedback phase to a reference phase. A frequency error is determined by comparing a feedback frequency to a reference frequency. A lock signal is determined in response to the phase error being less than an upper phase threshold and greater than a lower phase threshold, and the frequency error being less than an upper frequency threshold and greater than a lower frequency threshold.Type: GrantFiled: August 14, 2019Date of Patent: September 15, 2020Assignee: NXP B.V.Inventor: Ulrich Moehlmann
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Patent number: 10762937Abstract: According to one embodiment, in a semiconductor device, the first pull-up circuit is connected to a third node and to a fourth node. The third node is a node between a drain of the first transistor with a first conductivity type and a source of the second transistor with the first conductivity type. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with a second conductivity type and a source of the second transistor with the second conductivity type.Type: GrantFiled: March 12, 2019Date of Patent: September 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yohei Yasuda
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Patent number: 10748586Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.Type: GrantFiled: February 24, 2020Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventor: Kang-Yong Kim
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Patent number: 10727826Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.Type: GrantFiled: February 22, 2019Date of Patent: July 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hun-Dae Choi, Hwa-Pyong Kim
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Patent number: 10712770Abstract: Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.Type: GrantFiled: July 23, 2018Date of Patent: July 14, 2020Assignee: XILINX, INC.Inventors: Ping-Chuan Chiang, Kee Hian Tan, Arianne B. Roldan, Nakul Narang, Yipeng Wang, Yohan Frans, Kun-Yung Chang
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Patent number: 10707848Abstract: An apparatus for interpolating between a first and a second signal is provided. The apparatus includes a plurality of interpolation cells coupled to a common node of the apparatus. Further, the apparatus includes a control circuit configured to supply, based on a control word, respective selection signals to each of the plurality of interpolation cells. At least one of the plurality of interpolation cells is configured to couple the common node to a first potential if the first signal and the second signal are both at a first signal level, couple the common node to a second potential, which is different from the first potential, if the first signal and the second signal are both at a second signal level, which is different from the first signal level, and to decouple the common node from at least one of the first potential and the second potential if the first signal and the second signal are at different signal levels.Type: GrantFiled: March 31, 2017Date of Patent: July 7, 2020Assignee: Apple Inc.Inventors: Georgios Palaskas, Sebastian Sievert
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Patent number: 10680591Abstract: An example delay circuit is described that includes an input node to receive a first signal, a first circuit path, a second circuit path, an output buffer, and an output node. The first circuit path includes at least one first buffer and a first array of switches. The second circuit path includes at least one second buffer and a second array of switches. The output buffer receives a mixed output of the first circuit path and the second circuit path. The output node transmits a second signal equivalent to the first signal with a programmed delay.Type: GrantFiled: April 2, 2018Date of Patent: June 9, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Chris Schiller, Adam Johnson
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Patent number: 10651834Abstract: An apparatus of performing a clock skew adjustment between N clock signals. 2(N?1) skew sensors are configured as successive pairs k, each pair k having a first skew sensor and a second skew sensor. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. A skew controller performs the clock skew adjustment based on the first and second information.Type: GrantFiled: October 15, 2019Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
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Patent number: 10644813Abstract: A method and system for time domain calibration to compensate for signal phase impairment in transmit paths in a transmitter configured to drive an antenna array are disclosed. According to one aspect, a base station is configured to compensate for signal impairment in transmit paths feeding an array of antenna elements in which the compensation is performed in the time domain. The base station includes a combiner configured to combine signals output from the transmit paths to form a feedback signal. An impairment estimator is configured to receive the feedback signal and outbound traffic signals and to determine a phase compensation value for each impairment path. A multiplier is provided for each transmit path, the multipliers configured to multiply the outbound traffic signals by respective phase compensation values.Type: GrantFiled: March 11, 2016Date of Patent: May 5, 2020Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Neil McGowan, Slim Ben Ghalba, Marthinus Willem Da Silveira
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Patent number: 10636463Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.Type: GrantFiled: May 22, 2019Date of Patent: April 28, 2020Assignee: Micron Technology, Inc.Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
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Patent number: 10622981Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.Type: GrantFiled: September 25, 2017Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
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Patent number: 10623004Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.Type: GrantFiled: September 10, 2019Date of Patent: April 14, 2020Assignee: Micron Technology, Inc.Inventors: Dan Shi, Tyler J. Gomm, Michael J. Allen
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Patent number: 10623044Abstract: An apparatus for phase and frequency detection (PFD) includes a first circuit to receive a first input pulse and to generate a first output pulse, the rising edge of which is triggered by a first rising edge of the first input pulse, and a second circuit coupled to the first circuit and configured to receive a second input pulse and to generate a second output pulse, the rising edge of which is triggered by a second rising edge of the second input pulse. The second output pulse has a falling edge carrying first information related to a first rising edge of the first input pulse. The first output pulse has a falling edge carrying second information related to a second rising edge of the second input pulse.Type: GrantFiled: August 20, 2018Date of Patent: April 14, 2020Assignee: Avago Technologies International Sales Pte. LimitedInventors: Zhiyu Ru, Jun Cao
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Patent number: 10600459Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.Type: GrantFiled: October 22, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventor: Kang-Yong Kim
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Patent number: 10560106Abstract: A clock recovery circuit includes a delay line circuit configured to output a plurality of first clocks having different phases obtained by delaying an input data signal, a register circuit configured to determine and write received data in the input data signal based on the first clocks, and a control circuit configured to control the writing of the data in the register circuit based on transitions of the input data signal.Type: GrantFiled: October 26, 2017Date of Patent: February 11, 2020Assignee: FUJITSU LIMITEDInventor: Kouichi Kanda
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Patent number: 10552169Abstract: Apparatuses, systems, methods, and computer program products are disclosed for on-die signal calibration. A calibration circuit on an integrated circuit device receives data from an active data path of the integrated circuit device and detects a variation in the received data from a calibration data pattern. An adjustment circuit on an integrated circuit device reduces a delay of an active data path of the integrated circuit device in response to detecting a first variation in received data. An adjustment circuit on an integrated circuit device increases a delay of an active data path of the integrated circuit device in response to detecting a second variation in received data.Type: GrantFiled: September 18, 2017Date of Patent: February 4, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Ravindra Arjun Madpur, Amandeep Kaur
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Patent number: 10551869Abstract: This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.Type: GrantFiled: February 27, 2017Date of Patent: February 4, 2020Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Sarma Vrudhula, Aykut Dengi, Niranjan Kulkarni
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Patent number: 10547294Abstract: This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.Type: GrantFiled: June 9, 2017Date of Patent: January 28, 2020Assignee: Analog Devices, Inc.Inventors: Andrew Nathan Mort, Christopher C. McQuilkin
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Patent number: 10545530Abstract: An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.Type: GrantFiled: May 11, 2017Date of Patent: January 28, 2020Assignee: MEDIATEK INC.Inventors: You-Ming Tsao, Chun-Liang Chen, Chen-Chia Lee
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Patent number: 10474110Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.Type: GrantFiled: December 21, 2018Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Gil Horovitz, Aryeh Farber, Nisim Machluf, Evgeny Shumaker, Igal Kushnir
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Patent number: 10469063Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.Type: GrantFiled: March 22, 2019Date of Patent: November 5, 2019Assignee: International Business Machines CorporationInventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
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Patent number: 10454484Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.Type: GrantFiled: August 14, 2018Date of Patent: October 22, 2019Assignee: Micron Technology, Inc.Inventors: Dan Shi, Tyler J. Gomm, Michael J. Allen
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Patent number: 10419006Abstract: A enhanced DLL includes a delay chain, a phase detector and a delay control unit. The delay chain is arranged to delay a reference clock signal to generate a delayed reference clock signal and reflect the delay control setting on the delayed reference clock signal, wherein the delay chain is periodically reset according to a period of the reference clock signal. The phase detector is coupled to the delay chain, and arranged to detect a phase shift between the delayed reference clock signal and the reference clock signal, thereby to generate a control value. The delay control unit is coupled to the delay chain and the phase detector, and arranged to adjust the delay control setting based on the control value.Type: GrantFiled: September 18, 2018Date of Patent: September 17, 2019Assignee: Brocere Electronics company limitedInventors: Yu-Hong Yang, Jou-Hung Wang, Chih-Hao Lai
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Patent number: 10411718Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.Type: GrantFiled: September 25, 2017Date of Patent: September 10, 2019Assignee: QUALCOMM IncorporatedInventors: Karthik Nagarajan, Chenling Huang, Debesh Bhatta
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Patent number: 10403340Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.Type: GrantFiled: February 7, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
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Patent number: 10367634Abstract: A clock and data recovery device includes a data analysis circuitry, a loop filter circuitry, a phase rotator circuitry, a multiplexer circuitry, and a phase interpolator circuitry. The data analysis circuitry analyzes input data according to a first clock signal and a second clock signal to generate an error signal. The loop filter circuitry updates an adjustment signal according to the error signal. The phase rotator circuitry adjusts rotation signals according to the adjustment signal and limit values if the adjustment signal is updated. The multiplexer circuitry outputs one of the rotation signals as a phase control signal according to third clock signals. The phase interpolator circuitry adjusts the first and the second clock signals according to the phase control signal and fourth clock signals.Type: GrantFiled: September 20, 2018Date of Patent: July 30, 2019Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Po-Shing Yu
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Patent number: 10361689Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.Type: GrantFiled: December 27, 2017Date of Patent: July 23, 2019Assignee: International Business Machines CorporationInventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
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Patent number: 10355698Abstract: Clock circuits and apparatus containing such are useful in clock synchronization and skew adjustment. Such clock circuits may include a delay line coupled to receive an input signal, wherein the delay line comprises a plurality of delay elements, and wherein at least two delay elements of the plurality of delay elements differ in unit time delay. Such clock circuits may further include a phase detector coupled to receive the input signal and a signal generated from an output signal of the delay line. The phase detector may be configured to compare the input signal to the generated signal and to adjust a length of the delay line to synchronize the input signal and the generated signal.Type: GrantFiled: April 22, 2014Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventors: Tyler Gomm, Gary Johnson
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Patent number: 10340902Abstract: Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.Type: GrantFiled: April 30, 2018Date of Patent: July 2, 2019Assignee: Analog Devices Global Unlimited CompanyInventors: Justin L. Fortier, Rachel Katumba
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Patent number: RE49449Abstract: Operation of a charge pump is controlled to optimize power conversion efficiency by using an adiabatic mode with some operating characteristics and a non-adiabatic mode with other characteristics. The control is implemented by controlling a configurable circuit at the output of the charge pump.Type: GrantFiled: December 24, 2020Date of Patent: March 7, 2023Assignee: PSEMI CORPORATIONInventors: Gregory Szczeszynski, Oscar Blyde, David M. Giuliano