With Variable Delay Means Patents (Class 327/149)
  • Patent number: 10545530
    Abstract: An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: January 28, 2020
    Assignee: MEDIATEK INC.
    Inventors: You-Ming Tsao, Chun-Liang Chen, Chen-Chia Lee
  • Patent number: 10547294
    Abstract: This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 28, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Andrew Nathan Mort, Christopher C. McQuilkin
  • Patent number: 10474110
    Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Gil Horovitz, Aryeh Farber, Nisim Machluf, Evgeny Shumaker, Igal Kushnir
  • Patent number: 10469063
    Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
  • Patent number: 10454484
    Abstract: An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dan Shi, Tyler J. Gomm, Michael J. Allen
  • Patent number: 10419006
    Abstract: A enhanced DLL includes a delay chain, a phase detector and a delay control unit. The delay chain is arranged to delay a reference clock signal to generate a delayed reference clock signal and reflect the delay control setting on the delayed reference clock signal, wherein the delay chain is periodically reset according to a period of the reference clock signal. The phase detector is coupled to the delay chain, and arranged to detect a phase shift between the delayed reference clock signal and the reference clock signal, thereby to generate a control value. The delay control unit is coupled to the delay chain and the phase detector, and arranged to adjust the delay control setting based on the control value.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 17, 2019
    Assignee: Brocere Electronics company limited
    Inventors: Yu-Hong Yang, Jou-Hung Wang, Chih-Hao Lai
  • Patent number: 10411718
    Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Karthik Nagarajan, Chenling Huang, Debesh Bhatta
  • Patent number: 10403340
    Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
  • Patent number: 10367634
    Abstract: A clock and data recovery device includes a data analysis circuitry, a loop filter circuitry, a phase rotator circuitry, a multiplexer circuitry, and a phase interpolator circuitry. The data analysis circuitry analyzes input data according to a first clock signal and a second clock signal to generate an error signal. The loop filter circuitry updates an adjustment signal according to the error signal. The phase rotator circuitry adjusts rotation signals according to the adjustment signal and limit values if the adjustment signal is updated. The multiplexer circuitry outputs one of the rotation signals as a phase control signal according to third clock signals. The phase interpolator circuitry adjusts the first and the second clock signals according to the phase control signal and fourth clock signals.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 30, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Po-Shing Yu
  • Patent number: 10361689
    Abstract: Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
  • Patent number: 10355698
    Abstract: Clock circuits and apparatus containing such are useful in clock synchronization and skew adjustment. Such clock circuits may include a delay line coupled to receive an input signal, wherein the delay line comprises a plurality of delay elements, and wherein at least two delay elements of the plurality of delay elements differ in unit time delay. Such clock circuits may further include a phase detector coupled to receive the input signal and a signal generated from an output signal of the delay line. The phase detector may be configured to compare the input signal to the generated signal and to adjust a length of the delay line to synchronize the input signal and the generated signal.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tyler Gomm, Gary Johnson
  • Patent number: 10340902
    Abstract: Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 2, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Justin L. Fortier, Rachel Katumba
  • Patent number: 10326404
    Abstract: A time amplifier includes a first signal regeneration circuit, a second signal regeneration circuit, a first delay circuit configured to receive the second input signal and output the delayed second input signal by a predetermined delay time, and a second delay circuit configured to receive the first input signal and output the delayed first input signal by the predetermined delay time. A corresponding signal regeneration operation is stopped when at least one of the first and second output signals is high. The at least one output signal remains high.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 18, 2019
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Min Jae Lee, Min Uk Heo
  • Patent number: 10270455
    Abstract: Multi-phase clock generation employing phase error detection between multiple delay circuit outputs in a controlled delay line to provide error correction is disclosed. A multi-phase clock generator is provided that includes a controlled delay line and a phase error detector circuit. Tap nodes are provided from outputs of one or more delay circuits in the controlled delay line. To detect and correct for phase errors in the controlled delay line, a phase detection circuit is provided that includes at least two phase detectors each configured to measure a phase offset error between tap nodes from the delay circuit(s) in the controlled delay line. These phase errors are then combined to create an error correction signal, which is used to control the delay of the delay circuit(s) in the controlled delay line to lock the phase of the output of the final delay circuit to an input reference clock signal.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: April 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Bo Sun
  • Patent number: 10263627
    Abstract: A delay-locked loop (DLL) includes a delay line configured to receive a reference clock signal and a control signal, and generate a first plurality of clock signals. Each clock signal of the first plurality is configured to have a different phase delay relative to the reference clock signal. A phase frequency detector is coupled to the delay circuit and is configured to receive a first clock signal and a second clock signal of the first plurality, and generate up and down control signals. A charge pump is coupled to receive the up and down control signals and generates a charge pump current based on the up and down control signals. An output of the charge pump is coupled to the delay line at a voltage control node. An initialization circuit is coupled to the voltage control node and is configured to generate an initialization voltage based on the reference clock signal frequency.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 16, 2019
    Assignee: NXP USA, INC.
    Inventors: Deependra Jain, Krishna Thakur, Gaurav Agrawal
  • Patent number: 10242736
    Abstract: An example device includes a first module, a second module, and a third module. The first module is to compare an input current to a first reference current, and provide a first output. The second module is to compare the input current to a second reference current, and provide a second output. The third module is to compare the first output to the second output, and provide a third output indicative of a state associated with the input current.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: March 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Brent Buchanan
  • Patent number: 10224939
    Abstract: A circuit device includes a DLL circuit and an adjustment circuit. The DLL circuit has a plurality of delay elements, and a first clock signal generated using a first resonator and having a first clock frequency is input to the DLL circuit. Delayed clock signals from the delay elements of the DLL circuit, and a second clock signal generated using a second resonator and having a second clock frequency lower than the first clock frequency are input to the adjustment circuit, and the adjustment circuit adjusts delay amounts of the delay elements of the DLL circuit using a frequency difference between the first clock frequency and the second clock frequency.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 5, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Akio Tsutsumi, Katsuhiko Maki
  • Patent number: 10200046
    Abstract: A delay-locked loop includes multiple inverters coupled together, wherein the inverters receive an input clock signal and output a first clock signal and a second clock signal. The input clock signal passes through a first set of inverters having a first number of inverters to generate the first clock signal. The input clock signal also passes through a second set of inverters having a second number of inverters one inverter greater than the first number of inverters to generate the second clock signal. The delay-locked loop also includes a polarity matching block that receives the first clock signal and the second clock signal and changes polarity of one of the first clock signal and the second clock signal.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Chee Seng Leong, Tat Hin Tan
  • Patent number: 10176885
    Abstract: A semiconductor memory apparatus includes a comparison circuit generating a detection code in response to stored data and expected data, a counting circuit generating a counting code in response to the detection code, a selection code output circuit outputting one of a plurality of expected codes as a selection code in response to a selection signal, and a plurality of signal storage circuits. A comparison result output circuit including a plurality of signal storage circuits which stores a comparison result of a comparison between the counting code and the selection code in one signal storage circuit among the plurality of signal storage circuits according to the selection signal, and a value stored in one signal storage circuit among the plurality of signal storage circuits is output as a result signal in response to an output enable signal.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 8, 2019
    Assignee: SK hynix Inc.
    Inventor: Jae Seok Kang
  • Patent number: 10171091
    Abstract: A phase interpolator includes a control circuit configured to generate a selection control signal that corresponds to a selected coarse phase interval, and generate a weight setting signal for generating a phase interpolation clock signal with an interpolated phase within the coarse phase interval; a phase selector configured to receive a plurality of inversion delay clock signal pairs, select at least two inversion delay clock signal pairs from the plurality of inversion delay clock signal pairs based on the selection control signal, select and output a selection delay clock signal pair corresponding to the coarse phase interval from the selected at least two inversion delay clock signal pairs; and a phase mixer configured to receive the selection delay clock signal pair from the phase selector and generate the phase interpolation clock signal based on the weight setting signal.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-seok Song, Byoung-joo Yoo, Chang-kyung Seong
  • Patent number: 10162376
    Abstract: Operation of a charge pump is controlled to optimize power conversion efficiency by using an adiabatic mode with some operating characteristics and a non-adiabatic mode with other characteristics. The control is implemented by controlling a configurable circuit at the output of the charge pump.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: December 25, 2018
    Assignee: pSemi Corporation
    Inventors: Gregory Szczeszynski, Oscar Blyde
  • Patent number: 10141940
    Abstract: A delay-locked loop includes a voltage control delay line and a phase detector. The phase detector includes: a sampler unit generating multiple samples obtained by sampling a data signal in a time interval corresponding to a half of a unit interval based on a clock; a mode selection unit selecting a series of samples among the multiple samples in such a way that the mode selection unit selects the series of samples starting from an odd-numbered sample, or selects the series of samples starting from an even-numbered sample, according to a mode selection signal; and an XOR unit performing an XOR operation on the samples that are adjacent to each other and outputting an operation result, the output operation result is used for controlling the voltage-controlled delay line. The delay-locked loop can greatly reduce power consumption and an area of the voltage control delay line.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: November 27, 2018
    Assignee: Seoul National University R&DB Foundation
    Inventors: Deogkyoon Jeong, Woorham Bae
  • Patent number: 10128853
    Abstract: A delay-locked loop (DLL) circuit and an integrated circuit (IC) including the same are provided. The DLL circuit includes a pre-processing circuit configured to generate a first pulse signal and a second pulse signal based on a clock signal input, the first pulse signal and the second pulse signal having a phase difference of (s/2) times a clock period of the clock signal (where s is a positive integer), a delay line configured to generate a delay signal by delaying the first pulse signal by a delay amount corresponding to a selection value, a phase detector configured to detect a phase difference between the delay signal and the second pulse signal, and a control logic configured to adjust the selection value based on the phase difference between the delay signal and the second pulse signal as detected by the phase detector, so as to synchronize the delay signal with the second pulse signal.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan-yeob Chae, Shin-young Yi, Hyung-kweon Lee
  • Patent number: 10103721
    Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: October 16, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Albert Martinez, Michel Agoyan
  • Patent number: 10090828
    Abstract: A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, and generating an up/down signal according to the lengths of a second section of the target clock and the first section of the selected delayed clock, a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal, a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock, and a control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction period.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 2, 2018
    Assignee: SK Hynix Inc.
    Inventor: Yo-Han Jeong
  • Patent number: 10072976
    Abstract: An optical sensor arrangement (10) comprises a light sensor (11), a current source (41), an analog-to-digital converter (12) and a switch (44) which selectively couples the light sensor (11) or the current source (41) to an input (14) of the analog-to-digital converter (12).
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: September 11, 2018
    Assignee: ams AG
    Inventor: Gonggui Xu
  • Patent number: 10075175
    Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Young Min Park, Mark Elzinga
  • Patent number: 10056912
    Abstract: A circuit for phase locked loop (PLL) multiple spur cancellation includes multiple spur cancellation circuits and a number of multiplexers that are coupled to respective input ports of the spur cancellation circuits. The circuit further includes a number of demultiplexers that are coupled to respective output ports of the spur cancellation circuits. Each spur cancellation circuit can cancel a spur associated with a spur source, and input nodes of the multiplexers and output nodes of the demultiplexers are coupled to different connection points of a PLL circuit.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 21, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Long Bu, David Christopher Garrett, Dandan Li
  • Patent number: 10038549
    Abstract: A CDR (Clock and Data Recovery) circuit includes a current source, an operational amplifier, an NOR gate, and a capacitor. The current source supplies a current to a first node. The operational amplifier has a positive input terminal for receiving a reference voltage, a negative input terminal coupled to the first node, and an output terminal coupled to a second node. The NOR gate has a first input terminal coupled to the second node, a second input terminal coupled to an input node of the CDR circuit, and an output terminal coupled to an output node of the CDR circuit. The input node is arranged for receiving an input signal, and the output node is arranged for outputting an output signal. The capacitor is coupled between the first node and the output node.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: July 31, 2018
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventor: Yeong-Sheng Lee
  • Patent number: 10003353
    Abstract: Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: June 19, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Bryan Kris, Jim Bartling, Neil Deutscher
  • Patent number: 9999014
    Abstract: Embodiments of the present invention relate to a method and a system for controlling phase synchronization, and an apparatus. The method includes: determining a path from a non-reference base station to a preset reference base station, obtaining a first phase difference between every two adjacent base stations on the path, obtaining a second phase difference between the reference base station and the non-reference base station according to the first phase difference, and adjusting a non-reference phase of the non-reference base station to a reference phase of the reference base station according to the second phase difference. According to the method and system for controlling phase synchronization, and the apparatus that are provided in the embodiments of the present invention, in a single-frequency network system, phases of base stations are synchronized without a need to install a GPS antenna, so that system costs are reduced.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 12, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Jun Hu
  • Patent number: 9979575
    Abstract: A device implementing a distributed dynamic configuration of a scalable radio frequency communication system includes a primary radio frequency (RF) integrated circuit (RFIC) and at least one secondary RFIC. The primary RFIC includes at least one phase shifter, and the primary RFIC may be configured to apply a first phase shift to an RF signal using the at least one first phase shifter, and to transmit the RF signal to at least one secondary RFIC. The at least one secondary RFIC includes at least one second phase shifter, and the at least one secondary RFIC may be configured to apply a second phase shift to the RF signal using the at least one second phase shifter, and to transmit the RF signal via at least one antenna element. The first and second phase shifts may be received by the primary RFIC from a baseband processor.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 22, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Alireza Tarighat Mehrabani, Payam Torab Jahromi, Brima Babatunde Ibrahim
  • Patent number: 9935621
    Abstract: According to one embodiment, there is provided a semiconductor device including an input terminal, an output terminal, an oscillation circuit, an adjuster circuit, a driver circuit, and a detector circuit. The input terminal receives a first clock. The oscillation circuit generates an internal clock. The adjuster circuit corrects a duty ratio of a clock. The driver circuit receives the clock from the adjuster circuit and supplies a third clock to the output terminal. The detector circuit detects that a duty ratio of a clock according to the third clock deviates from a duty ratio of a second clock according to the internal clock. The adjuster circuit adjusts a correction amount in tune with the second clock, and corrects a duty ratio of the first clock with the adjusted correction amount according to a detection result of the detector circuit.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masashi Nakata, Hidefumi Kushibe
  • Patent number: 9929735
    Abstract: A circuit includes a first circuit, a second circuit and a third circuit. The first circuit is configured to receive a first phase of a clock signal, a second phase of a clock signal and a first control signal. The first circuit is configured to generate a first interpolated phase of a clock signal. The second circuit is configured to receive a third phase of a clock signal, a fourth phase of a clock signal and a second control signal, and generate a second interpolated phase of a clock signal. The third circuit is configured to receive the first interpolated phase of the clock signal and the second interpolated phase of the clock signal, and generate the first control signal. The first control signal dynamically adjusts the first interpolated phase of the clock signal.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Tsung-Ching Huang, Ming-Chieh Huang
  • Patent number: 9900196
    Abstract: A system implementing switching diversity in a scalable radio frequency communication system includes a primary radio frequency integrated circuit (RFIC), a first secondary RFIC, and a second secondary RFIC. The first secondary RFIC is configured to receive a radio frequency (RF) signal from a device via antenna elements based on a first beam setting, and transmit the RF signal to the primary RFIC. The primary RFIC is configured to receive the RF signal; downconvert the RF signal to an intermediate frequency (IF) signal; transmit the IF signal to a baseband processor; receive, from the baseband processor, a control signal including a second beam setting; and transmit the control signal to the second secondary RFIC. The second secondary RFIC is configured to receive the control signal from the first primary RFIC, and receive the first RF signal from the device via second antenna elements based on the second beam setting.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: February 20, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Alireza Tarighat Mehrabani, Payam Torab Jahromi, Brima Babatunde Ibrahim
  • Patent number: 9893878
    Abstract: Embodiments include systems and methods for on-chip random jitter (RJ) measurement in a clocking circuit (e.g., in a phase-locked loop of a serializer/deserializer circuit). Some embodiments determine a reference delay code sweep window to capture at least a candidate RJ range of a feedback clock signal, the reference delay code sweep window comprising a sequence of reference delay codes. A distribution of one-scores can be computed over the reference delay code sweep window, so that the distribution indicates a relatively likelihood, for each reference delay code, of obtaining a ‘1’ sample when sampling the feedback clock signal according to the delayed clock signal (delayed by an amount according to the reference delay code). The distribution can be transformed into a time domain by computing code offset times for the reference delay codes. A RJ output can be computed as a function of the distribution in the time domain.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: February 13, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Long Kong, Ben Li Chen, Philip Kwan, Zuxu Qin, Dawei Huang
  • Patent number: 9874895
    Abstract: A reference current generating circuit has a variable current supply to output a reference current, delay circuitry to generate a reference clock by delaying a clock by a reference delay amount and a delay clock by delaying the clock depending on a current value of the reference current, a phase comparator to compare a phase of the reference clock with a phase of the delay clock to output a comparison result, and control circuitry to control the current value of the reference current based on the compared result.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 23, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kentaro Yoshioka
  • Patent number: 9843316
    Abstract: An integrated circuit may be provided. The integrated circuit may include a transmitter and a receiver. The transmitter outputs first transmission data to a first channel and outputs second transmission data to a second channel. The phase of the first transmission data transmitted through the first channel is different from a phase of the second transmission data transmitted through the second channel.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 12, 2017
    Assignee: SK hynix Inc.
    Inventors: Hae Rang Choi, Dae Han Kwon, Hyung Soo Kim
  • Patent number: 9843465
    Abstract: A device implementing a distributed dynamic configuration of a scalable radio frequency communication system includes a primary radio frequency (RF) integrated circuit (RFIC) and at least one secondary RFIC. The primary RFIC includes at least one phase shifter, and the primary RFIC may be configured to apply a first phase shift to an RF signal using the at least one first phase shifter, and to transmit the RF signal to at least one secondary RFIC. The at least one secondary RFIC includes at least one second phase shifter, and the at least one secondary RFIC may be configured to apply a second phase shift to the RF signal using the at least one second phase shifter, and to transmit the RF signal via at least one antenna element. The first and second phase shifts may be received by the primary RFIC from a baseband processor.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 12, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Alireza Tarighat Mehrabani, Payam Torab Jahromi, Brima Babatunde Ibrahim
  • Patent number: 9836121
    Abstract: An eye-width detector, a memory storage device and an eye-width detection method of data signal are provided. The eye-width detector includes a phase interpolator, a calibration circuit and an eye-width detection circuit. The phase interpolator receives a first clock signal and a phase control signal and output a second clock signal. The calibration circuit receives the first clock signal and the second clock signal and output a first control signal. The eye-width detection circuit receive the data signal, the first clock signal and the second clock signal and generate a first sampling value and a second sampling value. If the first sampling value and the second sampling value do not match a first condition, the eye-width detection circuit outputs a second control signal; otherwise, outputs eye-width information of the data signal. Accordingly, the efficiency of the eye-width detection may be improved.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: December 5, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Jen-Chu Wu, Wei-Yung Chen, Yu-An Chen
  • Patent number: 9780769
    Abstract: A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 3, 2017
    Assignee: SK hynix Inc.
    Inventors: Da In Im, Young Suk Seo
  • Patent number: 9742386
    Abstract: Clock generation circuits including a single and multi-phase clock circuits are disclosed. A clock generation circuit is coupled to receive a first pulse on a first input and a second pulse on a second input. The first pulse may be generated responsive to a rising edge of an input clock signal, while the second pulse may be generated responsive to a falling edge of the input clock signal. Responsive to the first pulse, an output node of the clock generation circuit may be pulled high. Responsive to the second pulse, the output node may be pulled low. During those points in which neither pulse is asserted, a state element in the clock generation circuit may hold the output node to its most recent value. Using delay elements and multiple instances of the clock generation circuit and pulse generation circuits, a multi-phase clock generation circuit may be constructed.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 22, 2017
    Assignee: Apple Inc.
    Inventor: Haiming Jin
  • Patent number: 9729157
    Abstract: A variable phase generator is disclosed that includes a delay line with an input, and output, and a delay lone control signal input. A signal on the delay line output has a phase offset relative to the delay line input signal such that the phase offset is controlled by a digital offset signal. A phase detector process the input signal and the output signal to generate a phase detector output signal. A charge pump, responsive to the phase detector output signal, generates a charge pump output. A digital to analog converter receives and converts the digital offset signal to an analog offset signal. A control node is connected to the delay line control input, the charge pump, and the digital to analog converter, and is configured to receive and combine the charge pump output and the analog offset signal to create the delay line control signal.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 8, 2017
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Wim F. Cops
  • Patent number: 9667219
    Abstract: Methods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: May 30, 2017
    Assignee: The Regents of the University of California
    Inventor: Qun Gu
  • Patent number: 9658635
    Abstract: Operation of a charge pump is controlled to optimize power conversion efficiency by using an adiabatic mode with some operating characteristics and a non-adiabatic mode with other characteristics. The control is implemented by controlling a configurable circuit at the output of the charge pump.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: May 23, 2017
    Assignee: ARCTIC SAND TECHNOLOGIES, INC.
    Inventors: Gregory Szczeszynski, Oscar Blyde
  • Patent number: 9654093
    Abstract: An electronic device includes a first duty cycle correction circuit, a delay line, a second duty cycle correction circuit, and a delay control circuit. The first duty cycle correction circuit is configured to detect a duty cycle error of a clock signal by performing time-to-digital conversion on the clock signal, and to generate a corrected clock signal by adjusting a duty cycle of the clock signal based on the duty cycle error of the clock signal. The delay line is configured to generate a delayed corrected clock signal by delaying the corrected clock signal based on a delay control code The second duty cycle correction circuit is configured to detect a duty cycle error of a first output clock signal received through a feedback loop, and to generate a second output clock signal by adjusting duty cycle of the delayed corrected clock signal based on the duty cycle error of the first output clock signal.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Won-Joo Yun, Yong Shim
  • Patent number: 9640125
    Abstract: The present disclosure provides methods for transmitting data in a display system, a clock controller, a source driver, and a display system. The method includes the steps of: receiving, by the clock controller, a reference clock signal and a data signal from an external data source; determining a phase difference between the data signal and the reference clock signal in each cycle; encoding the determined phase difference to generate a corresponding encoded signal; and transmitting the encoded signal and the reference clock signal to the source driver. By encoding the phase difference between the data signal and the reference clock signal in each cycle, it is able to use the encoded signal and the reference clock signal to transmit the data signal and the reference clock signal between the clock controller and the source driver.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 2, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yizhen Xu
  • Patent number: 9627013
    Abstract: An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 18, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hiromasa Takeda, Hiroki Fujisawa
  • Patent number: 9614534
    Abstract: The digital delay-locked loop includes: a frequency divider, used to perform frequency division processing on a first clock-signal according to frequency division information, and output a second clock-signal; a signal-selector, used to select the first or second clock-signal as a third clock-signal according to the selection signal output; a delay line, used to delay the third clock-signal according to the delay control signal, and output a fourth clock-signal; a phase detector, used to receive the third and fourth clock-signals, perform phase detection processing, and output a phase detection judgment signal; and a state machine connected with the frequency divider, signal-selector, delay line and phase detector, used to adjust and control the frequency division information, the selection signal and the delay control signal output according to the phase detection judgment signal and a set state logic, to achieve that delay time of the fourth clock-signal relative to the first clock-signal.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 4, 2017
    Assignee: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventor: Mingfu Shi
  • Patent number: 9608642
    Abstract: A delay lock loop including a selection unit, a delay unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit is coupled to the selection unit. The delay unit includes a delay factor and delays the first clock signal to generate a third clock signal according to the delay factor. The phase detection unit is coupled to the delay unit and the selection unit and generates the indication signal according to a phase difference between the second and third clock signals. The delay unit adjusts the delay factor according to the indication signal.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 28, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Qiang Si, Fan Jiang