Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

Abstract: A method of controlling a hybrid phase-locked loop may include generating a first control signal based on an offset signal and a second control signal and determining a difference between the first and the second control signals. The method may further include adjusting a value of the offset signal based on the difference between the first and the second control signals to drive a level of the first control signal to a level of the second control signal. The method may further include determining when the level of the first control signal crosses the level of the second control signal. After the level of the first control signal crosses the level of the second control signal, the method may include adjusting the value of the offset signal based on a number of occurrences of the level of the first control signal crossing the level of the second control signal.

Abstract: A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.

Abstract: A semiconductor device includes a sampling unit suitable for sampling a logic value of an input signal based on an edge of an operation clock to output a sampling signal, an edge detection unit suitable for detecting an edge of the input signal based on the sampling signal, and a phase control unit suitable for controlling a phase of the operation clock while periodically changing a value of a clock delay code at each predetermined period and substituting a code value, which is obtained by calculating a value of the clock delay code corresponding to a time point at which an operation of the edge detection unit is completed and a value of a pre-phase code determined based on the sampling signal, for the clock delay code.

Abstract: An apparatus relates generally to an injection-controlled-locked phase-locked loop (“ICL-PLL”) is disclosed. In this apparatus, a delay-locked loop is coupled to an injection-locked phase-locked loop. An injection-locked oscillator of the injection-locked phase-locked loop is in a feedback loop path of the delay-locked loop.

Abstract: A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.

Abstract: A Micro Electrical Mechanical System (MEMS) oscillator supplies a MEMS clock signal to a digital locked loop that generates an output clock signal having a frequency that corresponds to a desired frequency ratio between the MEMS oscillator output signal and the digital locked loop output signal. The frequency ratio may be determined, at least in part, as a function of temperature.

Abstract: A clock generator includes a delay circuit to have 2N delays, in which a delay time from a first delay of the 2N delays to a last delay is set to a length of one cycle of an input; a first phase-detector to detect a first phase-difference between the input and an output from the last delay; a first charge-pump to generate a first current according to the first phase-difference; a first loop-filter to adjust a delay amount of each of the 2N delays, based on a voltage of the first current; a second phase-detector to detect a second phase-difference between the input and an output from an Nth delay; a second charge-pump to generate a second current according to the second phase-difference; and a second loop-filter to adjust a duty ratio of an output from each of the 2N delays, based on a voltage of the second current.

Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

Abstract: A delay locked loop (DLL) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (PFD) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal.

Abstract: The DLL comprises a coarse delay line configured to have a plurality of unit delays and delay an reference dock to output a delayed clock, a fine delay line configured to delay the delayed clock to output a delayed output clock, a replica delay unit configured to delay the delayed output clock by an expected modeling value to output a feedback clock, a phase detection unit configured to compare a phase of the feedback clock with a phase of the reference clock to generate first to third phase detection signals based on a result of the comparison, a locking detection unit configured to output a locking signal by selecting a first locking detection signal or a second locking detection signal, and a control unit configured to control the coarse and fine delay lines in response to the locking signal and the first phase detection signal.

Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

Abstract: Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by an adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.

Abstract: A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a phase finder and a time-to-digital converter. The phase finder is configured for sampling the oscillator output signal with the N-phased oscillator output signals to calculate an estimated value of a fractional phase part. One oscillation period of the digitally-controlled oscillator is divided into N sub-periods. The time-to-digital converter is configured for sampling one of the N-phased oscillator output signals with a reference-frequency signal to calculate a precise value of the fractional phase part within one sub-period.

Abstract: Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. The inputs to the QTF may be either single input, multiple outputs, or alternatively, multiple inputs, multiple outputs. Furthermore, the second state of either of the two QTF transformations may be either positive or negative. A phase-locked-loop (PLL) operation may be performed on the quadrature signal to monitor a voltage vector between the grid and a connected power converter. The QTF and PLL methods are suitable for either single-phase applications or n-phase (any number of phases) applications.

Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

Abstract: A delayed locked loop (DLL) adjusts a duty cycle of an input clock signal and outputs an output clock signal. The DLL includes a phase and duty cycle detector configured to detect a phase and duty cycle of the input clock signal, a duty cycle corrector configured to correct the duty cycle, a control code generator configured to detect coarse lock of the DLL and generate a binary control code corresponding to the detection result, and a delay circuit configured to delay an output signal of the duty cycle corrector by a predetermined time according to the binary control code, tune the duty cycle thereof, and mix the phase thereof, wherein the phase and duty cycle detector, the duty cycle corrector, the control code generator, and the delay circuit form a feedback loop.

Abstract: Disclosed herein is a device that comprises a delay line delaying a first clock signal in response to the delay control information to produce a delayed clock signal, a phase detector unit controls the delay control information in response to a relationship in phase between the first clock signal and a second clock signal, and an inverting control unit receiving the delayed clock signal and producing a third clock signal, the second clock signal being produced in response to the third clock signal. The third clock signal is in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state.

Abstract: A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.

Abstract: Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a delay length, and, in a second mode, to determine an initial delay. The apparatus further including a delay line circuit coupled to the controller and includes delay elements. Each of the delay elements includes delay gates that are the same type of delay gate. The delay line circuit is configured to, in the first mode propagate a signal through one or more of the delay elements to provide a delayed signal. The delay line circuit is further configured to, in the second mode, propagate a pulse signal through one or more of the delay elements and provide a corresponding output signal from each of the one or more delay elements responsive to the pulse signal reaching an output of the corresponding delay element.

Abstract: A phase calibration device comprises: an oscillator for generating a reference clock; a phase-lock-loop for generating an input clock by the reference clock; a multiphase clock generator for generating a plurality of output clocks by the input clock; a selector for selecting one of the output clocks as an operation clock; an analog-to-digital convertor for performing analog-to-digital conversion to input data by the operation clock to generate a conversion result; a control circuit for generating parameters according to the conversion result and controlling the selector to do selection; and a phase calibration circuit for outputting a calibration signal and the input clock of the phase-lock-loop to the multiphase clock generator after restarting the phase-lock-loop, so that the multiphase clock generator can correctly regenerate the output clocks by the calibration signal and the input clock, and then the control circuit controls the selector to do selection by the parameters.

Abstract: A circuit comprising 1) a master delay-locked loop comprising a phase detector for receiving a reference clock and generating an output, control logic for receiving the output from the phase detector and a delta delay input and generating a control output, a clock splitter for receiving the reference clock and generating differential clock output, a delay line for receiving the differential reference clock from the clock splitter and generating n phases of differential reference clock at output, a multiplexer for receiving the output from the delay line and the control logic output and generating a clock output, wherein the phase detector is for receiving the reference clock, and 2) a slave delay-locked loop for receiving the control logic output and a strobe input and generating a delay locked loop output.

Abstract: An apparatus and method for reducing effects of spurs in a phased-locked loop having a sigma-delta modulator and digital circuits. The apparatus includes a clock dithering circuit coupled to each of the sigma-delta modulator and the digital circuits. Each clock dithering circuit is configured to dither flanks of a respective first and second clock input signal, and generate a dithered clock output signal, one for each of the sigma-delta modulator and digital circuits. A frequency of each dithered clock output signal follows a frequency of the respective first and second clock input signals, and a phase between each dithered clock output signal and the respective first and second clock input signal is shifted and constantly changing.

Abstract: Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.

Abstract: A method and apparatus for measuring the duration of a transient signal with high precision.

Abstract: Methods and apparatuses are provided that allow for the synchronization of an operating point transition in an embedded system environment. Identification of an upcoming operating point transition, operating point transition constraints, and maximum parking latency parameters is provided. Then, an ordering of seizing bus activity as well as an ordering of resuming bus activity is determined. The operating point transition is then implemented using the determined ordering. Simulation and determination of change of successfully completing operating point transition prior to initiating and while the transition is pending are also provided.

Abstract: A semiconductor device includes a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a reference clock signal in response to a second delay amount tracked using a first delay amount as an initial delay amount, and track the second delay amount again by adjusting the first delay amount in response to a reset signal, and a DLL controller configured to activate the reset signal when the second delay amount deviates from a given range.

Abstract: A delay-locked loop (DLL) circuit having improved phase correction performance includes a variable delay unit configured to generate a DLL clock signal by delaying an input clock signal by a varied delay time in response to a delay control signal at timing corresponding to an update cycle signal, a delay model configured to generate a feedback clock signal by delaying the DLL clock signal for a predetermined delay time, a phase detection unit configured to output a result of the detection of the phase of the feedback clock signal based on a reference clock signal as the delay control signal, and an update cycle control unit configured to determine whether a cycle has been shifted or not in response to an external clock signal and the delay control signal and shift a cycle where the update cycle signal is generated based on a result of the determination.

Abstract: The present invention relates to a method and device for phase-frequency detection in a phase-lock loop circuit. The method comprises receiving compare edge of a reference clock signal and compare edge of a feedback clock signal, maintaining a phase/frequency detector, PFD, state machine with three PFD states, UP, DOWN, and IDLE, based on the received compare edges of the reference and feedback clock signals, recording current and previous time the state machine stays in UP or DOWN states, generating an UP or DOWN signal based on transition of PFD states and the comparison between recorded current time and recorded previous time; and outputting a digital control signal to a feedback frequency control device based on the UP or DOWN signal. A device and system is arranged to execute the method according to the present invention.

Abstract: A circuit includes a delay line and a delay locked loop. The circuit is configured to receive a delay parameter and a clock signal. The delay locked loop is configured to generate a pair of control codes based on a frequency of the clock signal and a frequency of an oscillator of the delay locked loop. The delay locked loop is configured to determine a difference between the frequency of the clock signal and the frequency of the oscillator based on a phase of an output of the oscillator and a phase of the clock signal after the output of the oscillator and the clock signal are aligned. The delay line is configured to receive an input signal and generate an output signal delayed from the input signal by a time delay that corresponds to a delay line control code calculated from the pair of control codes and the delay parameter.

Abstract: A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.

Abstract: A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.

Abstract: A transmission/reception device includes a transmission circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals to be sent to another device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew; and a reception circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals sent from another transmission/reception device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew.

Abstract: A semiconductor device includes a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line in response to the measured cycle of the source clock as determined from an output signal of the clock cycle measuring unit.

Abstract: A digital to analog converter including at least one current steering source and a master replica bias network. Each current steering source includes a data current source, two switches, two buffer devices, and two activation current sources. The switches are controlled by a data bit and its inverse for switching the source current between first and second control nodes. The buffer devices buffer the control nodes between corresponding output nodes. The activation current sources ensure that each buffer device remains active regardless of the state of the switches. The master replica bias network includes a replica buffer device coupled to a replica control node and a master buffer amplifier. The master buffer amplifier drives the first, second and replica buffer devices in parallel to maintain the first, second and replica control nodes at a common master control voltage to minimize noise and glitches at the output.

Abstract: A delay-locked loop includes a first delay unit, a second delay unit, a third delay unit, a phase detector, and a controller. The first delay unit generates a first delay clock according to a clock and a first delay time. The second delay unit generates a second delay clock according to the first delay clock and a second delay time. The third delay unit generates a third delay clock according to the second delay clock and a third delay time. The phase detector generates a phase detection signal according to the clock and the second delay clock. The controller generates and outputs a phase control signal according to the phase detection signal. The second delay unit and the third delay unit adjust the second delay time and the third delay time respectively according to the phase control signal.

Abstract: A phase calibration device comprises: an oscillator for generating a reference clock; a phase-lock-loop for generating an input clock by the reference clock; a multiphase clock generator for generating a plurality of output clocks by the input clock; a selector for selecting one of the output clocks as an operation clock; an analog-to-digital convertor for performing analog-to-digital conversion to input data by the operation clock to generate a conversion result; a control circuit for generating parameters according to the conversion result and controlling the selector to do selection; and a phase calibration circuit for outputting a calibration signal and the input clock of the phase-lock-loop to the multiphase clock generator after restarting the phase-lock-loop, so that the multiphase clock generator can correctly regenerate the output clocks by the calibration signal and the input clock, and then the control circuit controls the selector to do selection by the parameters.

Abstract: A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: A delay locked loop (DLL) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (PFD) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal.

Abstract: Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

Abstract: An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference.

Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.

Abstract: A delay time control circuit is provided which includes a delay locked loop generating a second clock signal delayed by a predetermined time in response to a first clock signal; a plurality of delay circuits each receiving the first and second clock signals and outputting third and fourth clock signals in response to first and second digital clock signals; and a feedback control unit receiving the third and fourth clock signals to detect a delay time and generating the first and second digital control signals for compensating the detected delay time.

Abstract: The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.

Abstract: Control circuitry and adjustable clock signal generation circuitry is provided to control the signal transmission rate for electronic devices and systems of electronic devices. The control circuitry may receive status signals indicating current clock rates of a signal transmitting and receiving circuit as well as current processing capacity from the signal receiving circuit. The control circuitry may then generate control signals which control adjustable clock signal generation circuitry. The adjustable clock signal generation circuitry may be used to adjust the rate of generated clock signals for the signal transmitting and receiving circuits which can increase or decrease the signal transmission rate between those circuits.

Abstract: A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: A semiconductor device includes a delay locked loop unit configured to compare a phase of an internal clock with a phase of a feedback clock to delay the internal clock by a delay amount corresponding to a comparison result, and to output a delay locked clock, a delay replica modeling unit configured to output the feedback clock by reflecting a transfer delay amount of the internal clock used in an internal circuit into the delay locked clock, and to adjust the transfer delay amount in response to a delay replica adjustment signal, and a delay replica adjustment signal generation unit configured to compare the phase of the feedback clock with a phase of the delay locked clock, and to set a value of the delay replica adjustment signal in response to a comparison result.

Abstract: A synchronous semiconductor device includes an internal command generation unit configured to generate an internal command corresponding to a source command, a delay locked loop configured to delay a source clock by a first delay time required for delay-locking to generate a delay locked clock, a delay time determination unit configured to determine a second delay time for delay-locking the internal command using the source clock, the second delay time being determined by reflecting a third delay time generated on a command path, and a latency control unit configured to shift the internal command by a shifting period, in which the second delay time is reflected, in response to the delay locked clock.