With Digital Element Patents (Class 327/150)
  • Patent number: 10355587
    Abstract: There is described an electronic device, the device comprising (a) a power supply terminal for connecting to a power supply (130, 330), (b) a first circuit (110, 310) coupled to be powered by the power supply, the first circuit (110, 310) being susceptible to power supply noise within a predetermined frequency range, and (c) a second circuit (120, 320) coupled to be powered by the power supply, the second circuit (120, 320) comprising an open-loop capacitive DC-DC converter (323) having a switching frequency outside of the predetermined frequency range. There is also described a system comprising an electronic device and a reader/writer device. Furthermore, there is described a method of manufacturing an electronic device.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: July 16, 2019
    Assignee: NXP B.V.
    Inventors: Jaydeep Dalwadi, Venkata Satya Sai Evani
  • Patent number: 10164648
    Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John W. Stanton, Pradeep Thiagarajan
  • Patent number: 10148275
    Abstract: Various embodiments of fractional-N phase-locked loop (PLL) frequency synthesizers based on digital-to-analog conversion (DAC) are disclosed. In some embodiments, a PLL frequency synthesizer includes a phase-frequency detector, a voltage controlled oscillator (VCO) coupled to the phase-frequency detector, and a digital-to-analog converter (DAC) coupled between an input of the phase-frequency detector and an output of the VCO within a feedback path of the PLL frequency synthesizer. The phase-frequency detector is configured to receive a reference input clock and an output signal of the DAC as a feedback input clock. Furthermore, the DAC receives an output clock from the VCO and a digital control signal comprising frequency and phase information for synthesizing the feedback input clock. The disclosed DAC-based PLL frequency synthesizers do not require any frequency divider in a feedback path of the PLL, thereby significantly reducing power consumption and noise levels.
    Type: Grant
    Filed: August 28, 2016
    Date of Patent: December 4, 2018
    Inventor: Deyi Pi
  • Patent number: 9866222
    Abstract: An embodiment method for voltage-controlled oscillator (VCO) control includes detecting a first VCO output signal of a first VCO. The first VCO output signal has a first VCO output frequency. The method also includes determining a first down-scaled signal in accordance with the first VCO output signal. The first down-scaled signal has a first down-scaled frequency that is reduced by a fixed ratio relative to a current value of the first VCO output frequency. The method also includes modifying the first VCO output frequency using a first phase lock loop (PLL) in accordance with the first down-scaled signal and an oscillating reference signal, and detecting a second VCO output signal of a second VCO. The second VCO output signal has a second VCO output frequency. The method also includes modifying the second VCO output frequency in accordance with the second VCO output signal and the first down-scaled signal.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: January 9, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Saverio Trotta, Reinhard-Wolfgang Jungmaier
  • Patent number: 9859903
    Abstract: Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot are provided. During acquisition, a first phase offset signal configured to drive a phase error signal to zero is provided at a first circuit of the PLL. The first circuit may be a time-to-digital converter (TDC) of the PLL. A second phase offset signal configured to offset the first phase offset signal is provided at a second circuit of the PLL. The second circuit of the PLL may be a loop filter at the PLL.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 2, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Greg Alyn Unruh, Pin-En Su, Fazil Ahmad
  • Patent number: 9762252
    Abstract: Methods and systems for a digitally controlled oscillator may comprise, for example, an all-digital all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising a thermometer pulse coder comprising a plurality of frequency control word signal lines. the thermometer pulse coder may be configured to generate a frequency control word from a binary encoded frequency control word, where the frequency control word may comprise hermometer coded signals and a pulse modulated dither signal, and may select a frequency control word signal line over which to transmit the pulse modulated dither signal and may transmit the thermometer coded signals over another of frequency control word signal lines. A digitally controlled oscillator may be configured to receive a frequency control word and generate an output clock signal at a frequency determined using at least the frequency control word.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: September 12, 2017
    Assignee: Entropic Communications, LLC
    Inventors: Josephus A. Van Engelen, Hairong Yu, Howard A. Baumer
  • Patent number: 9722539
    Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 1, 2017
    Assignee: Rambus Inc.
    Inventors: Mohammad Hekmat, Reza Navid
  • Patent number: 9571082
    Abstract: A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lan-Chou Cho, Chewn-Pu Jou, Feng Wei Kuo, Huan-Neng Chen
  • Patent number: 9559704
    Abstract: In an example, operating a PLL circuit includes generating an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency, generating a plurality of clock signals having an output frequency based on the error signal, and generating the feedback clock signal from the plurality of clock signals based on a first divider value and a control value derived from a second divider value. Operating the PLL circuit further includes multiplying each of a first integer value and a first fractional value by a power of two to generate a second integer value and a second fractional value, respectively, generating the second divider value using a sigma-delta modulator (SDM) based on the second integer value and the second fractional value, and dividing the second divider value by the power of two to generate the first divider value.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: January 31, 2017
    Assignee: XILINX, INC.
    Inventors: Anna W. Wong, Ankur Jain, Richard W. Swanson
  • Patent number: 9553594
    Abstract: A DLL includes a phase detector, a counter, a delay circuit, and a false-lock detection and recovery circuit. The false-lock detection and recovery circuit checks whether the DLL is in a true-lock condition or not, based on an average of a phase difference between a clock signal and an intermediate clock signal. The intermediate clock signal is generated by the delay circuit based on a count value generated by the counter and a select signal generated by the false-lock detection and recovery circuit. The false-lock detection and recovery circuit generates and provides a control signal to the counter. Based on the control signal, the counter modifies the count on which a delay between the clock signal and an output signal of the DLL depends when the DLL is not in the true-lock condition.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 24, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Atul Gupta, Risi Jaiswal
  • Patent number: 9397674
    Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: July 19, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Pervez M. Aziz, Shiva Prasad Kotagiri, Sundeep Venkatraman, Sunil Srinivasa, Amaresh V. Malipatil
  • Patent number: 9231576
    Abstract: A device, comprises a first counter and a second counter, a control unit and a comparing unit. The first counter and the second counter are configured to alternately count a cycle number of a monitoring clock signal. The control unit is configured to generate, based on an input clock, both a first counter enable signal and a second counter enable signal that enable or disable the first and the second counters respective, and the first counter enable signal and the second counter enable signal are inverted. The comparing unit is coupled to both the first counter and the second counter and configured to detect a loss fault of the input clock if the cycle number of the monitoring signal counted by one of the first and the second counters exceed a predetermined threshold.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: January 5, 2016
    Assignee: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventors: Yi Li, Yong Wang
  • Patent number: 9077512
    Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: July 7, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Piotr Olejarz, Ara Arakelian, Lewis Malaver
  • Patent number: 9035683
    Abstract: Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: May 19, 2015
    Assignee: SILICON WORKS CO., LTD.
    Inventors: Hong Jun Yang, Yong Hwan Moon, Sang Ho Kim
  • Patent number: 9019017
    Abstract: A digitally controlled oscillator has a high-order ?? modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ?? modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 28, 2015
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Win Chaivipas, Masazumi Marutani, Daisuke Yamazaki
  • Patent number: 9007108
    Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: April 14, 2015
    Assignee: IQ-Analog Corporation
    Inventors: Mikko Waltari, Michael Kappes, William Huff
  • Patent number: 9007109
    Abstract: A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: April 14, 2015
    Assignee: Nvidia Corporation
    Inventors: Seydou Ba, Abdellatif Bellaouar, Ahmed R Fridi
  • Patent number: 9007105
    Abstract: A PLL includes an oscillator, multiple time-to-digital converters (TDCs) and a system for the remaining functionality. The TDCs measure the oscillator's phase against respective multiple reference clocks. The system compares the respective measured phases with respective desired phases to obtain phase error signals. One is selected to close the loop. The others are monitored and adjusted when not equal to zero. When a new reference clock must be used, the loop is changed from including the old phase error signal to the new. The old phase error was zero because the loop was in lock, the new phase error is zero because it was monitored and adjusted. Therefore, upon switching the loop from the old to the new phase error signal, the loop remains locked and switching is hitless.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 14, 2015
    Assignee: Perceptia Devices Australia Pty Ltd
    Inventor: Julian Jenkins
  • Patent number: 8994422
    Abstract: A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: March 31, 2015
    Assignee: ESS Technology, Inc.
    Inventors: Hu Jing Yao, Dustin Dale Forman, A. Martin Mallinson
  • Patent number: 8994418
    Abstract: A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 31, 2015
    Assignee: Technische Universitaet Dresden
    Inventors: Sebastian Hoeppner, Stefan Haenzsche
  • Publication number: 20150070051
    Abstract: A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Applicant: Synopsys, Inc.
    Inventors: Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8957714
    Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Vaishnav Srinivas, Jan Christian Diffenderfer, Philip Michael Clovis, David Ian West
  • Patent number: 8957712
    Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yi Tang, Bo Sun
  • Patent number: 8957713
    Abstract: Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: February 17, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Olivier Burg, Cao-Thong Tu
  • Patent number: 8952759
    Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 10, 2015
    Assignee: MediaTek Inc.
    Inventors: Ping-Ying Wang, Kuan-Hua Chao, Jeng-Horng Tsai
  • Patent number: 8947139
    Abstract: An apparatus increases the dynamic range of a time to digital converter. The apparatus includes: an input network configured to receive a first signal, a second signal, and a control signal having a sign value; and a time-to-digital converter (TDC) configured to generate a digital code value that represents a time delay value between the first signal and the second signal. The input network is configured to switch where the first signal and second signal are output in response to the sign value that is determined by the time delay value between the first signal and the second signal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: February 3, 2015
    Assignee: Marvell International Ltd.
    Inventors: Luca Vercesi, Rinaldo Castello, Fernando De Bernardinis
  • Patent number: 8923375
    Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, ?. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various ? values.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 30, 2014
    Assignee: Parade Technologies, Inc.
    Inventors: Ming Qu, Yuanping Chen, Yuntao Zhu, Quan Yu, Kochung Lee
  • Patent number: 8917125
    Abstract: A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s1(t) is accepted having a first frequency f1 and a bandwidth (BW). The method generates a clock at frequency fs, and creates 2 sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. The method also generates a first tone signal s2(t) having a predetermined second frequency f2 outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating 2 digital sample signals per clock period 1/fs. The 2 digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: December 23, 2014
    Assignee: IQ-Analog Corporation
    Inventor: Mikko Waltari
  • Patent number: 8917124
    Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: December 23, 2014
    Assignee: IQ-Analog Corporation
    Inventors: Mikko Waltari, Michael Kappes, William Huff
  • Patent number: 8914909
    Abstract: A frequency measuring and control apparatus includes a plurality of synchronized oscillators integrated in parallel into one programmable logic device.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 16, 2014
    Assignee: RHK Technology, Inc.
    Inventor: Steffen Porthun
  • Patent number: 8907704
    Abstract: Disclosed is a frequency synthesizer including first and second shift register circuits 3a and 3b each for outputting PLL setting data on a rising edge of a load enable signal, first and second fractional modulators 4a and 4b each for generating dividing number control data on the basis of the PLL setting data in synchronization with a reference signal, and first and second fractional PLL synthesizers 5a and 5b each for generating a high frequency signal according to the PLL setting data, the reference signal, and the dividing number control data. By controlling the timing of the load enable signal, the frequency synthesizer carries out phase control between the high frequency signals generated by the first and second fractional PLL synthesizers 5a and 5b.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: December 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yusuke Kitsukawa, Hideyuki Nakamizo, Kenji Kawakami
  • Patent number: 8890624
    Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: November 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shuo-Wei Chen, David Kuochieh Su
  • Patent number: 8878614
    Abstract: A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: November 4, 2014
    Assignee: MegaChips Corporation
    Inventors: Wenjing Yin, Anand Gopalan
  • Patent number: 8878577
    Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 4, 2014
    Assignee: IQ-Analog Corporation
    Inventors: Mikko Waltari, Michael Kappes, William Huff
  • Patent number: 8872559
    Abstract: A digital phase-locked loop is provided. The digital phase-locked loop includes: a phase-locked loop, for generating an output frequency according to a reference frequency; and a numerically-controlled oscillator, coupled to the phase-locked loop, for generating the reference frequency, in which the numerically-controlled oscillator includes: a phase accumulator (PA), for outputting a sawtooth signal according to a clock signal and a frequency control word; and a most significant bit (MSB) detector, coupled to the phase accumulator, for detecting a most significant bit of the sawtooth signal outputted from the phase accumulator, thereby generating the reference frequency with a square waveform.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: October 28, 2014
    Assignee: Princeton Technology Corporation
    Inventor: Wen-Jan Lee
  • Patent number: 8873693
    Abstract: In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Limited
    Inventor: Nikola Nedovic
  • Patent number: 8860475
    Abstract: A first phase alignment circuit generates an indication of a phase of a first clock signal. A second phase alignment circuit adjusts a phase of a second clock signal based on a data signal. The second phase alignment circuit adjusts the phase of the second clock signal based on the indication of the phase of the first clock signal. The second phase alignment circuit resets an indication of the phase of the second clock signal generated based on the data signal in response to the indication of the phase of the first clock signal. The second phase alignment circuit captures a value of the data signal in response to the second clock signal.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: October 14, 2014
    Assignee: Altera Corporation
    Inventors: Tze Yi Yeoh, Lay Hock Khoo
  • Patent number: 8847641
    Abstract: A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 30, 2014
    Assignee: MegaChips Corporation
    Inventor: Shoichiro Kashiwakura
  • Publication number: 20140266337
    Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Cory Jay Peterson, Bhoodev Kumar, Daniel John Allen, Jeffrey D. Alderson
  • Publication number: 20140210525
    Abstract: A PLL includes an oscillator, multiple time-to-digital converters (TDCs) and a system for the remaining functionality. The TDCs measure the oscillator's phase against respective multiple reference clocks. The system compares the respective measured phases with respective desired phases to obtain phase error signals. One is selected to close the loop. The others are monitored and adjusted when not equal to zero. When a new reference clock must be used, the loop is changed from including the old phase error signal to the new. The old phase error was zero because the loop was in lock, the new phase error is zero because it was monitored and adjusted. Therefore, upon switching the loop from the old to the new phase error signal, the loop remains locked and switching is hitless.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 31, 2014
    Applicant: PERCEPTIA DEVICES AUSTRALIA PTY LTD.
    Inventor: Julian Jenkins
  • Patent number: 8779817
    Abstract: An apparatus and method for reducing effects of spurs in a phased-locked loop having a sigma-delta modulator and digital circuits. The apparatus includes a clock dithering circuit coupled to each of the sigma-delta modulator and the digital circuits. Each clock dithering circuit is configured to dither flanks of a respective first and second clock input signal, and generate a dithered clock output signal, one for each of the sigma-delta modulator and digital circuits. A frequency of each dithered clock output signal follows a frequency of the respective first and second clock input signals, and a phase between each dithered clock output signal and the respective first and second clock input signal is shifted and constantly changing.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: July 15, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Anders Jakobsson
  • Patent number: 8779812
    Abstract: Clock circuits are presented for providing a clock signal using multiple reference clock signals, including a PLL operating from a PLL reference clock signal, an FLL operating from an FLL reference clock signal, and a multiplexer circuit that selectively provides up and down signals from either a PFD of the PLL or the FLL to a charge pump of the PLL according to a reference clock select signal.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 15, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Peter Michael Kavanagh, Andrew Khar Boon Ong
  • Patent number: 8760201
    Abstract: Systems and methods for capacitance multiplication using one charge pump for a phase lock loop employ a digital controlled loop filter that operates in a time division mode. Embodiments of the loop filter block the current from the charge pump according to the digital control, such that the charge pump cannot charge or discharge the integral capacitor when the digital control is enabled. Because at least a portion of the current is blocked, it takes more time for the charge pump to charge or discharge the capacitor to a certain level. The capacitor then appears to be larger than its actual value with respect to operation of the phase lock loop.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: June 24, 2014
    Assignee: Analog Devices Technology
    Inventors: Ting Gao, Jiefeng Yan
  • Patent number: 8736325
    Abstract: A system for wide frequency range clock generation, includes: a phase lock loop (PLL) to generate a signal having a frequency; at least one fractional-N divider to divide the frequency of the signal; and a multiplexer to receive the signal from the PLL and an output signal from the at least one fractional-N divider, and to select the signal from the PLL or the output signal from the at least one fractional-N divider as a selected signal.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: May 27, 2014
    Assignee: Xilinx, Inc.
    Inventors: Jafar Savoj, Kun-Yung Chang
  • Patent number: 8710884
    Abstract: Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: April 29, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Olivier Burg, Cao-Thong Tu
  • Patent number: 8711018
    Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 29, 2014
    Assignee: Intel Corporation
    Inventors: Ehud Shoor, Dror Lazar, Assaf Benhamou
  • Patent number: 8704571
    Abstract: Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. A phase-locked-loop (PLL) operation may be performed on the quadrature signal to monitor a voltage vector between the grid and a connected power converter. The QTF and PLL methods are suitable for either single-phase applications or n-phase (any number of phases) applications. A frequency estimator estimates the grid frequency of the electric grid and outputs the estimated frequency to the QTF algorithms. The frequency estimator may include a three-phase phase-locked-loop (three-phase PLL) suitable for estimating the center frequencies of multiple phases of the electric grid. The frequency estimator may also include means for reducing the harmonics in the grid system.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 22, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Russel J. Kerkman, Ahmed Mohamed Sayed Ahmed, Brian J. Seibel, Carlos Rodriguez Valdez
  • Patent number: 8686771
    Abstract: The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 1, 2014
    Assignee: Broadcom Corporation
    Inventors: Emmanouil Frantzeskakis, Ioannis L. Syllaios, Georgios Sfikas, Henrik Jensen, Stephen Wu, Padmanava Sen
  • Patent number: 8675800
    Abstract: Disclosed herein is a synchronizing circuit including: a first PLL circuit; a second PLL circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; a control circuit; and a holding section.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 18, 2014
    Assignee: Sony Corporation
    Inventors: Tetsuhiro Futami, Ikko Okamoto
  • Patent number: 8653869
    Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 18, 2014
    Assignee: Media Tek Singapore Pte. Ltd.
    Inventors: Tsung-Kai Kao, Che-Fu Liang, Michael A. Ashburn, Jr.