Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: An apparatus for controllably distorting the duty cycle of a clock signal is disclosed. Methods and systems using embodiments of the invention are also described.

Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

Abstract: In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.

Abstract: A digital feedback loop circuit achieves a resolution as good as the intrinsic resolution of the delay element of the circuit, notwithstanding the presence of a feedback counter/divider of integer value N that might otherwise be expected to multiply the minimum resolution by N. Output altering circuitry is used to alter the error feedback signal for M out of every N feedback cycles in such a way that the overall delay over N cycles can be controlled to within the resolution of the delay element. In one embodiment, the output altering circuitry includes a second counter whose maximum value is controllable and that outputs a signal whose value changes after its current maximum value has been reached. In another embodiment, the output altering circuitry includes a lookup table preloaded with sequences of output signals, with the sequence selected by a controller.

Abstract: We describe and claim a delay locked loop harmonic detector and associated method. A delay locked loop includes a detection circuit to generate a detection signal responsive to an input clock and a control circuit to synchronize the delay locked loop to a fundamental of the input clock responsive to the detection signal. A method includes detecting harmonic synchronization in a delay locked loop responsive to an input clock and locking the delay locked loop to a fundamental of the input clock responsive to the detecting.

Abstract: An improved charge pump used in a phase-locked loop includes transient current correction capability by adding a canceling capacitance for each parasitic capacitance associated with a switching device in a charge pump. For each transient current component flowing through the parasitic capacitance, a canceling capacitance is implemented to create a canceling transient current component in the opposite direction such that it cancels out the transient current component. Preferably, an additional switching device is added to implement such a canceling capacitance for each parasitic capacitance.

Abstract: A digital feedback loop circuit achieves a resolution as good as the intrinsic resolution of the delay element of the circuit, notwithstanding the presence of a feedback counter/divider of integer value N that might otherwise be expected to multiply the minimum resolution by N. Output altering circuitry is used to alter the error feedback signal for M out of every N feedback cycles in such a way that the overall delay over N cycles can be controlled to within the resolution of the delay element. In one embodiment, the output altering circuitry includes a second counter whose maximum value is controllable and that outputs a signal whose value changes after its current maximum value has been reached. In another embodiment, the output altering circuitry includes a lookup table preloaded with sequences of output signals, with the sequence selected by a controller.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic. Moreover, it provides a frequency-scalable circuit that unlike a conventional phase-and-frequency detector (PFD), does not rely on asynchronous elements.

Abstract: A method for synchronizing a plurality of sub-systems, comprising the steps of measuring a relationship between a divider associated with each of the plurality of sub-systems; and adjusting a phase of one or more of the dividers to a known relationship with one of the dividers. A command is issued synchronous to a divider associated with one of the plurality of sub-systems. The command is received at one of the sub-systems and is acted upon synchronous to a divider associated with the one of the sub-system receiving said command.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A phase-locked loop circuit is arranged for equalizing pulse removal. The phase-locked loop circuit includes a multi-phase pulse generator circuit that is arranged to provide a feedback signal and a gate signal from an output of a voltage-controlled oscillation circuit. The gate signal leads the feedback signal by approximately one-fourth of a period. Also, an equalizing pulse removal logic circuit is arranged to provide a sync gate signal from the feedback signal, the gate signal, and a sync signal. The sync gate signal is provided such that, if the sync signal includes equalizing pulses, the sync gate signal corresponds to an inactive logic level during the equalizing pulses. A phase-frequency detector of the phase-locked loop circuit is gated such that the phase-frequency detector is not changed by the sync signal if the sync gate signal corresponds to the inactive logic level.

Abstract: An apparatus for generating multi-phase signals includes a delay chain to produce multi-phase signals, a slow boundary signal, and a fast boundary signal. An array of trim capacitors is connected to the delay chain. A timing control window circuit produces a control signal when a reference signal is outside a timing control window defined by the slow boundary signal and the fast boundary signal. A digital circuit produces a digital capacitive trim signal for application to the array of trim capacitors in response to the control signal. The digital capacitive trim signal alters the capacitive loading of the delay chain.

Abstract: Method and apparatus for performing joint timing recovery in a digital receiver using multiple input signals. The apparatus comprises a plurality of phase detectors, a summer, a level shifter, a loop filter and a numerically controlled oscillator NCO. The phase detectors produce a phase signal by comparing a timing signal produced by the NCO with the input signals. The phase signals are then summed and the level shifter adjusts the summed value to compensate for the number of signals used to form the sum, i.e., the summed value is adjusted to be within the input range of the NCO.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: Techniques are described for producing a signal having a desired frequency. The desired frequency can be produced to a very high precision, even when the desired frequency is very high. The techniques, in one example, represent an intermediate, otherwise non-available frequency, by dithering between two exact frequencies. Then, over some reasonably short timescale, the desired frequency is provided to high precision. Such precise frequency output may be used for, for example, measurement transmission and other uses. The techniques can be implemented in low-cost hardware, and may provide a precision of, for example, 10?6% for many frequencies.

Abstract: There is provided a transmission circuit which can certainly perform transmission of data of digital form between two circuits operating in synchronization with two clock signals having the same frequency even if phase shift is generated between the two clock signals. According to a phase difference between a clock signal CK1 and a clock signal CK2, the transmission circuit performs either one of an operation of outputting pre-transmission digital data inputted to the transmission circuit as it is or after it is inverted, and an operation of sampling it in synchronization with the clock signal CK2 and outputting it as it is or after it is inverted.

Abstract: A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface that has a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array that has programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from between a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network that selects a signal from between a clock signal from the interface and a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: In accordance with one embodiment of the invention a circuit includes a split delay-chain, a phase detector, and a voltage controlled oscillator (VCO) coupled so as to produce a clock signal based on a non-external reference.

Abstract: A synchronous circuit according to an embodiment of the present invention, comprising: a clock selector configured to select a suitable phase clock signal from a plurality of clock signals differing in phase from each other in accordance with a clock-selecting signal; a phase comparator configured to compare a phase of input data with that of the selected clock signal; a phase control circuit configured to generate a phase control signal in accordance with the comparison result obtained by the phase comparator and to generate the clock-selecting signal in accordance with a offset control signal; and a frequency offset control circuit configured to generate the offset control signal in accordance with the phase control signal.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a PhaseLock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A method for optimizing loop bandwidth in a delay locked loop is provided. A representative power supply waveform having noise is input into a simulation of the delay locked loop; an estimate of jitter is determined; and the loop bandwidth of the delay looked loop is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing loop bandwidth in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize loop bandwidth in a delay locked loop is provided.

Abstract: A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase-locked loop (PLL) circuit in another implementation. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit generates a synchronized clock signal that is distributed throughout the programmable integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. The clock synchronization circuit improves the overall performance of the programmable logic integrated circuit.

Abstract: A clock signal generator having a DDS circuit which adds up a frequency word with a particular frequency and generates an output pulse when an overflow occurs. To reduce jitter, a parameter value corresponding to the ideal overflow time of the DDS circuit is determined and an output pulse generating circuit determines, in dependence on the parameter value and using a further, higher frequency, a corrected time for the output pulse and outputs the output pulse at this corrected time.

Abstract: The invention relates to a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock. A control signal for rapidly adjusting the DLL circuit is converted into a delayed control signal, which is kept constant with the rising edge of a counter clock signal. This prevents instabilities of the counter value from occurring.

Abstract: A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb2. The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb2. The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2. enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb2.

Abstract: In accordance with one embodiment of the invention a circuit includes a split delay-chain, a phase detector, and a voltage controlled oscillator (VCO) coupled so as to produce a clock signal based on a non-external reference.

Abstract: An input data signal is digitally sampled by a data sampling section using an N-phase clock signal including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal including N sample data signals is obtained. An edge point detection operation section detects edge points in the N sample data signals in one cycle of an extracted clock signal and outputs an edge point operation output signal. A clock signal extraction section selects a clock signal from the N-phase clock signal based on the information of the edge point operation output signal and outputs the selected clock signal as the extracted clock signal. A delay section delays the N sample data signals of the parallel sample data signal and thereby outputs a parallel delayed sample data signal including N delayed sample data signals.

Abstract: A switching circuit includes an insulating substrate including two signal transmission lines; a switching diode mounted, in series between the two signal transmission lines, on the insulating substrate, wherein an anode terminal and a cathode terminal are connected to the two signal transmission lines, and the switching diode is turned on or off; and a conductive pattern formed, below the switching diode, on a mounting face of the insulating substrate on which the switching diode is mounted, wherein the conductive pattern is grounded. There are stray capacitances between the anode terminal and the conductive pattern and between the cathode terminal and the conductive pattern.

Abstract: In a clock control circuit, a multiplication factor setting unit outputs a multiplication factor. A buffer circuit holds a previous multiplication factor and the multiplication factor output by the multiplication factor setting unit and compares the two multiplication factors. When the multiplication factors are different from each other, a clock state control circuit provides a control to, stop the output of clock to the outside, switch the clock to a clock other than those output by the PLL oscillation circuit, change the multiplication factor in the PLL oscillation circuit, switch the clock to clock output by the PLL oscillation circuit after the PLL output clock is stabilized, and restart output of the clock to the outside.

Abstract: A PLL device has a voltage-controlled oscillator, a reference generator that generates reference signals with different phases, and a main divider that divides the frequency of the output signal of the voltage-controlled oscillator by a frequency-division ratio N1. An auxiliary divider divides the frequency of the output of the main divider by a frequency-division ratio N2. A distribution circuit distributes the output of the auxiliary divider as feedback signals. Phase detectors compare the reference signals and the feedback signals, and generate error signals. Each of the main divider and the auxiliary divider has a programmable divider or a counter. The main divider and the auxiliary divider are both operative during start-up to shorten PLL lock-up time, and the auxiliary divider then powers down to reduce power consumption.

Abstract: A PLL system (200) includes a clock sequence generator (190). Clock sequence generator (190) provides a clock that steps down from a fast frequency through several steps to a frequency of zero. This step-down non-linear digression of frequencies causes a counter (110) driving a tank circuit of a self-calibrating VCO to achieve lock at an extremely rapid rate. The PFD (150) generates an analog signal based on the phase and frequency relationship of the reference and feedback clock signals. The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit (120) and the signals UP and DOWN are supplied to the counter (110). The counter (110) provides a count value that controls the resonant frequency generated by the tank circuit. The convergence speed of the PLL system (200) is accelerated by the effects of the step-down clock provided by the clock sequence generator (190).

Abstract: Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices.

Abstract: A system and method is described for providing a single pin reset for a mixed signal integrated circuit. The system and method provides for a single reset signal/pin of the integrated circuit to be utilized to generate all internal resets for the analog and digital circuitry/sections of the mixed signal integrated circuit. In one form, a state machine generates a reset signal for a phase locked loop synthesizer that is utilized to generate internal system clocks for the analog and digital circuitry, as well as a digital reset signal that provides reset signals to the various digital sections circuitry of the integrated circuit. Preferably, the chip reset signal is provided for a longer period of time than the PLL reset signal in order to assure that the PLL is running and generating clocking signals before the digital logic is clocked.

Abstract: A synchronous quad clock domain system synchronizes an external primary and secondary clock (130, 132) with an internal primary and secondary clock (134, 136). The rising edge of the internal primary and secondary clock signals are matched and a synchronous multiple ratio is applied to the internal primary clock signal to produce the internal secondary clock signal. The phase of the internal and external secondary clock signals are matched. The external secondary clock signal is sampled to produce a external sample signature and the external sample signature is matched to a pattern corresponding to the synchronous multiple ratio to produce an external clock cycle signal. The internal secondary clock signal is also sampled to produce an internal clock cycle signal. The internal and external clock cycle signals are compared and a phase adjust signal is provided to match the phase of the internal and external secondary clock signals.

Abstract: The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: An A/D converter (30) samples an analog signal synchronously with a sampling clock from a VCO (70). These sampled values are stored in a shift register (410). A code judging section (420) detects the positive/negative sign pattern (time-series code pattern) of the sampled values held in storage elements (S0 to S5) of the shift register (410) and stores the sampled values in predetermined register (431 to 434) according to the detected sign pattern. According to this, a calculating section (430) determines the phase difference between the analog signal and the sampling clock. The phase difference is fed to a VCO (70) through a D/A converter (50) and a loop filter (60).

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase-Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Abstract: A clock output controller using a digital frequency synthesis minimizes the clock output disturbance due to input reference signal switchover. The controller includes a first and a second accumulator where the Most Significant Bit (MSB) of the first accumulator output generates the clock output signal and the MSB of the second accumulator generates a feedback signal. A reset control signal is generated by the transition edge detector/switchover controller and it is coupled to the register block of the second accumulator in order to reset the feedback signal at an appropriate time so as to match the phase of the new reference signal. A hold control signal is also generated to keep the clock output locked on the old reference signal until the feedback signal is locked to the new signal. The hold signal is then reset once locking to the new reference signal is accomplished and the clock output is fully switched over with minimal disturbance.

Abstract: A system and method for switching between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a phase locked loop (PLL) circuit. The phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing an input clock signal from a first clock source failure. The phase detector is coupled to receive the input clock signal and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL, with the feedback signal indicative of the output signal. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure.

Abstract: A digital PLL circuit, which can realize a high accurate hold-over function even in case that power supply voltage or ambient temperature is changed, is provided. The digital PLL circuit provides a first, a second and a third loop circuits. In the third loop circuit, an adder and a differentiator calculate a difference between a frequency of a signal outputted from a fixed frequency oscillator and an output frequency, and a memory circuit memorizes the difference calculated at the adder and the differentiator, and another adder compares the difference between the frequency of the signal outputted from the fixed frequency oscillator and a current output frequency with the difference memorized in the memory circuit. And a frequency of a signal outputting from a voltage controlled oscillator (VCO) is controlled by the compared result.

Abstract: A circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.

Abstract: A digital PLL's stability and immunity to jitter are improved by deriving the correction to the state machine count from an average over several computations of the phase error, and re-initializing the computation of the phase error to the residual error remaining after the correction. The PLL stability is improved by retaining all of the phase errors measured during a succession of plural phase measurement intervals and by retaining the residual error in the next cycle of cumulative phase error. The plurality of phase errors thus obtained are averaged together starting from the residual error left over from the previous cycle, and the state machine internal count is corrected (updated) in accordance with this average, rather than according to an instantaneous phase error. As a result, the performance of the PLL is less susceptible to jitter-induced temporary excursions in the phase error, a significant advantage.

Abstract: An apparatus including a clock circuit and a control circuit. The clock circuit may be configured to generate a first output clock, a second output clock and a first control signal in response to (i) a first input clock, (ii) a second input clock, (iii) a second control signal and (iv) a third control signal. The control circuit may be configured to generate the second control signal and the third control signal in response to the first input clock and the first control signal. The first and second output clocks may have a skew less than a predetermined threshold.