Abstract: A clock signal generator comprises a phase locked loop circuit and a voltage level converting circuit. The phase locked loop circuit is supplied with a control base clock signal and an input clock signal which has a first frequency. The phase locked loop circuit converts the input clock signal to generate a PLL output clock signal which has the second frequency. The input clock signal has one of binary values that has a voltage level which is similar to a reference voltage level of a reference voltage. The voltage level converting circuit is supplied with the PLL output clock signal, the control base clock signal, the reference voltage, and a voltage level control signal. The voltage level converting circuit converts, in response to the control base clock signal, the reference voltage, and the voltage level control signal, the PLL output clock signal to generate an output clock signal which has an output voltage level which is different from the reference voltage level.

Abstract: A method and apparatus for recovering the time base of signals which change at periodic intervals is disclosed. The apparatus comprises gated voltage controlled oscillators (GVCO) that are alternated or exchanged, to reduce phase and frequency deviations in the recovered time base signal, such as the deviations induced by inherent GVCO differences. Each GVCO is stabilized by a respective phase locked loop. The respective GVCOs are gated only in response to a chosen polarity transition in the input signal, to make the circuit more tolerant of waveform distortions. More than two GVCOs may be used to provide improved frequency drift resistance. The circuit uses resynchronization control signals, such as the time slot signal in synchronous switching systems, to indicate resynchronization or reassignment of the GVCOs in gaps in the data transmission.

Abstract: The digital phase detector detects a phase shift between a comparison clock pulse signal (VT) and a reference clock pulse signal (RT). It includes logic gates (STO,STA) for generating start and stop pulses from respective successive pulses of the comparison and reference clock pulse signals (RT,VT). A counter (ZG,Z) counts the pulses of a counter clock pulse signal (ZT) of a higher frequency in a time window between the start signal and the subsequent stop signal. The counter value of the counter is a measure of the phase shift between the comparison and reference clock pulse signals (VT,RT). Quantization errors in the phase shift signal are considerably reduced by providing a logical gate (VZ) for determining the sign of the phase shift and a device (.mu.P) for adding a constant, advantageously 0.5, to the counter value.

Abstract: A fractional-N frequency synthesizer comprises a voltage-controlled oscillator (107) for generating an output signal (F.sub.o) in response to a control voltage derived by a digital-to-analog converter (105) from a digital error signal (e). The error signal is derived by a differencing device (103) which subtracts a digital signal (D.sub.o) representing the actuated frequency of the output signal from an input signal (F.sub.d) having the desired frequency for the output signal. The digital signal representing the output signal frequency is derived by a frequency discrimination device (101) which determines the instant frequency of the analog output signal and provides a corresponding digital representation with zero static frequency error. In preferred embodiments, the frequency discrimination device is a delta-sigma frequency synthesizer in combination with a decimator (102). This frequency synthesizer configuration avoids deficiencies due to non-linearity and noise sensitivity of analog phase detectors.

Abstract: An oscillating circuit 30 outputs a signal .o slashed..sub.o whose pulse cycle T is a linear function T=kS+m of a control input value S. A frequency control circuit 10, every time a counter 11 counts a number Nr of pulses of a reference signal .o slashed..sub.r, calculates S=No-m/k, where No is a count of .o slashed..sub.o counted by the counter 12, makes a judgement on convergence of .o slashed..sub.o based upon the difference between input and output values of a register 14, makes the register 14 hold S, updates Nr=S+m/k and clears the counter 12 to 0. A digital phase control circuit 20 judges a advance/delay of the phase of .o slashed..sub.o relative to .o slashed..sub.

Abstract: A dual phase-locked loop (PLL) clock synthesizer is disclosed for generating clock signal in synchronization with the data input signal received over a network environment. The dual PLL clock synthesizer is suitable for processing data streams of any bit sequence without data error caused by interference due to clock signal jittering phenomena. The dual PLL clock synthesizer is particularly suitable for application to high-speed Ethernet network environment such as for decoding to obtain the original data conveyed over the network through selected encoding scheme.

Abstract: A digital loss of lock detection (LLD) device for a phase looked loop (PLL) generates a locked frequency signal synchronized with a reference frequency signal. The LLD comprises first to fifth latching means for detecting when the reference clock failed high/low, when the locked clock failed high/low and when the reference clock is outside the tracking range of the PLL. The first to fifth latching means provide respectively a first to fifth error signals for each type of the above faults.

Abstract: A circuit for synchronizing a multiplied system clock signal includes a device for generating a system clock signal, a first device that receives the system clock signal and generates a synchronization signal and at least one second device that receives the system clock signal and the synchronization signal. Each of the second devices includes a device for multiplying the system clock signal to produce the multiplied system clock signal and a device for synchronizing the multiplied system clock signal with each other multiplied system clock signal produced by the other second devices based on the synchronization signal.

Abstract: A phase control circuit adjusts the width of a PLL clock signal so that a PLL clock signal generated from a master clock signal MCK is in synchronization with an EFM signal. A velocity detector detects offset in velocity by counting a pulse width of an EFM signal with a master clock signal MCK. The phase control circuit alters the pulse width of a PLL clock signal according to the detected offset in velocity to alter the average frequency of a PLL clock signal in proportion to offset of the rotational speed.

Abstract: Asynchronously-generated digital and analog clocks in a mixed-signal test system are accurately aligned for repeatable and deterministic testing. A variable-frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal. A resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal. The analog clock signal is thus phase-aligned with the master clock signal in a known and deterministic relationship. The resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test. Aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test-to-test. A phase-locked loop removes spurs from the synthesized analog clock signal.

Abstract: In a new formulation for digital phase-locked loops, loop-filter constants are determined from loop roots that can each be selectively placed in the s-plane on the basis of a new set of parameters, each with simple and direct physical meaning in terms of loop noise bandwidth, root-specific decay rate, and root-specific damping. Loops of first to fourth order are treated in the continuous-update approximation (B.sub.L T .fwdarw.0) and in a discrete-update formulation with arbitrary B.sub.L T. Deficiencies of the continuous-update approximation in large-B.sub.L T applications are avoided in the new discrete-update formulation.

Abstract: A frequency synthesizer circuit for the front end of an RF system. The frequency synthesizer uses two pulse-swallow phase-locked loops in a synthesizer architecture that produces an output frequency that is a function of the two reference frequencies used as inputs into the two phase-locked loops. As a result, the frequency synthesizer can be incremented in steps equal to the differential of the reference frequencies of the two phase-locked loops, while the frequency outputs of each of the phase-locked loops can be incremented in much larger steps. This enables the two phase-locked loops to employ relatively large bandwidths, thereby achieving a faster signal lock as well as a better suppression of the voltage controlled oscillator (VCO) phase noise in each loop. The use of a dual loop synthesizer architecture allows for feedback correction of the VCO phase noise outside the loop bandwidth.

Abstract: The clock generator of this invention includes: an input shutoff control circuit for receiving a base clock and a reference clock and outputting a first signal and a second signal in response to a reset signal, a phase comparator for outputting a phase difference signal indicating a phase difference between the first signal and the second signal; a voltage control oscillator for outputting a frequency variable clock in correspondence with the phase difference signal; and a voltage fixing control circuit for controlling a voltage of the phase difference signal in response to the reset signal, wherein, when the reset signal is in a first level, the input shutoff control circuit: outputs the base clock to the phase comparator as the first signal and outputs the reference clock to the phase comparator as the second signal, and the voltage fixing control circuit holds the voltage of the phase difference signal, and when the reset signal is in a second level different from the first level, the input shutoff control

Abstract: A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.

Abstract: A fault tolerant computer according to the invention includes a processing unit including a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second, abbreviated system bus to receive read data from said first system bus. Coupled to said processing unit is an Input/Output device for interfacing to external devices. The processing unit includes a phase detector apparatus for aligning a clock of the processor unit to that of the Input/Output unit to facilitate data transfer. The phase detector apparatus includes a first means for providing a first clocking signal related to the clocking signal of the Input/Output unit, and a second means for providing a second clocking signal related to the clocking signal of the processor unit. The phase detector apparatus further includes means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

Abstract: The phase-locked loop includes means (3) for generating an internal signal (SIN) drawn from the output signal of the voltage-controlled oscillator (2), and a phase comparator (4) able to compare the phase of the internal signal (SIN) with that of an external signal received (SSY), and the output of which is looped back onto the voltage-controlled oscillator (2). It further comprises a device (6) accelerating the synchronization of the internal and external signals, including processing means able to receive, from the phase comparator (4), a predetermined indication representative of the non-coincidence of the internal and external signals, and, in response to this predetermined indication, to deliver control information in response to which the generation means (3) modify the phase of the internal signal in order to force the latter substantially into phase with the external signal (SSY).

Abstract: A method and apparatus for performing frequency acquisition. Frequency acquisition is accomplished by utilizing binary-search techniques with a controller (13), variable digital oscillator (16), frequency detector (11) an incrementor (19) and decrementor (21) and control registers (22). The frequency detector (11) generates an output indicating the relative speed of the variable oscillator (16) with reference to a externally provided signal. Depending on the output of the frequency detector (11 ), the arithmetic logic circuitry (19, 21) will increase or decrease the value in a control register (22), resulting in a corresponding increase or decrease in speed of the variable oscillator (16). The magnitude of changes to the control register (22) is gradually reduced as the steps of frequency detection and arithmetic updates are repeated until the variable oscillator (16) has reached the proper frequency.

Abstract: A circuit for attenuating phase jitter on an incoming clock signal includes a digital frequency synthesizer, and a phase lock loop including a phase detector. The digital phase detector compares the phase relationship between an incoming signal and a clock signal generated by the digitally controlled frequency synthesizer and produces an output signal proportional to the phase difference. The output signal comprises both a direction indicator and a magnitude indicator for controlling the digitally controlled frequency synthesizer. One of a plurality of phases of a voltage controlled oscillator (VCO) are selected in response to the output signal to alter the frequency of the clock signal.

Abstract: A digital phase-locked loop circuit includes circuitry for generating substantially periodic recovered clock signals each one corresponding to a discrete amount of delay from a local clock signal. Incremental delay is added or subtracted at each clock generation cycle until the data input signal and the last-generated recovered clock signal are substantially phase-aligned. The circuit includes delay measurement circuitry for dynamically measuring the smallest quantity of delay units required to provide at least a 360 degree phase shift of the local clock signal. The circuitry for generating the recovered clock signals is then constrained to generate clock signals having a maximum delay corresponding to the last-measured quantity of delay.

Abstract: The present invention relates to a circuit board having a plurality of integrated circuits provided thereon, wherein each integrated circuit (IC) receives a common clocked input reference signal and outputs a dam signal. Each integrated circuit is provided with a de-skewing circuit which compensates for signal delays in the IC so as to synchronize the output data signal with the clocked input reference signal. The de-skewing circuit is operative to generate a simulated signal delay to the input signal which emulates the signal delays of the IC.

Abstract: A clock signal distribution system for a digital electronic system operating at high clock speed and short cycle times distributes a primary clock signal which is of relatively low frequency through conventional hardware. A high frequency secondary clock signal is generated using a phase locked loop to maintain high accuracy synchronization with the primary clock. Delay means are provided for both the primary and secondary clock signals to provide compensation of propagation time or to provide desired offsets. The phase locked loop arrangements with delays can be cascaded to provide flexibility of both frequency and phase of signals throughout the system, any or all of which may be maintained in synchronism with the primary clock. A dynamic digital transfer function generator is also used within the phase locked loop to achieve particular synchronization functions.

Abstract: A clock synchronizing circuit includes a voltage controlled oscillator (VCO) for producing an output signal whose oscillation frequency changes in response to control signals. A phase comparator compares a phase of an input signal and a phase of the output signal to thereby generate a phase difference signal. A filter filters the phase difference signal to thereby output a filtered phase difference signal. A frequency synchronizing circuit responsive to the filtered phase difference signal generates a first compensation signal for controlling a frequency of the output signal. A phase synchronizing circuit responsive to the filtered phase difference signal generates a second compensation signal for controlling a phase of the output signal. A signal supplying circuit feeds the first and second compensation signals as the control signals.

Abstract: A digital phase-locked loop includes a digital controller whose output is coupled to a controllable oscillator and which loop comprises a phase detector (PD) whose two inputs are provided to receive a pulse-shaped reference signal (REF) and a pulse-shaped oscillator signal (OSC) generated by the oscillator. This phase detector comprises a first circuit branch provided to receive the reference and the oscillator signal, to form a pulse-shaped signal whose pulse width is equal to the distance in time between two specific successive pulse edges of the reference and oscillator signal, to filter by low-pass filter the pulse-shaped signal and to code sample values of the low-pass filtered signal with a first number (Nf) of least significant bits.

Abstract: A nested digital phase lock loop (DPLL) circuit (400) provides center bit sampling for incoming recovered data (406). Included in the nested DPLL circuit (400) are a narrow bandwidth DPLL (402) and a wide bandwidth DPLL (404) which generate first (410) and second (428) recovered clock signals respectively. Initially the first recovered clock signal (410) is used to clock in the recovered data (406) until the narrowband DPLL (402) is stabilized. Once the narrowband DPLL (402) is stabilized, the second recovered clock signal (428) generated from the wideband DPLL (404) is switched in by a multiplexer (424). If for any reason the center bit sampled data becomes corrupted, a RESET occurs in the wideband loop (404) to zero out the phase shift of the second recovered clock signal (428) to match that of the narrow loop. Thus, when a RESET occurs, the wideband loop is tracking at exactly the same clock rate as the narrowband loop.

Abstract: A method and apparatus for implementing a constant gain in a digitally-controlled variable oscillator (DCO) 16 where the frequency of the DCO 16 is controlled via binary-weighted control signals. The frequency of the DCO 16 is modulated via arithmetic increments or decrements to the binary-weighted DCO control signals. The magnitude of the arithmetic increments and decrements defines the gain of the DCO. To maintain a constant gain, regardless of operating point or environment, a phase gain register 15 bit-shifts a current DCO control value by a predefined number of bit positions, thereby determining a phase gain value. The phase gain value defines the magnitude of an arithmetic increment or decrement of the current DCO control value, used to determine the next DCO control value. Since the phase gain register 15 uses a bit-shifted version of the current value of the DCO control, the gain value dynamically tracks all updates to the DCO control value, thereby implementing a constant gain in the DCO 16.