Abstract: A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

Abstract: A phase detecting module includes a phase detecting unit, a comparator and a counter. The phase detecting unit is arranged to compare a first input signal and a second input signal to generate a phase detecting result. The comparator is arranged to compare the phase detecting result and a predetermined voltage to generate a comparing result. The counter is arranged to count one of the first input signal and the second input signal to generate a counting value. The phase detecting result and the counting value are reset if the counting value reaches a predetermined value, and the comparing result is outputted to a target device from the comparator if the counting value reaches a predetermined value.

Abstract: A circuit for generating an output enable signal includes a reset signal generator for synchronizing a reset signal with an external clock signal to generate an output enable (OE) reset signal, synchronizers for synchronizing the OE reset signal with an internal clock signal to generate a source reset signal, and an output enable signal output unit, reset by the source reset signal, for counting pulses of the external clock signal and the internal clock signal to output an output enable signal corresponding to a read command and CAS latency.

Abstract: A resistor/capacitor identification detection (RCID) circuit may provide system level identification of hardware (e.g. circuit board ID) through a single pin interface, by identifying up to a specified number of more than two quantized RC time constant states by measuring the discharge and charge times of an external RC circuit coupled to the single pin. The RCID circuit may initiate the discharge followed by a charging of the external RC circuit. The signal developed at the signal pin may be provided to the input of a threshold detector, with the threshold set at a specified percentage of a supply voltage used for operating the RCID circuit. The digitized output of the threshold detector may be used to gate a counter, after having been filtered through an input glitch rejection filter. A resolution of the counter may be determined by a high frequency clock used for clocking the counter. The numeric values of the charge and discharge times may be stored in data registers comprised in the RCID circuit.

Abstract: A phase selection circuit having a selection circuit, binary weighted current sources, and an amplifier circuit. The phase selection circuit is configured for selecting adjacent phase signals from a number of equally-spaced phases of a clock signal, based on a phase selection value. The selection circuit outputs the adjacent phase signals to respective first and second binary weighted current sources, along with a digital interpolation value. The first current source outputs a contribution current onto a summing node based on the first adjacent phase signal and the digital interpolation control value, and the second current source outputs a second contribution current to the summing node based on the second adjacent phase signal and an inverse of the digital interpolation control value, resulting in an interpolated signal. An amplifier circuit outputs the interpolated signal as a phase-interpolated clock signal according to the phase selection value.

Abstract: A digital frequency/phase recovery circuit includes a comparator with hysteresis, a counter, a frequency determiner, a multi-phase clock generator, a transition detector, a phase adjuster, and a multiplexer. The comparator with hysteresis receives the input signal and generates a comparison signal. The counter receives the comparison signal, calculates the pulse number of the comparison signal in one period, and outputs a pulse value. The frequency determiner receives the pulse value, calculates the frequency of the input signal, and generates a frequency value. The multi-phase clock generator receives the frequency value and generates multi-phase reference clocks according to the frequency value. The transition detector receives the comparison signal and generates a transition signal.

Abstract: First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode, an output circuit outputs signals exhibiting normal-phase and reversed-phase PWM waveforms based on both of the signals of the first and second counter circuits. In a second output mode, the output circuit outputs signals that are each based only on either of the signals of the first and second counter circuits.

Abstract: The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit selectively generates divided clock signals CLK1, CLK2. A discrete value correction circuit controls the clock divider circuit so as to repeat C times the process of generating the clock signal CLK2 once and the clock signal CLK1 (Q?1) times and then to generate the clock signal CLK1 R times if C<D and so as to repeat D times the process of generating the clock signal CLK1 once and the clock signal CLK2 (Q?1) times and then to generate the clock signal CLK2 R times if C>D. A, B, and C are natural numbers satisfying freq=fref/(A+C/B). In D=B?C, Q is a quotient of B/C if C<D or a quotient of B/D if C>D.

Abstract: Methods and apparatuses for detecting an in-band reset using digital circuitry. A first counting circuit is coupled to receive a first clock signal and to generate output signals based on a number of cycles of the first clock signal. A second counting circuit is coupled to receive a second clock signal and the output signals from the first counting circuit. The second counting circuit generates output signals based on number of cycles of the second clock signal. A comparison circuit is coupled with to receive the output signals of the second counting circuit and to generate a reset signal if the output signals from the second counting circuit correspond to a pre-selected range.

Abstract: A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein an average rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates a modulated error value based on the snapshots and a modulation value, where the modulation value is used to spread the spectrum of the output clock. The tapped delay line module produces the output clock based on the modulated error value.

Abstract: A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for generating a control signal to control an operation of the DLL driver in response to a signal having information associated with an active mode. The DLL driver controller is provided with a counter for counting the DLL clock to produce a count a setting value having a plurality of bits and generating an activated equal signal if the two values are the same, and an SR latch for accepting the equal signal and the signal having the information associated with the active mode to provide the control signal.

Abstract: An increment/decrement circuit for use with a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. In one embodiment, the increment/decrement circuit includes a delay circuit block operable to receive and align the debug data. First and second mask circuits are connected in parallel to the delay circuit block in order to select and assert portions of the aligned debug data for incrementing and decrementing, respectively. An accumulation circuit is connected to the first mask circuit and the second mask circuit for generating an accumulated value based on the outputs of the mask circuits.

Abstract: According to the present invention, there is provided a semiconductor device including: a phase locked loop circuit having, a phase frequency detector which receives a reference signal and a frequency-divided signal, and outputs a phase difference detection signal by performing phase comparison, a charge pump which receives the phase difference detection signal and outputs a charge pump signal by converting a voltage change into a current change, a loop filter which receives the charge pump signal, and outputs a control voltage by passing components having frequencies not more than a predetermined frequency, a voltage controlled oscillator which outputs a frequency signal having a frequency based on the control voltage, and a frequency divider which receives the frequency signal, and outputs the frequency-divided signal by dividing the frequency; a mask signal generator which generates a mask signal masking a timing at which the phase frequency detector compares phases of the frequency-divided signal and the

Abstract: A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. The clock signals of different phases are selectively fed back to the phase frequency detector. In this way, the frequency of the output signal is changed, which achieves spreading spectrum.

Abstract: Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles of the common clock signal. One of the plurality of phases is selected (308) for each of the serial bitstreams based upon the activity detected within the selected phase. Data is then extracted (322) from the selected phase for each of the serial bitstreams using the common clock signal to thereby bit synchronize each of the plurality of serial bitstreams to each other.

Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.

Abstract: An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.

Abstract: A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.

Abstract: The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the synchronization circuit comprising a delay monitor adapted to produce a delayed input signal, a counter adapted to determine a difference between the input signal and the delayed input signal and produce a coarse timing signal in response thereto, a circuit adapted to produce a fine timing signal based on the input signal, and a circuit adapted to combine the coarse timing signal and the fine timing signal to produce an output signal.

Abstract: One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the occurrence of the initial change of a performance due to a variation or variety factors through a manufacturing process, but also at the time of the occurrence of the time elapsed change.

Abstract: A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input parallel lines and a plurality of output parallel lines and is switched to one of a first output state and a second output state in accordance with the internal control signal. In the first state, the data multiplexer outputs parallel data, which is input to the plurality of input parallel lines and read out from the memory core unit, to the plurality of output parallel lines corresponding to the plurality of input parallel lines. In the second state, the data multiplexer selects 1-bit data of the parallel data input to the plurality of input parallel lines and outputs the 1-bit data to the plurality of output parallel lines. A conversion circuit converts the parallel data into serial data.

Abstract: A circuit generates a qualified data read strobe signal from a start burst signal and a bidirectional data strobe signal in a DDR memory control module. The circuit includes a delay module that receives the start burst signal and that generates a delayed start burst signal. An enable signal generator receives the delayed start burst signal and generates an enable signal. A first circuit generates the qualified data read strobe signal based on the enable signal and the bidirectional data strobe signal.

Abstract: A method and circuit capable of handling skew between a clock and data signal up to +/? one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first sampling region and in a second sampling region and determining a difference between a number of transitions in the first sampling region and a number of transitions in the second sampling region. The sampling regions and a deskew timing signal may then be incremented or decremented based on a comparison of the computed difference to a predetermined constant. If no transitions occur on a particular bit, the algorithm times out leaving the deskew timing signal in the original position. When analysis of a final bit of a channel is completed, the algorithm begins monitoring and analyzing the first bit of another channel.

Abstract: A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for outputting the local clock signal as a phase-adjusted local clock having a selected phase based on a phase selection value specified by the counter. The synchronizer is configured for digitally sampling the received reference clock relative to the phase-adjusted local clock, and outputting a digital phase bit identifying whether the phase-adjusted local clock has a later phase relative to the received reference clock. The counter selectively increments or decrements a counted value based on the digital phase bit, and outputs to the phase selection circuit a prescribed number of most significant bits from the counted value as the phase selection value.

Abstract: A digital-control phase-composing circuit system has a phase-composing circuit which is supplied with two input clock signals having a phase difference therebetween and a control signal, and which composes an output clock signal having a phase between the phases of the two input clock signals on the basis of weighting through the control signal, a binary comparison circuit which compares the phase of the output clock signal to the phase of a reference clock signal, a first up/down counter which increments or decrements a first count value on the basis of the result of comparison made by the binary phase comparison circuit, outputs the most significant bit of the first count value, and outputs a clock pulse when a carry or a borrow occurs in the first count value, and a second up/down counter which operates on the basis of the clock pulse as an operating clock, increments or decrements a second count value on the basis of the most significant bit of the first count value, and outputs the second count value as

Abstract: Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.

Abstract: A synchronizing circuit includes a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock. The circuit further includes a variable frequency divider configured to generate a fourth clock by subjecting a third clock to frequency division at a frequency division ratio set in accordance with the frequency division ratio control signal, and a clock generator configured to subject the fourth clock supplied from the variable frequency divider to frequency division at a predetermined frequency division ratio, and generate the second clock such that the second clock synchronizes with transfer data which is supplied from an outside of the synchronizing circuit.

Abstract: A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A reference counter is clocked by a reference clock and has a reference count. A control circuit controls the delay and reference counters, compares a representation of the delay count to a representation of the reference count and responsively generates a modified value for the delay setting to reduce a difference between the representations of delay count and the reference count.

Abstract: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start of the period, which includes generating a first reference signal having a first reference signal frequency and a first reference signal phase synchronized with the start of the period, and detecting a first time interval required for the input signal phase to have a first specified relationship to the first reference signal phase. The technique includes similarly determining a relative ending phase of the input signal at the end of the period. The technique includes determining an input signal temporal characteristic from the number of transitions and the relative beginning phase and the relative ending phase.

Abstract: A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies of a useful signal and the frequency of a reference signal exceeds a prescribed error limit value, where the useful signal and the reference signal are used to produce a pulsed signal whose pulse length is proportional to the frequency difference between the useful signal and the reference signal. The pulse length is then compared with a prescribed maximum pulse length, and the control signal is produced if the pulse length exceeds the prescribed maximum pulse length.

Abstract: A local timer includes a dividing counter which counts a first clock and outputs a reference counting signal divided from the first clock; a timing synchronizing timer which counts a timing synchronizing timer value in synchronization with a reference timer responsive to the reference counting signal; a first buffer which stores a counted value of the dividing counter in synchronization with a second clock, when operation is by the first clock; a second buffer which stores the timing synchronizing timer value in synchronization with the second clock, when operation is by the first clock; a first adder which adds a first or second offset value to the stored value in the first buffer in synchronization with the second clock, when the first clock is suspended; and a second adder which adds a set value to the timing synchronizing timer value responsive to a carry from the first adder.

Abstract: A method for synchronizing a plurality of sub-systems, comprising the steps of measuring a relationship between a divider associated with each of the plurality of sub-systems; and adjusting a phase of one or more of the dividers to a known relationship with one of the dividers. A command is issued synchronous to a divider associated with one of the plurality of sub-systems. The command is received at one of the sub-systems and is acted upon synchronous to a divider associated with the one of the sub-system receiving said command.

Abstract: A system is disclosed that detects data forwarding clock errors including both missing and additional clock signals. The system provides for a phase locked loop (PLL) that locks onto a data forwarding source synchronous clock signal wherein the PLL outputs a system clock whose frequency is the average of the data forwarding clock frequency. The data forwarding clock signals and the system clock signals are counted separately and when a discrepancy occurs the receiving system is informed that an error has occurred. The receiving system will handle the error in its routine fashion. The counters and the PLL are synchronized to be sure that the PLL has acquired a lock before the error detection is enabled.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A multimode clock recovery circuit for providing constant bit rate services in a cell relay network has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services.

Abstract: Circuits, devices and methods are provided for dividing a fast pulse signal by an integer M. A dual modulus prescaler receives input pulses, counts them, and generates one prescaled pulse for every Qth input pulse. Q is a division modulus, and has a different value depending on a modulus control signal. When the prescaler generates a prescaled pulse from an input pulse, it ignores the modulus control signal at least until the onset of a next input pulse. A program counter generates a reset signal when the prescaler receives the Mth input pulse. A swallow counter then changes the modulus control signal to a different value, and the prescaler starts dividing by a different modulus. Even if the prescaler had already received the onset of the next input pulse, it accounts for it properly, for dividing with the different modulus.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a counting value, and means for applying the first clock signal and a first counting value to the first counting circuit, so as to produce a first time base signal. According to the present invention, the integrated circuit comprises means for producing a second time base signal using the second clock signal and a second counting value, and means for calibrating the second counting value such that it is equal or proportional to the number of periods of the second clock signal occurring during a determined time interval equal to a period or to a whole number of periods of the first time base signal. Application particularly to the management of a timer in a microprocessor.

Abstract: A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling both the oscillator and the low power oscillator. The oscillator control circuit including at least one real time counter. The oscillator control circuit being so configured that the oscillator is energized when said oscillator control circuit is in a normal mode and that, when a power down signal is received: a) the oscillator control circuit measures an oscillation frequency of the low power oscillator, b) the oscillator control circuit uses the measured oscillation frequency of the low power oscillator to set the real time counter so as to maintain the power down mode for the predetermined time, c) the oscillator control circuit turns off the oscillator and uses the low power oscillator for the duration of the power down.

Abstract: A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.

Abstract: A phase-locked loop (PLL) has an analog divider in the feedback path that receives either the in-phase or quadrature-phase pair of outputs from a voltage-controlled oscillator (VCO) while the other pair, 90-degree out-of-phase, of outputs from the VCO is used for the PLL output. Phases between the PLL's input and output are inherently aligned. The analog output of the analog divider is converted to a digital clock signal and applied to a cascade of digital dividers to generate a reduced feedback clock. The reduced feedback clock is applied to the D input and the digital clock signal is applied to the clock input of a pseudo D-flip-flop that drives the feedback input of a phase-frequency detector that drives the charge pump to the VCO input. Another cascade of digital dividers and pseudo D-flip-flop re-align the reference clock input to the phase-frequency detector. Analog and digital re-alignment circuits reduce internal skew.

Abstract: The present invention is intended to provide a delay lock loop circuit which is capable of providing a minute delay amount with stability regardless of the variations in delay amount due to variations in temperature and power supply voltage for example and process conditions. On the basis of a up/down control signal from a delay amount detector, count value is counted from initial setting value up to maximum setting value or down to minimum setting value. When the count value has reached the maximum or minimum value, another count value is counted up and down, thereby cutting the noise component of the up/down control signal. Consequently, regardless of the variation in delay amount due to a delay line, a delay lock detector to which the latter count value is supplied operates normally, thereby outputting with stability a reference delay step count for obtaining a delay of 1T.

Abstract: A method for resynchronizing a clock signal, includes the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency with a programmable digital frequency divider to produce a second clock signal having a second frequency, measuring the second clock signal with a digital control circuit, and programming a programmable digital frequency divider with the digital control circuit, such that the second clock signal corresponds to the presettable clock signal.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a PhaseLock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.

Abstract: A programmable frequency multiplier receives data representing a desired multiplication ratio from a first configuration register. The ratio data is transferred to the frequency multiplier concurrently with the generation of an internal delayed reset signal which holds all configuration registers in a reset condition until the frequency multiplier achieves a locked state. The configuration registers are dependent upon the internal clock signal generated by the frequency multiplier for proper operation. By causing the configuration registers to renew operation only after the stable frequency multiplier operation the danger of corrupting the information in the configuration registers is minimized.

Abstract: The invention relates to a circuit configuration for the interference-free initialization of delay locked loop circuits with fast lock. A control signal for rapidly adjusting the DLL circuit is converted into a delayed control signal, which is kept constant with the rising edge of a counter clock signal. This prevents instabilities of the counter value from occurring.

Abstract: A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with the downward shift of the standard clock 34 to output a shift clock 72. The shift clock 72 is supplied to the pulse inserter 54. The phase controller 56 receives the standard clock 34 and generates a phase control signal 74 indicating cycles of the shift clock 72 to which the insert-pulses are inserted among a plurality of cycles of the shift clock 72. The pulse inserter 54 inserts the insert-pulses to the cycles of the shift clock indicated by the phase control signal 74. The phase-lock unit 58 generates a delay clock 82 by delaying the phase of the shift clock 70 oscillated by the ring oscillator 50 with respect to the phase of the standard clock, based on the standard clock and the shift clock 76 including the insert-pulses.

Abstract: A phase-locked loop (PLL) having a digitally controlled oscillator (DCO), where the DCO receives a digital control signal generated by the PLL and an externally generated oscillator clock signal and generates an output signal having a frequency greater than that of the oscillator clock signal. In one embodiment, the DCO is an analog PLL, such as a fractional-N frequency synthesizer, that receives a two-part digital control signal corresponding to the integer and fractional portions of a desired multiplier. The feedback path within the DCO has a dual-modulus divider that is controlled by a modulus controller to apply, over time, an effective divisor value that achieves the desired degree of multiplication. PLLs of the present invention are especially applicable to low-bandwidth, low-noise applications, such as high-multiplication frequency synthesizers and clock filtering, that are integrated into digital ASICs.

Abstract: A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.