Abstract: A multinode multiprocessor computer system with distributed local clocks wherein a local clock may be synchronized with other clocks in the system without affecting the operation of the other clocks. A local clock to be synchronized is reset and counts an elapsed time since the reset. Simultaneously with resetting the local clock, a clock value from a clock on a source node is stored. The clock value from the source node is copied to the node to be synchronized and added to the elapsed time. The resulting summation is then stored in the local clock to be synchronized. As a result, the local clock is synchronized to the clock on the source node. In one system embodiment, the local clock includes a dynamic register and a base register and an adder adds the two portions together to generate an output of the local clock. For a node being synchronized, the dynamic portion is reset and allowed to count the elapsed time while the base portion is loaded with a clock value copied from the source node.

Abstract: A clock control circuit includes a ring counter for outputting a signal of N bits count value and a complementary signal thereof; a rescue & flag generating circuit for effecting rescue from a bit pattern that is outside of expectations and generating a flag signal JBTFLG having a value corresponding to a combination of bits in a 2N-bit signal; a decoder; a clock selector for outputting a pair of clocks from multiphase clocks based upon a selection control signal from the decoder circuit; an interpolator for outputting a signal having a delay time corresponding to a time that is the result of internally dividing the phase difference between the pair of clocks; a phase comparator for comparing the phase of the interpolator output and the phase of a reference clock; and an interpolator control circuit, the shift direction of which varies, for outputting an interior-division ratio control signal that sets the interior-division ratio of the interpolator based upon the phase comparison by the phase comparator

Abstract: A method of detecting a frequency of a digital phase locked loop in an optical disc reproduction and/or recording apparatus, which includes (a) detecting an edge point of an input signal, (b) sampling a previous and following input signal on the basis of the detected edge point into a predetermined frequency, (c) counting a number of reference clock signals between the detected edge point and a sample which is positioned previously, adding a count value and an interval of time corresponding to the count value to obtain a frequency count value at the edge point, and (e) comparing the obtained frequency count value with a predetermined reference value, to enhance the frequency according to the comparison result can detect frequency having high resolution with only a reference clock frequency without heightening a frequency of a reference clock signal, to thereby enhance the quality of data.

Abstract: A method and apparatus for generating multiple locked self-timed pulsed clock signals is disclosed. Race margins are reduced over separate clock generating circuits by sharing the necessary delay circuit elements between the multiple clock generating circuits. An edge is gated with a delayed edge to form the first clock pulse. A subsequent second clock pulse is generated by gating a partially-delayed edge with the first clock pulse, which minimizes race margins and pulse evaporation.

Abstract: A timing adjusting circuit receives a clock and a data from an outside, and outputs the delayed data to the outside. A variable delay circuit receives the data and outputting the data delayed according to a value set by a delay value setting signal A first flip-flop has a data input terminal for inputting the data output from the variable delay circuit and a clock input terminal for receiving an inverse signal of the clock being frequency divided. A second flip-flop has a data input terminal for receiving a fixed value and a clock input terminal for receiving a signal output from the first flip-flop. A counter has a counter enable input terminal for inputting a signal output from the second flip-flop, counts the clock at every plural periods, and sends an output count value as the delay value setting signal to the variable delay circuit.

Abstract: A prescaler (200) includes a first frequency divider (204, 206) configured to receive an input signal at an input frequency. The prescaler further includes a phase rotator (208) coupled to the first frequency divider to produce a plurality of signal phases in response to the input signal. A frequency control circuit (214) is configured as a one-hot decoder to select one signal phase of the plurality of signal phases. The one-hot decoder provides maximum speed of operation of the prescaler by eliminating decoding of the feedback signal.

Abstract: The PLL (Phase Lock Loop) circuit generates a sampling clock for sampling an analog image signal and a second clock having a frequency equal to that of the sampling clock and a phase different from that of the sampling clock based on the horizontal synchronizing signal supplied together with the analog image signal. The measuring circuit counts the number of pulses of the sampling clock and the number of pulses of the second clock for a predetermined time period. The MPU (Micro Processing Unit) determines whether or not the numbers of pulses of the sampling clock and second clock have been counted correctly based on the number of pulses of the sampling clock and the number of pulses of the second clock. Then, the MPU adjusts the frequency and phase of the sampling clock, when it is determined that the numbers have been counted correctly.

Abstract: A delay locked loop circuit for conserving power on a semiconductor chip is provided. The circuit includes a delay chain circuit responsive to a clock input signal for generating an output clock signal having a selectively adjustable delay at an output circuit; a feedback loop circuit connects to and controls said delay chain circuit; and a pre-divider circuit connected to said delay chain circuit, wherein said pre-divider circuit is configured to disable the delay chain circuit when the output clock signal is inactive and the memory device is in an idle state (i.e., all banks closed).

Abstract: Disclosed is a delay locked loop (DLL) for use in a semiconductor memory device, which has the ability to reduce or eliminate a power supply noise, a random noise or other irregular noise. The DLL includes a controllable delay modification unit for delaying a clock signal fed thereto to produce a time-delayed signal, a comparator for comparing the time-delayed signal from the modification block and a reference signal, and determining an addition or subtraction of the time delay according to the compared result to produce a corresponding output signal, and a delay control unit for counting the number that the corresponding output signal is activated, and producing a signal for controlling the addition or the subtraction of the time delay to the modification unit, if the counted value satisfies a predetermined condition.

Abstract: A leakage current compensation system and method is disclosed that reduces frequency spurs and phase offset in a frequency synthesizer. The leakage current is determined based on the phase offset of the frequency synthesizer relative to a reference clock. A leakage current compensation circuit provides a leakage current compensation signal to the frequency synthesizer at the loop filter terminals to minimize the phase offset.

Abstract: A programmable digital phase lock loop produces an output bit clock signal that is synchronized to the rising edge of a reference input signal. In the absence of the reference input signal the programmable digital phase lock loop free runs creating an output bit clock signal at a programmed frequency. Various parameters of the output bit clock signal are programmable including its period, its offset from the reference input signal and its pulse width. There is provided an adjustment in the bit clock signal in the event that the required period thereof is not an integral multiple of the base clock signal of the programmable digital phase lock loop. The adjustment occurs only in the absence of the input reference signal. When the input reference signal is present its rising edge resynchronizes the output bit clock signal to the required frequency.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase-Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A method and device to synchronize sampled digital data transferred from an input section to an output section prevents data overrun or underrun due to timing differences of timing signals of the input and output section. The timing synchronization device has an input sampled data counter to determine a number of samples in a frame time of the input sampled data. The timing synchronization device further has an interpolator to estimate data sample values for each sample of the input sampled data to coincide with each sample of the output sampled data if the number of samples in said input sampled data is less than an expected number of samples in said output sampled data.

Abstract: An output driver includes an adjustable main output stage and a control circuit with a digital delay locked loop (digital DLL) circuit and an adjustable scaled output stage. The main output stage and the scaled output stage are both configured to adjust their strengths in response to a control signal generated by the control circuit. The control circuit receives a clock signal and propagates a transition through the scaled output stage. The DLL circuit compares the propagation time through the scaled output stage with a reference signal (that is dependent on the clock signal frequency) and generates the control signal as a function of comparison. The main output stage, receiving the same control signal, adjusts its strength in a corresponding manner.

Abstract: A method for determining a digital phase in a signal comprises sampling a reference signal for a low going edge. If the low going edge is not detected the reference signal is sampled again. If low going edge is detected (78) a counter is initialized (70). The reference signal is again sampled if a high going edge is not detected the reference signal is resampled until the high going edge is detected (79). When a high going edge is detected (79) a counter is started (73). A resulting signal is then sampled if the level of the resulting signal is high the resulting signal is sampled until a low going edge is detected (78). If a low going edge is not detected sampling of the resulting signal continues. If a low going edge is detected (78) sampling is continued until a high going edge is detected (79) at which point the counter is stopped (76). The counter updates a register (96).

Abstract: A phase-locked loop circuit includes with an oscillator which outputs a pulse signal, and a frequency divider for frequency-dividing the pulse signal. The frequency divider includes with a dividing factor switching circuit which switches the dividing factor before a phase of the pulse signal is locked to that of a reference clock signal.

Abstract: Intermittent miscounts generated by counters used in a phase-locked loop (“PLL”) are precisely measured by detecting changes to a predetermined waveform, such as a sawtooth waveform. The miscounts are detected using an open loop, not closed loop, set-up which comprises two separate signal generators feeding two separate frequencies into MAIN and REF counters of a PLL. Offsetting the frequencies slightly and integrating an output generates the predetermined waveform. Thereafter, miscounts can be detected by comparing waveforms corresponding to miscounts to theoretically predicted, predetermined waveforms.

Abstract: A clock pulse degradation detector monitors the leading and trailing edges of the monitored clock pulse train, and determines the number of leading and trailing edges of the supervised clock pulse train occurring within a single reference pulse. An external oscillator provides an external signal to a reset generator that develops reference pulses having a period less than that of a full cycle of the supervised clock pulse train, but longer than either a single pulse or land of the monitored clock pulse train. Based upon the number of leading and trailing edges detected in the supervised pulse train, a determination is made as to whether the supervised clock train is regular or irregular. Preferably, a pair of two-bit shift registers are utilized to accumulate the number of leading and trailing edges of the supervised clock pulse train. Logic is utilized to determine whether the number of leading and trailing edges stored within these two-bit shift registers indicate a regular or irregular clock pulse train.

Abstract: The lock detector circuit for a phase-locked loop has two counters and a comparator, to which the counter readings of the two counters are fed. The lock detector circuit is symmetric and has two comparators in which the counter readings of the counters are checked separately in each case. If the difference between the counter readings exceeds a predetermined threshold value in one of the comparators, then the phase-locked loop is immediately set to the non-locked state and the counter readings are reset to zero. Frequency differences are detected immediately in the novel lock detector circuit, without a time delay and independently of the relative position of the reference edges of the signals to be compared. The phase-locked loop is thus quickly and reliably set to a locked or non-locked state. Furthermore, the functioning of the lock detector circuit is preserved when one of the two clock signals fails to appear, for example in the event of a crystal fault.

Abstract: In a synchronous circuit constructed with a sequence circuit, for reproduce a clock signal synchronized with a synchronizing signal of such as television signal, an influence of variation of a d.c. component superposed on an edge of the synchronizing signal is reduced by obtaining phase errors at a falling edge and a rising edge of the synchronizing signal, arithmetically operating the phase errors and feeding back a result of the operation of the phase errors to a PLL. An influence of pseudo synchronizing signal is restricted by updating a phase error signal or holding a previous value according to the result of count of operation clocks during the synchronizing signal period.

Abstract: A digital PLL circuit is formed by a first digital PLL circuit, a signal generation circuit that generates a plurality of signals that have the same frequency as the output of the first PLL circuit but differing phases, and the second digital PLL circuit having a signal selecting circuit that can select the signals from the signal generation circuit, a frequency divider circuit that divides the output signal of the signal selecting circuit, a phase comparator circuit that compares the phase between the a signal used as a reference and the output signal from the frequency divider circuit, an up/down counter that detects the phase difference of the phase comparison circuit, and a digital filter that is provided between the up/down counter and the signal selecting circuit, the second PLL circuit selecting the signals from the signal generation circuit based on the output from the up/down counter.

Abstract: In a method of synchronizing a local oscillator to a main oscillator signal in a network, the local oscillator signal has a phase shift relative to and upon appearance of the main oscillator signal. The phase shift is used as a reference phase shift between the local oscillator signal and the main oscillator signal to synchronize the local oscillator signal. Initially the reference phase shift is fixed.

Abstract: An improved integrated circuit including decryption functions employs a method for determining if its environment has been modified, by providing a first VCXO as part of the integrated circuit, providing a second VCXO, adjusting one of the VCXOs in a first preselected manner, determining a first frequency count of the adjusted VCXO during a first preselected time interval using the other VCXO, adjusting the one of the VCXOs in a second preselected manner, determining a second frequency count of the adjusted VCXO during the first preselected time interval using the other VCXO, averaging the first and second frequency count to provide an average frequency count, adjusting the average frequency count in a predetermined manner, and comparing the adjusted average frequency count to a previously stored, determined, or provided average frequency count to determine if the environment of the integrated circuit has been modified.

Abstract: A phase locked loop makes a system clock signal synchronous to a horizontal synchronizing signal for a display unit, and a lock-in detecting circuit monitors said phase locked loop to see whether or not a phase difference takes place between the system clock signal and the horizontal synchronizing signal, wherein the lock-in detecting circuit measures the unlocked state between the system clock signal and the horizontal synchronizing signal in a window defined in a vertical synchronizing period and, thereafter, compares the time period of the unlocked state with a critical value to see whether or not the unlocked state is due to a temporary phenomenon or a phase difference to be corrected so that an detecting signal of the lock-in detecting circuit is reliable.

Abstract: A method for synchronizing multiple subsystems using one voltage-controlled oscillator. The method includes transmitting a phase and frequency aligned output of a voltage-controlled oscillator to each subsystem within a digital system. A first subsystem of the multiple subsystems generates a first internal clock and outputs a synchronization signal to each of the other subsystems. The synchronization signal has a marker that defines a known point in time of the first internal clock. The other subsystems sample the synchronization signal using the output signal of the voltage controller oscillator to determine a starting indicator that indicates the known point in time of the first internal clock. Upon detection of the marker in the synchronization signal, the other subsystems starts a second internal clock that is synchronized with the first internal clock.

Abstract: A frequency divider circuit, and a digital PLL circuit including the same, which can suppress jitter occurring in an output signal, including a first circuit module which drives D-FFs connected in series using an input signal as a reference clock signal and divides the input signal by a frequency division ratio selected by a frequency division ratio determining signal to produce a first divided signal; a second circuit module which drives D-FFs connected in series using the first divided signal as a reference clock signal and divides the first divided signal by a frequency division ratio corresponding to the number of D-FFs connected in series to produce an output signal; and an OR circuit which produces a frequency division ratio determining signal based on the outputs of the D-FFs of the second circuit module and a frequency division ratio selecting signal.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A wireless communication system (10) uses a phase detector (28) having a first pair of flip-flops (50, 56) for detecting the phase difference between an input frequency and a reference frequency. The first pair of flip-flops control current sources (66, 70) in the charge pump of the phase detector to modulate the error signal. A second pair of flip-flops (52, 58) detect when the input frequency is more than 2.pi. ahead of or behind the reference frequency. The second pair of flip-flops increment and decrement a counter (54) which in turn controls additional current sources (78-88) in the charge pump. The additional current sources extend the linear operating range of the error signal when the phase error exceeds .+-.2.pi..

Abstract: A method and an apparatus for control a timing in a flat panel display system are disclosed. In an alternating current plasma display system for respectively driving a plurality of subfields at every field in three steps such as a) entering and for eliminating a whole pixel for a first predetermined time, b) entering data for a second predetermined time and c) maintaining a discharge at every subfield for times which are different from one another, a first clock generator generates a first clock signal having a high frequency. A second clock generator generates a second clock signal having a low frequency. A first counter counts the second clock signal in response to a vertical synchronizing signal, and generates both a first pulse signal which sets the first and second predetermined times respectively in steps a) and b) in the respective subfield sections and a second pulse signal which sets times in step c) in the respective subfield sections which are different from one another.

Abstract: A no-hit switching apparatus includes a phase comparing circuit, a first selecting circuit, a second selecting circuit, a memory circuit, a read address counter, and a switching circuit. The phase comparing circuit compares the phases of two received signals. The first selecting circuit selects a signal with a smaller phase delay from the two received signals on the basis of the comparison result in the phase comparing circuit. The second selecting circuit selects a signal with a larger phase delay from the two received signals on the basis of the comparison in the phase comparing circuit. The memory circuit stores the signal selected by the first selecting circuit. The read address counter reads out the signal stored in the memory circuit with the phase of the signal with the larger phase delay. The switching circuit switches between the signal read out by the read address counter and the signal selected by the second selecting circuit.

Abstract: A phase-locked loop circuit is constituted in such a manner that a delayed signal created by causing an input signal to loop through a delay stage a plurality of times is compared in terms of phase with the input signal, and an amount of delay in the delay stage is controlled in accordance with the comparison result of the delayed signal and the input signal. Therefore, the circuit size can be reduced with a reduced number of delay units constituting the delay stage.

Abstract: A method and apparatus for generating multiple frequency clock signals using a single input clock signal are provided. Each clock signal generated has a cycle time that is an integer multiple of the input clock cycle time. The fastest clock signal, i.e., the clock signal with the highest frequency generated has the same cycle time as the input clock. The rising edges of all the clock signals generated are synchronized and each clock signal generated has an approximate duty cycle of 50%. This is achieved by first applying the input clock signal to an input terminal of a plurality of registers and of a frequency control module of the signal generator, presenting control signals to input terminals of the registers and of the frequency control module, and generating a plurality of output clock signals in the frequency control module, dependent on the input clock signal and on the control signals.

Abstract: According to the present invention, a mobile communications terminal includes a high accuracy clock for providing a timebase in a normal operating mode, a "slow clock" for providing the timebase in a low power mode of operation, and at least one processor coupled to the high accuracy clock and the "slow clock" for controlling the modes of operation. In a preferred embodiment, the mobile communications terminal includes a conversion signal processor (CSP), a digital signal processor (DSP), a communications protocol processor, and a radio frequency (RF) segment. The CSP, which includes a plurality of registers, interfaces with the DSP to execute the timing control functions for the terminal. In the normal operating mode, the timebase is maintained from the high accuracy clock. During inactive periods of terminal operation (e.g.

Abstract: An output timer includes a capture register for capturing a count value held by a free running up-counter in coorporation with a transmission gate in response to an event signal applied to the output timer. An adder adds a first value stored in another register to the count value captured by the capture register and produces a sum. A comparator compares a count value held by the free running up-counter with the sum and outputs a coincidence signal when the count value and sum are equal to each other. A set-reset flip-flop includes a set terminal for receiving the event signal and a reset terminal connected to the output terminal of the comparator.

Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock.

Abstract: A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.

Abstract: A method and phase locked loop for generating an eight-to-fourteen (EFM) data restoring clock signal. A frequency detector detects the number of clock pulses input during a pulse width of the EFM data signal, compares the detected number with predetermined maximum and minimum values, and outputs a signal indicative of the resulting comparison value. A voltage controlled oscillator varies an oscillating frequency in response to a DC control signal and outputs the clock pulses corresponding to the oscillating frequency. A programmable counter frequency-divides the clock pulses generated by the voltage controlled oscillator in response to a predetermined speed multiple and outputs the frequency-divided clock pulses. A phase detector detects a phase difference between the EFM data signal and the clock pulses generated by the programmable counter and outputs a signal indicative of the phase difference. A mixer mixes the output of the phase detector with the output of the frequency detector.

Abstract: A D flip-flop latches a reference clock signal in response to an output signal fed back from an output circuit. A pulse generating circuit generates a pulse in response to the output signal fedback from the output circuit. From the latched signal and the pulse generated by the pulse generating circuit, a count pulse is generated. The count pulse is output to an up/down counter. Based on the counting result of the up/down counter, a digital-to-analog conversion circuit generates a delay control signal. Using this delay control signal, the delay circuit synchronizes its output signal with the reference clock signal. It is possible to synchronize the output data signal with the reference clock signal regardless of variations in the reference clock signal, source voltage, and ambient temperature.

Abstract: The invention provides a PLL circuit which can form a phase difference between input and output signals with a high degree of accuracy without employing a current source for a very weak current and eliminates dependency of the phase difference upon the input signal frequency. In the PLL circuit, phase difference forming current is added within a term of a fixed period to a selected one of charge-up current and charge-down current, selected by a phase comparison circuit, of a charge pump circuit, which charges up or charges down a loop filter under the control of an output signal of a phase comparison circuit, to form a phase difference between input and output signals of the PLL circuit which are to be compared in phase by the phase comparison circuit. The magnitude of the phase difference depends upon and is controlled by a term within which the phase difference forming current.

Abstract: A phase detector provides a digital output having a linear relationship to the phase difference between a reference signal and an applied input signal. The phase detector counts the number of cycles of the reference signal within a time interval determined by the difference in arrival times of corresponding amplitude transitions of the reference signal and the input signal. A digital output representing the number of counted cycles is produced. A dither generator adds random time variation to the time interval over which the reference signal cycles are counted to introduce a corresponding random variation in the digital output.

Abstract: An exchange system comprising a plurality of redundant clock supply modules for receiving respective clock signals to maintain synchronization. Each redundant clock supply module includes a phase locked loop coupled to receive a network synchronizing reference signal, for generating a most significant clock of the exchange system synchronized to the network synchronizing reference signal; a clock generator for counting the most significant clock to generate a plurality of system clocks including a least significant clock and a first frame pulse; and a redundancy synchronizer for synchronizing the first frame pulse and a second frame pulse from a counterpart redundancy module to generate a redundancy synchronization signal for establishing synchronization between redundancy modules from the most significant clock to the least significant clock.

Abstract: Improved PLL frequency synthesizer circuits, including a novel swallow counter, may be operated at high speeds without experiencing internal delays or malfunctions. The swallow counter supplies a modulus signal to a prescaler which is capable of selectively changing a frequency-dividing ratio of a frequency signal. The swallow counter includes a shift register, a counter, a count-up detector, a modulus signal generator, and a control circuit. The swallow counter is connected to the prescaler and the program counter, and is capable of counting a frequency-divided signal based on a set value data and producing the modulus signal in response to a load signal after counting is completed. The swallow counter supplies the modulus signal to the prescaler and determines whether the set value data is data prepared to fix the frequency-dividing ratio.

Abstract: A system is provided for generating an accurate and stable output clock signal of a desired output frequency in response to a system clock signal having a system clock period. The system uses an accurate and stable reference clock signal. The system comprises a measuring circuit and a ratio counter. The measuring circuit receives and processes the system clock signal and produces a measurement, referred to as the system clock measurement, that is indicative of the system clock period. The ratio counter receives the system clock signal and the system clock measurement and generates the output clock signal. The system is resistant to noise in the output clock signal caused by asynchronicity between the system clock signal and the reference clock signal. The system is resistant because it employs at least one of a lock-on unit and a synchronizing controller in operating the clock measuring circuit.

Abstract: A digital audio frame and block synchronization signal is generated from a reference clock having a nominal 50% duty cycle except that one out of every N cycles has a different duty cycle, where N corresponds to a block span of ancillary data within the frame samples of the digital audio. A phase locked loop includes a loop counter that provides a sample clock synchronized with the reference clock. A block counter subdivides the sample clock by N to produce a block clock. A logic circuit has the reference clock and a current count from the loop counter as inputs, and detects when the Nth non-50% duty cycle occurs to generate a reset signal. The reset signal is used to reset the block counter so that the block clock is synchronized with the reference clock.

Abstract: A clock circuit for providing an integrated circuit with a high accuracy, crystal oscillator clock which interfaces to an "off-chip" crystal to provide a high accuracy clock signal while an internal, low power oscillator provides a low power clock source. Either clock may be selected to drive a programmable processor under program control. When high accuracy and stability are required, the crystal oscillator may be chosen as the processor clock, and when lower power is desired, the low power oscillator may be chosen as the processor clock while the high accuracy clock is disabled. The high accuracy oscillator is used to clock a first timer circuit, while the low power oscillator is used to clock a second timer circuit. The second timer circuit output, in turn, is synchronized to the processor clock so that the programmable processor can utilize the second timer circuit even when the processor clock is asynchronous to the second timer circuit.

Abstract: A deviation of a clock rate of the timepiece clock signal is determined relative to a reference clock rate of a reference clock signal (CR) which is either issued while the mobile unit is switched on or is contained in a received signal. The reference clock rate is higher than the clock rate of the timepiece clock signal. A count number (N) is calculated based on the deviation of the clock rate of the timepiece clock signal. The clock signal is generated such that the clock pulses the clock signal are successively issued each time the clock pulses of the timepiece clock signal counted up to the count number.

Abstract: A frequency departure detecting circuit permits flexibly modify a detecting condition of frequency departure. A working reference clock is counted for a given period. On the basis of uniformity between bits of given number of upper bits of the counted value, large magnitude of frequency departure of repeated frequency of the reference clock from a frequency that should be is judged. Also, through comparison of given number of lower bits of the counted value and externally set detecting value, departure of the repeated frequency of the reference clock from the frequency that should be, is judged. When the counted value reaches a predetermined value, free running condition of the counter is judged to stop counting operation. When judgement is made that the repeated frequency of the reference clock is departed from the frequency that should be, the working reference clock is replaced with a back-up reference clock in response to an alarm.

Abstract: A data transfer synchronizing unit is provided for generating flags indicating the fullness state of a data transfer element. The determining unit includes the first and second counters operating according to first and second clock signals, first and second registers, serially connected to the output of the second counter, a latch unit and a comparator. The first register is clocked by the second clock signal and the second register is clocked by the first clock signal. The latch unit alternately activates the first and second registers to receive data in accordance with the second and first clock signals, respectively. The comparator produces the flags by comparing the output of the first counter with the output of the second register.

Abstract: An oscillating circuit 30 outputs a signal .o slashed..sub.o whose pulse cycle T is a linear function T=kS+m of a control input value S. A frequency control circuit 10, every time a counter 11 counts a number Nr of pulses of a reference signal .o slashed..sub.r, calculates S=No-m/k, where No is a count of .o slashed..sub.o counted by the counter 12, makes a judgement on convergence of .o slashed..sub.o based upon the difference between input and output values of a register 14, makes the register 14 hold S, updates Nr=S+m/k and clears the counter 12 to 0. A digital phase control circuit 20 judges a advance/delay of the phase of .o slashed..sub.o relative to .o slashed..sub.

Abstract: The present invention provides a delay clock generator where a plurality of stable delay clocks can be generated and digitizing is easy. The delay clock generator comprises first to nth (n: integer not less than 2) delay circuits (11 to 1n) connected in cascade connection for delaying the basic clock (KO) in sequence, a phase comparator (21) for comparing phase of a delay clock from the nth delay circuit (1n) with that of the basic clock, and a delay control circuit (31) for generating a delay control value to make the phase of the delay clock from the nth delay circuit synchronize with that of the basic clock based on a phase comparison result, and for controlling delay amounts of the first to nth delay circuits respectively by the delay control value.