Abstract: A digital phase detector 100 receives a limited input signal 108 and inputs it and a reference oscillation 112 into an EXCLUSIVE NOR gate 102. The output 110 of the EXCLUSIVE NOR gate 102 is input to a gated N-bit counter 104, which produces an N-bit representation of the magnitude of the phase 115 of the signal 108. A sign detector 105 determines the sign of the phase of the signal by sampling the resultant 110 and combines the magnitude of the phase 115 with the sign of the phase to produce a digital numeric representation of the phase of the signal 116.

Abstract: An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a later point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: A frequency synthesizer including a phase-locked loop, an oscillator of which supplies n phases with increasing delays of a fast clock signal synchronized on a reference frequency, each of said n phases being sent onto a same number m of fractional dividers having their respective outputs sent onto m jitter compensators which each issue, based on said n phases, a clock signal synchronized on said reference frequency.

Abstract: A phase control circuit adjusts the width of a PLL clock signal so that a PLL clock signal generated from a master clock signal MCK is in synchronization with an EFM signal. A velocity detector detects offset in velocity by counting a pulse width of an EFM signal with a master clock signal MCK. The phase control circuit alters the pulse width of a PLL clock signal according to the detected offset in velocity to alter the average frequency of a PLL clock signal in proportion to offset of the rotational speed.

Abstract: A digital phase-locked loop adjusts the phase of a Recovered Clock in the receiver under the condition of asynchronous serial data transmission so that the phases of the transmission data are locked in order to reduce errors in read data. The digital phase-locked loop includes a zero-phase start circuit, a phase-error detecting circuit, an error-filtering circuit, a Recovered Clock adjusting circuit and a clock-generation circuit. This phase-locked loop generates a set of clocks through the detection of the transmission data level in the zero-phase start circuit so as to lock the phase of the transmission data quickly, and the phase-error detecting circuit detects the phase error between the phase of the transmission data and the phase of the Recovered Clock, after which the phase error signal is filtered through the adaptive filtering circuit for conversion into error-adjusting signals.

Abstract: A circuit for generating a low power CPU clock signal is disclosed. The circuit includes a multi-frequency oscillator having a plurality of output signals of various frequencies that are input to a signal selector. The signal selector is controlled to route one of the various frequency signals to the output, which provides the CPU clock oscillating signal. The frequency of the CPU clock signal is compared against a reference oscillatory signal that is generated by a reference oscillator. Based upon the comparison, the frequency comparator generates an output signal that is used to control the signal selector to select an input signal of either higher or lower frequency, depending upon the comparison. Finally, an enable signal is provided for selectively enabling the operation of the CPU clock oscillating circuit.

Abstract: An automatic adjustment circuit for an oscillator converts an output from a register into an analog signal by means of a D/A converter. An oscillation frequency of an oscillator is controlled by an output of the D/A converter. A first counter for counting an oscillation signal of the oscillator 1 resets itself and generates a pulse when a count reaches a predetermined value. A second counter counts a reference frequency pulse having a frequency substantially higher than the oscillation frequency of the oscillator. The second counter, on completion of counting a given preset value, changes an output level. The second counter is preset by said first counter when the first counter resets itself. Outputs from the first and the second counters are processed by an AND operation in an AND circuit. A third counter counts an output from the AND circuit, and provides a count output to the register.

Abstract: A synchronizing circuit has a first signal generating unit for dividing a control signal to obtain a first signal having a first frequency, a second signal generating unit for dividing the control signal to obtain a second signal having a second frequency, a third signal generating unit for dividing the control signal to obtain a third signal having a third frequency and synchronized with the second signal, and a synchronizing signal generating unit for generating a synchronizing signal which is adapted to synchronize the first signal with the second and third signals in accordance with a logical operation on the first, second and third signals. With this arrangement, the internal clock signals can be synchronized without using a reset signal. Consequently, neither wiring for supplying the reset signal nor a circuit for generating the reset signal are necessary.

Abstract: A bypass means is provided for bypassing a system clock disabling signal around a conventional system clock disabling signal processing path to reduce the amount of delay between the occurrence of the disabling signal and a stopping of the system clock.

Abstract: A method and apparatus for implementing a zero latency synchronizer that permits the reliable transfer of data between clock domains by placing a metastability delay in the clock path. The zero latency synchronizer for synchronizing a signal from a first clock domain to a second clock domain is formed from a clock regenerator circuit and input and output master slave flip flops. The clock regenerator receives a first clock from the first clock domain and a second clock from the second clock domain and generates first and second regenerated clock signals. The first and second regenerated clock signals are formed in a manner that guarantees that the first and second regenerated clocks, in conjunction with the first and second clocks, can be used to control the input and output master slave flip flops and thereby pass data reliably from one clock domain to the other without delay.

Abstract: There is disclosed a horizontal synchronizing signal generating circuit for generating a horizontal synchronizing signal which has no frequency variations and which is in phase with an entered composite synchronizing signal if the entered composite synchronizing signal is a nonstandard signal having a varying horizontal frequency. A horizontal counter circuit (5) counts a reference clock (V.sub.CL), and a window pulse generating circuit (4) outputs a window pulse signal (V.sub.W) which is low for a fixed time period when a counter output (V.sub.CT) equals a counter value (878) indicative of a standard output timing. A horizontal synchronizing signal separating circuit (1) outputs a horizontal synchronizing signal (V.sub.2) only when the composite synchronizing signal (V.sub.1) falls within the fixed time period. Then a horizontal phase judging circuit (2) outputs a standard signal flag (V.sub.3) and a synchronizing signal generating circuit (3) outputs the horizontal synchronizing signal (V.sub.

Abstract: A phase-locked oscillator circuit with a broad pull-in frequency range generates a stable output signal synchronized to the phase of an input signal. An input-stage phase-locking circuit wherein the phase of a first frequency-converted output signal from a 1st frequency-conversion section is compared by a 1st phase-comparison circuit with the phase of the input signal and the phase of the 1st frequency-converted output signal is controlled. A processing section determines the frequency component of the input signal based on the phase-comparison output signal from the 1st phase-comparison circuit. An output-stage phase-locking circuit compares the phase of a 2nd frequency-conversion section with the phase of the input signal in a 2nd phase-comparison circuit. The phase of the 2nd frequency-conversion section is controlled based on the resulting phase-comparison output signal and the phase comparison output signal from the 1st phase-comparison circuit.

Abstract: A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a late point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Abstract: A data processing system having a first circuit and a second circuit that together control a third circuit by a respective first control signal and a second control signal. The first circuit issues a request signal to the second circuit to trigger initiation of the operation of the third circuit and the second circuit returns a grant signal to the first circuit to indicate that operation of the third circuit has completed. An advance controller within the second circuit serves to start to synchronize the grant signal back to the clock signal of the first circuit at one of a plurality of possible times that is selected to match the relative frequencies of the clock signals driving the first circuit and the second circuit.

Abstract: An input clock delay circuit includes an up counter for estimating the approximate number of internal clock cycles that occur during one cycle of the input clock signal and another up counter for determining the portion of each cycle of the input clock signal that is high. A clock manipulation circuit receives each counter's value, and may be set to perform a fixed transform on the input clock signal, such as clock delay/advance, duty cycle shifting, and frequency multiplication/division. The clock manipulation circuit output values are loaded into two down counters that are also clocked by the internal clock. On the rising edge of the input clock signal, the first down counter starts decrementing until the counter reaches zero, indicating that the desired delay interval has passed, at which point the delayed output clock signal is taken high. The second down counter then starts decrementing for an interval that is equal to the desired duty cycle of the output clock signal.

Abstract: A method and a device for regenerating clock rate information in which data is intermediately stored in a memory to which the data is read at a first rate and out of which the data is read at a second rate. The difference between two levels of the amount of data stored in the memory is determined, after which the difference is compared with a reference value. The result from the comparison affects the second rate so that, at subsequent measurements of the difference, the difference between it and the reference value shall decrease.

Abstract: A time measurement system for measuring time accurately with an inaccurate clock, in which two clock oscillators are compared and the momentary error of the slower clock oscillator is measured. When the error change rate of the slower clock oscillator is slow enough the fast clock oscillator can be switched off for longer time intervals. With the help of this apparatus and method of operation power can be saved in portable equipment which requires accurate time measurement.