With Variable Delay Means Patents (Class 327/158)
  • Patent number: 11327553
    Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: May 10, 2022
    Assignee: NVIDIA CORPORATION
    Inventors: Siddharth Saxena, Tezaswi Raja, Fei Li, Wen Yueh
  • Patent number: 11327922
    Abstract: The systems and methods for bus ownership in a system power management interface (SPMI) bus may include two or more masters on the SPMI bus, and bus ownership may be passed between masters. The current owner of the bus is responsible for providing a clock signal on the clock line of the SPMI bus. To avoid problems caused by ringing of the clock signal being sent on a conductor that exceeds the SPMI specification, the original master (from whom bus ownership is being transferred) holds the clock line of the SPMI bus at a logical low for a clock delay value that is based on conductor length.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 10, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Sharon Graif, Sai Ganapathy Srinivasan, Navdeep Mer, Sriharsha Chakka
  • Patent number: 11323131
    Abstract: A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Gagan Midha, Kallol Chatterjee
  • Patent number: 11296684
    Abstract: A phase interpolating (PI) system includes: a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal, the PI stage being further configured to avoid a pull-up/pull-down (PUPD) short-circuit situation by using the multi-bit weighting signal and a logical inverse thereof (multi-bit weighting_bar signal); and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component; the capacitive component being tunable; and the capacitive component having a Miller effect configuration resulting in a reduced footprint of the amplifying stage.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Che Lu, Chin-Ming Fu, Chih-Hsien Chang
  • Patent number: 11277143
    Abstract: A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Somnath Kundu, Abhishek Agrawal, Brent Carlton
  • Patent number: 11264994
    Abstract: A delay circuit includes a coarse delay circuit, a header circuit, and a phase mixing circuit. The coarse delay circuit is configured to delay a reference clock signal to generate a first clock signal and a second clock signal and to change each phase of the first clock signal and the second clock signal by double a unit phase. The header circuit is configured to receive the first clock signal and the second clock signal and to generate a first phase clock signal and a second phase clock signal, between which a phase difference corresponds to half of the unit phase. The phase mixing circuit is configured to mix phases of the first phase clock signal and the second phase clock signal to generate an output clock signal.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Young Ouk Kim
  • Patent number: 11239847
    Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das
  • Patent number: 11233500
    Abstract: A clock distribution network includes a global driver configured to receive a pair of clock signals to generate a pair of global clock signals, a clock transmission driver configured to amplify the pair of global clock signals to generate a pair of transmission clock signals, a first boosting circuit configured to boost voltage levels of the pair of transmission clock signals to generate a pair of first boosted clock signals, a first local driver configured to shift voltage levels of the pair of first boosted clock signals to generate a pair of first local clock signals, a second boosting circuit configured to boost voltage levels of the pair of first boosted clock signals to generate a pair of second boosted clock signals, and a second local driver configured to shift voltage levels of the pair of second boosted clock signals to generate a pair of second local clock signals.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: January 25, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Hyo Kang
  • Patent number: 11233480
    Abstract: A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 25, 2022
    Assignee: Stichting IMEC Nederland
    Inventor: Johan van den Heuvel
  • Patent number: 11206026
    Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Yun Tack Han, Kyeong Min Kim
  • Patent number: 11196425
    Abstract: An eye width monitor (EWM) for a clock and data recovery (CDR) circuit includes a delay circuit, a first multiplexer (MUX) and a calibration circuit. The delay circuit includes an input terminal and an output terminal. The first MUX, coupled to the delay circuit, includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first MUX is coupled to a clock input terminal of the EWM. The second input terminal of the first MUX is coupled to the output terminal of the delay circuit. The output terminal of the first MUX is coupled to the input terminal of the delay circuit. The calibration circuit, coupled to the delay circuit, is configured to receive an oscillation clock from the delay circuit and receive a reference clock, and calibrate the oscillation clock with the reference clock.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: December 7, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Che-Yi Lin, Yung-Cheng Lin
  • Patent number: 11189333
    Abstract: A memory device includes a delay locked loop (DLL), a clock compensating circuit, and a data input/output (I/O) circuit. The DLL outputs a first clock signal and a second clock signal. The clock compensating circuit adjusts a voltage level of an output node and generates an inner clock signal based on the voltage level of the output node. The data I/O circuit outputs data to an outside based on the inner clock signal. The clock compensating circuit includes first and second pulse adjusting circuits. The first pulse adjusting circuit connected to a first output node and outputs a first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit connected to a second output node and outputs a second adjusting current based on the second clock signal and a voltage level of the second output node.
    Type: Grant
    Filed: July 26, 2020
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang-Woo Ryu, Soojung Rho
  • Patent number: 11183990
    Abstract: A clock synchronization signal generator generates a dead time in which gates of both of two switching elements included in a switching circuit are in an off state, and generates the dead time for controlling a plurality of pulses having different widths to pulses having a constant width, which is output by the switching circuit.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 23, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tsuyoshi Nakahira, Akihiro Nishigaki
  • Patent number: 11177810
    Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 16, 2021
    Inventors: Feng Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Patent number: 11177814
    Abstract: A delay locked loop circuit including: a clock signal input buffer to buffer an input clock signal and generate a reference clock signal; a delay unit to delay the reference clock signal in response to a coarse and fine delay code and generate an internal clock signal; a clock signal delay replica unit to delay the internal clock signal and generate a feedback clock signal; a coarse delay control unit to receive the reference and feedback clock signals, detect a time period between a transition time point of the reference clock signal and a transition time point of the feedback clock signal occurring before the transition time point of the reference clock signal, and generate a coarse delay code; and a fine delay control unit to compare a phase of the reference clock signal and a phase of the feedback clock signal, and generate a fine delay code.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwapyong Kim, Hundae Choi
  • Patent number: 11132015
    Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenji Asaki, Shuichi Tsukada
  • Patent number: 11120855
    Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tsuneo Abe
  • Patent number: 11115014
    Abstract: A duty cycle correction circuit includes: a first inverter, a first delayer, and a first adjustment circuit. An input terminal and output terminal of the first inverter are respectively configured to receive a first signal and output a third signal. A first input terminal and an output terminal of the first adjustment circuit are respectively configured to receive the third signal and output a first correction signal. An input terminal and output terminal of the first delayer are respectively configured to input a second signal and output a fourth signal to the first adjustment circuit. The fourth signal has a first delay time relative to the second signal. When the third signal and the fourth signal are at a high level, so is the first correction signal. When the third signal and the fourth signal are at a low level, so is the first correction signal.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: September 7, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Boxin Yang
  • Patent number: 11088684
    Abstract: An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Thomas Makowski, Matthias Ringe
  • Patent number: 11079964
    Abstract: A memory system may include a semiconductor memory and a memory controller. The memory controller may include an adjustment circuit configured to receive a first signal having a first duty cycle, and intermittently output a second signal to an outside of the memory controller on the basis of a control signal, the second signal having a second duty cycle which is different from the first duty cycle. The memory controller may further include a selector circuit configured to receive the second signal, receive a third signal which is generated on the basis of the second signal, and output a selected one of the second signal and the third signal. The memory controller may further include a control circuit configured to generate the control signal on the basis of the selected one of the second signal and the third signal output from the selector circuit.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: August 3, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jianan Wang, Kouichi Tashiro, Kenji Kikuchi
  • Patent number: 11082037
    Abstract: A duty cycle correction circuit includes: a first inverter, a first delayer, and a first adjustment circuit. An input terminal and output terminal of the first inverter are respectively configured to receive a first signal and output a third signal. A first input terminal and an output terminal of the first adjustment circuit are respectively configured to receive the third signal and output a first correction signal. An input terminal and output terminal of the first delayer are respectively configured to input a second signal and output a fourth signal to the first adjustment circuit. The fourth signal has a first delay time relative to the second signal. When the third signal and the fourth signal are at a high level, so is the first correction signal. When the third signal and the fourth signal are at a low level, so is the first correction signal.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 3, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Boxin Yang
  • Patent number: 11082034
    Abstract: A method for cycle accurate deskewing a second clock signal with respect to a first clock signal is provided. The first clock signal has been propagated from a first clock source through a first clock tree. The second clock signal has been propagated from the first clock source through a second clock tree. The second clock tree comprises a programmable delay line for inducing a delay. The method comprises determining a first clock tree latency of the first clock tree, determining a second clock tree latency of the second clock tree, setting a cycle time of the first clock source to a measuring cycle time depending on the first clock tree latency and/or the second clock tree latency, adjusting a skew between the second clock signal and the first clock signal, setting the cycle time of the first clock source to an operating cycle time.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Andreas H. A. Arp, Douglas J. Malone, Thomas Makowski, Michael V. Koch
  • Patent number: 11082049
    Abstract: A semiconductor device includes a delay code generation circuit configured to adjust a shifting code for delaying a first internal clock, by comparing phases of a second internal clock and a delayed clock, the delayed clock generated by delaying the first internal clock, and configured to generate a first delay code and a second delay code from the shifting code.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventor: Jayoung Kim
  • Patent number: 11075782
    Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Timothy M. Hollis, Feng Lin
  • Patent number: 11070352
    Abstract: A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 20, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Nobuaki Kawasoe, Yoshiharu Yoshizawa, Manabu Yamazaki
  • Patent number: 11063597
    Abstract: Described is a delay-locked loop which includes a frontend circuit configured to output a control voltage based on an input clock and a feedback clock and a delay line circuit connected to the frontend circuit. The delay line circuit configured to generate a bias voltage based on the control voltage and a step size, where the bias voltage is variable based on the step size, and apply at least one level of delay on the input clock based on the bias voltage to generate an output clock, where the feedback clock being based on the output clock and where the input clock is aligned with the feedback clock by delaying the phase of the output clock until phase lock.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: July 13, 2021
    Assignee: SiFive, Inc.
    Inventors: Santosh Mahadeo Narawade, Jithin K, Mohit Gupta
  • Patent number: 11057040
    Abstract: A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehong Jung, Sangdon Jung, Kyungmin Lee, Byungki Han
  • Patent number: 11043942
    Abstract: A variable delay circuit includes first pull-up and first pull-down current paths and second pull-up and second pull-down current paths. The variable delay circuit generates first delays in an output signal relative to an input signal in response to the first pull-up and first pull-down current paths being enabled by a first control signal. The variable delay circuit generates second delays in the output signal relative to the input signal that are different than the first delays in response to the second pull-up and second pull-down current paths being enabled by a second control signal.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventor: Chee Seng Leong
  • Patent number: 11042181
    Abstract: A circuit comprises a burst clock control and gating device configured to generate a modified clock signal in a test mode by allowing a preset number of clock pulses of a clock signal to go through during each clock cycle of a reference clock signal, and a plurality of clock gating devices. Each of the plurality of clock gating devices comprises a multiplexing device, wherein the modified clock signal is coupled to a selector input of the multiplexing device, and input signal generation circuitry configured to ensure the timing of the transitions on the output are derived purely from the timing of the transitions of the clock and not by the timing of the transition of the first and second inputs of the multiplexer.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: June 22, 2021
    Assignee: Siemens Industry Software Inc.
    Inventor: Jean-Francois Cote
  • Patent number: 11041722
    Abstract: Systems and methods for sensing angular motion using a microelectromechanical system (MEMS) gyroscope are described. These systems and methods may be useful for sensing angular motion in the presence of low-frequency noise, which may be noise below 1 KHz. In a system for sensing angular motion, low-frequency noise may give rise to duty cycle jitter, which may affect the demodulation of the sense signal and cause errors in angular motion estimates. The systems and methods described herein address this problem by relying on double-edge phase detection technique that involves sensing when the rising and falling edges of the resonator signal deviate from their expected values in the idealized 50% duty cycle scenario. To prevent the formation of ripples in the double-edge phase detection that may otherwise affect the demodulation of the sense signal, a switch may be used. The switch may be maintained in a non-conductive state when a ripple is received.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 22, 2021
    Assignee: Analog Devices, Inc.
    Inventors: Jiefeng Yan, William A. Clark, Ronald A. Kapusta, Jr.
  • Patent number: 11038511
    Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 15, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Neil E. Weeks, Reuben P. Nelson
  • Patent number: 11022997
    Abstract: A signal processing device includes an oscillation circuit, a protection target circuit, a delay time detection circuit, and a clock control circuit. The oscillation circuit receives the frequency control signal and generates a clock signal having a frequency corresponding to the frequency control signal. According to the above-mentioned configuration, even when a delay failure due to aging occurs in the signal processing device, it is possible to prevent a malfunction.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: June 1, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Narihira Takemura, Terunori Kubo, Tetsuo Takahashi
  • Patent number: 11012055
    Abstract: A comparator system and a method for comparing an input signal and a reference signal are presented. The system has a controller to adjust a rising output delay and/or a falling output delay of a system output signal. The system output signal is dependent on the comparison between the input signal and the reference signal. This system provides a more efficient comparator with reduced power consumption whilst still providing the required rising output delay and falling output delay for a given application. Techniques used in prior art will always resort to running the comparators at a speed that supports the speed requirements in the worst case conditions and does not exploit any asymmetries in the required rising output delay and falling output delay for a given application. When these asymmetries are exploited, further increases in power efficiency can be achieved.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 18, 2021
    Assignee: Silego Technology Inc.
    Inventors: Vikas Vinayak, David Kuneth Chow, Nathan Willis John, Sidney Chan
  • Patent number: 11012060
    Abstract: Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh
  • Patent number: 11005464
    Abstract: The disclosure provides a delay line circuit including an output stage. The output stage includes a first inverter cell, a second inverter cell, a correction circuit, and a first switch capacitor array. The input terminal of the first inverter cell receives a reference clock signal. The input terminal of the second inverter cell is coupled with the output terminal of the first inverter cell. The first terminal of the correction circuit is coupled with the output terminal of the first inverter cell, and the second terminal of the correction circuit is coupled with a ground, wherein the correction circuit corrects a duty cycle of the delay line circuit. The first terminal of the first switch capacitor array is coupled with the output terminal of the second inverter cell, and the second terminal of the first switch capacitor array is coupled with the ground.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Tso Lin
  • Patent number: 10992306
    Abstract: A self-start-up control circuit adaptable to an oscillation circuit includes a state circuit that generates a reset signal according to a level of a control voltage for a voltage-controlled oscillator (VCO) of the oscillation circuit; and a start-up circuit that starts up the VCO by generating an enable signal according to the reset signal.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 27, 2021
    Assignee: Himax Technologies Limited
    Inventor: Chun Hung Wang
  • Patent number: 10965293
    Abstract: A delay-locked loop includes a phase detector configured to detect a phase difference between a first clock and a second clock, a charge pump configured to increase a charge amount at a capacitive load in accordance with a first charge amount and decrease the charge amount at the capacitive load in accordance with a second charge amount based on a phase difference provided by the phase detector, a sample and hold circuit configured to receive the charge amount from the capacitive load and hold the charge amount, and a voltage control delay line configured to select a delay amount based on the charge amount received from the sample and hold circuit. At least one parameter of the delay-locked loop is configured such that a desired pump current ratio of a delay cell is achieved by adjusting a delay amount of the delay cell and/or an amount of current coupled to the delay cell.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Tin Chang, Chih-Hsien Chang, Mao-Hsuan Chou, Ruey-Bin Sheen
  • Patent number: 10965280
    Abstract: A delay circuit, a clock control circuit and a control method are disclosed. The delay circuit includes N-stage delay units coupled in a chain, the delay unit of each stage comprises the four-state gate circuit and an inverter circuit, an input terminal of a four-state gate circuit and an input terminal of an inverter circuit of each stage are coupled together, another input terminal of the inverter circuit is coupled to an output terminal of the inverter circuit of the next stage; an input signal is coupled to the input terminal of the four-state gate circuit and the inverter circuit of the first stage, and is output with a certain delay of time by sequentially passing through the four-state gate circuit and the inverter circuit of each stage.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 30, 2021
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Bo Qu, Jinfu Chen, Lixin Jiang
  • Patent number: 10951216
    Abstract: A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: March 16, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: James D. Barnette, William Anker, Xue-Mei Gong
  • Patent number: 10931289
    Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh
  • Patent number: 10915474
    Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Dean Gans
  • Patent number: 10892032
    Abstract: System and method of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: January 12, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: David Da Wei Lin
  • Patent number: 10892744
    Abstract: The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael Koch, Matthias Ringe, Andreas Arp, Fatih Cilek
  • Patent number: 10872643
    Abstract: An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Uemura, Yasuhiro Takai
  • Patent number: 10872564
    Abstract: A data driver IC can include an analog-to-digital converter; a sensing part that, in a sensing mode for sensing the driving characteristics of pixels, samples a signal outputted from the pixels in response to a data voltage for sensing, and, in a calibration mode for sensing the output characteristics of the analog-to-digital converter, samples a calibration current and outputs the same to the analog-to-digital converter; and a current generator that generates N calibration currents by dividing an external input source current into N parts, where N is a natural number.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 22, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jisu Choi, Myunggi Lim, Taeyoung Lee
  • Patent number: 10862478
    Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Kyu Dong Hwang
  • Patent number: 10860052
    Abstract: A delay locked-loop includes, in part, a phase/frequency detector responsive to a reference clock signal, a charge pump responsive to the phase/frequency detector, a variable delay line responsive to an output of the charge pump to cause a delay in the reference clock signal thereby to generate an internal clock signal, and a controlled delay line that includes a multitude of fixed delay cells. The controlled delay line causes the internal clock signal to be delayed by a delay across one of the multitude of fixed delay cells in response to the output of the charge pump. The controlled delay line generates the output clock signal of the delay-locked loop. The delay locked-loop may further include an overflow detector configured to cause the selection of one of the multitude of fixed delays in response to the output of the charge pump.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: December 8, 2020
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Matan Gal, Seyed Ali Hajimiri
  • Patent number: 10848299
    Abstract: A phase interpolator includes a phase adjusting circuit. The phase adjusting circuit includes a first phase adjusting module and a second phase adjusting module, the first phase adjusting module outputs a first clock signal, and the second phase adjusting module outputs a second clock signal; the first phase adjustment module and the second phase adjustment module are connected in parallel to output an interpolation signal. Through the first phase adjustment module and the second phase adjustment module the first clock signal and the second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 24, 2020
    Assignee: AMLOGIC (SHANGHAI) CO., LTD.
    Inventor: Ming Shi
  • Patent number: 10841072
    Abstract: An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhiqiang Huang, Hiep Pham, Chih-Wei Yao
  • Patent number: 10795401
    Abstract: A semiconductor device includes a delay-locked clock generation circuit configured to generate a delay-locked clock which is driven by at least one internal clock selected from a plurality of internal clocks in response to a phase control signal. The semiconductor device also includes a latency command generation circuit configured to generate a latency command for generating transmission data from data by latching an internal command sequentially by the at least one internal clock in response to the phase control signal and shifting the sequentially latched internal command by a period set by a shifting control signal in response to the delay-locked clock.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung Chun Jang, Kyung Whan Kim, Hak Song Kim