Abstract: A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.

Abstract: A clock recovery circuit comprises an input node receiving a data signal having a data rate, and a digital oscillator producing a local clock signal with a frequency higher than the data rate. A counter clocked by the local clock signal has its count value sampled and reset at the rising and falling edges of the data signal, and a storage block coupled to the counter stores a count value that is updated in response to the current sampled count value of the counter lying in an update range between lower and upper bounds. A threshold value set is produced as a function of the updated count value stored in the storage block. Sampling circuitry receives and samples the data signal, and provides a sampled version of the data signal in response to the count value of the counter reaching any of the threshold values.

Abstract: A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.

Abstract: This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

Abstract: A method for determining a target locking time for a delay locked loop of a memory apparatus are provided. The method includes, a system inputting a first set of input signals to the memory apparatus in accordance with a first set of first operational parameters and a set of second operational parameters, the system measuring a first set of output signals from the memory apparatus in response to the first set of input signals to determine whether the delay locked loop fails at any combination of the first set of first operational parameters and the set of second operational parameters, the system determining a first candidate operational parameter from the first set of first operational parameters under which the delay locked loop does not fail for each of the set of second operational parameters, and the system determining the target locking time based on the first candidate operational parameter.

Abstract: In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.

Abstract: The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device.

Abstract: In one embodiment, electronic circuitry includes a reference circuit configured to generate a reference pulse signal synchronized with a clock signal on the basis of an input pulse signal, a delay circuit configured to delay the reference pulse signal and generate a delayed pulse signal, and an output circuit configured to output a pulse train including a plurality of pulses synchronized with the clock signal on the basis of the reference pulse signal and the delayed pulse signal, and the clock signal.

Abstract: Embodiments of bidirectional repeaters and communications systems are disclosed. In an embodiment, a bidirectional repeater includes a digital state machine configured to control the bidirectional repeater to operate under a functional mode or under a bypass mode and a bypass mode driver configured to automatically detect a direction of signal through input/output (I/O) terminals of the bidirectional repeater and to allow a signal to pass through the bidirectional repeater based on the direction of signal under the bypass mode.

Abstract: A DLL circuit (110) includes a phase delay circuit (114), a selection circuit (115), a detection circuit (117), and a clock stop circuit (116). The phase delay circuit (114) generates a plurality of delayed signals having different phases according to a clock signal. The selection circuit (115) selects one of the plurality of delayed signals as an output signal according to a setting signal. The detection circuit (117) detects a timing of switching the setting signal. The clock stop circuit (116) stops input of the clock signal to the phase delay circuit (114) for a predetermined period including the timing detected by the detection circuit (117).

Abstract: Electronic devices for correcting a duty-cycle of a clock signal are disclosed. An electronic device may include circuitry configured to receive an input clock signal and generate, based on the input clock signal, a number of corrected clock signals. The circuitry may further be configured to generate, via an amplifier of the circuitry, a number of error signals based on the number of corrected clock signals and adjust a duty cycle of the number of corrected clock signals based on the number of error signals. Further, the circuitry may be configured to disable the amplifier in response to determining that the input clock signal is disabled. Associated apparatuses and methods are also disclosed.

Abstract: A chip-to-chip process variation aware power efficiency optimization method that includes determining, using an adaptive voltage scaling (AVS) module of a processing unit in a system, an optimal voltage identification (VID) based on chip process variation. The method outputs the optimal VID from the AVS module to a voltage regulator of the system. The method adjusts a direct current (DC) load line setting based on the optimal VID of the processing unit in the system. The method regulates, using the voltage regulator of the system, a voltage supplied to the processing unit based on the DC load line setting.

Abstract: A “frequency shifter” is a clock synthesis system, that includes either a multiplexer or a multi-modulus divider (MMD), a fractional frequency divider, a tunable delay element, a sawtooth signal generator, in addition to other synchronization and control circuits. The generated sawtooth signal is used to control the delay of the tunable delay element, which in turn is used to adjust the phase of the signal generated by either M-to-1 multiplexer or the MMD, reducing its timing errors, and improving the spectral purity of the generated clock signal.

Abstract: A phase interpolation circuit includes: a first buffer circuit configured to adjust a rise time or a fall time of a first reference clock signal based on a first control signal to generate a first input clock signal; a second buffer circuit configured to adjust a rise time or a fall time of a second reference clock signal based on a second control signal to generate a second input clock signal; a detection circuit configured to detect a rise time or a fall time of the first input clock signal or the second input clock signal and generate the first control signal and the second control signal according to a detection result thereof; and a mixer circuit configured to generate an output clock signal having a phase between a phase of the first input clock signal and a phase of the second input clock signal.

Abstract: A duty correction circuit comprises a first delay circuit, a second delay circuit, a bang-bang driver, a duty detection circuit, and a delay control circuit. The first delay circuit delays an input clock signal to generate a first delayed clock signal. The second delay circuit delays the input clock signal based on a delay control signal to generate a second delayed clock signal. The bang-bang driver generates first and second driving clock signals from the first and second delayed clock signals based on a locking signal and a duty detection signal. The duty detection circuit may detect duty cycles of the first and second driving clock signals and generate the duty detection signal. The delay control circuit may generate the delay control signal and the locking signal based on the duty detection signal.

Abstract: Methods, systems, and devices for random number generation based on threshold voltage randomness are described. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.

Abstract: An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.

Abstract: A delay circuit including a first output clock generation circuit and a second output clock generation circuit. The first output clock generation circuit generates a first output clock signal by mixing phases of a first clock signal and a second clock signal based on an (n+1)-th generated delay control signal. The second output clock generation circuit generates a second output clock signal by mixing the phases of the first and second clock signals based on both an n-th generated delay control signal and the (n+1)-th generated delay control signal.

Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

Abstract: A data receiving circuit includes a clock generation circuit, a skew adjustment circuit, a leading edge detecting circuit, and a control circuit. The clock generation circuit generates a clock signal and a decision clock signal transitioning from a second level to a first level at a time point advancing by a time of ½ of the bit cycle with respect to the clock signal, according to the received reference clock signal. The skew adjustment circuit generates a skew adjustment data signal by delaying the received data signal through a delay circuit. The leading edge detecting circuit detects a leading edge of one bit of the skew adjustment data signal to generate a leading edge detection signal. The control circuit controls the delay time of the delay circuit based on the decision clock signal and the leading edge detection signal.

Abstract: The present application relates to a chip test method and apparatus, a computer device, and a readable storage medium thereof. The chip test method includes: applying a test signal to a to-be-tested chip; and sending a data signal to the to-be-tested chip such that the to-be-tested chip enters a test mode based on the test signal and the data signal, and regulating a test voltage of the to-be-tested chip.

Abstract: A phase-locked loop circuit includes a voltage controlled oscillator (VCO) that generates a VCO clock in response to a voltage control signal, a divider that divides the VCO clock to output a division clock, a phase-frequency error detector that receives a reference clock and outputs a first error compensation signal, a sampler that receives the reference clock and oversamples the reference clock at a rising edge or a falling edge to output a sampling clock, a window phase error detector that receives the reference clock and outputs a second error compensation signal, a residue phase error detector that outputs a third error compensation signal, an adder that accumulates the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal, and a loop filter that converts and output the final error compensation signal into the voltage control signal.

Abstract: A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

Abstract: A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.

Abstract: A circuit device includes an oscillation circuit configured to oscillate a resonator to thereby generate an oscillation signal, a waveform shaping circuit to which the oscillation signal is input, and which is configured to output a clock signal obtained by performing waveform shaping on the oscillation signal, a first duty adjustment circuit configured to perform a duty adjustment of the clock signal, and an output buffer circuit configured to output a first output clock signal and a second output clock signal to an outside based on the clock signal. The output buffer circuit includes a second duty adjustment circuit configured to perform a duty adjustment of the second output clock signal.

Abstract: In one embodiment, an apparatus includes: an oscillator to output a clock signal on a first line; a switch coupled to the first line; and a voltage divider coupled to the switch. The switch may be controlled to output the clock signal through the voltage divider via the first line to a pin in a non-reset mode and prevent the clock signal from being provided to the pin in a reset mode.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.

Abstract: A method and system for performing duty-cycle correction (DCC) on a clock signal is provided. The method provides a two-step duty cycle correction. The method can include performing a main DCC of a single-ended clock signal, to generate a duty cycle adjusted single-ended clock signal, wherein a duty cycle of the single-ended clock signal is corrected according to a received duty-cycle continuous control signal and converting the duty cycle adjusted single-ended clock signal to differential clock signals. The method can further include performing a trim DCC by correcting a duty cycle of the differential clock signals according to a duty-cycle trim control signal received and generated in dependence upon duty cycles detected from differential output clock signals to provide error-corrected differential clock signals.

Abstract: Delay locked loop (DLL) circuitry system and a memory device are disclosed. The DLL circuitry system includes a timer unit and a DLL circuit coupled thereto. The timer unit is enabled to generate a DLL enable signal based on the signal instructing the entry into a low power consumption mode and a predefined timer condition. The DLL enable signal enables the DLL circuit to realign an internal clock signal with an external clock signal. In this way, the DLL circuit is avoided from being unable to align the internal clock signal with the external clock signal because the memory device enters the low power mode which causes the variation of the power supply voltage of the DLL circuit. Moreover, a read or write error that may occur when data is to be read or written immediately after exiting the low power consumption mode is also avoided.

Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

Abstract: An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.

Abstract: A data acquisition system and a control method, apparatus, and device therefor, and a medium. The data acquisition system comprises: a signal transmission line, the signal transmission line having multiple first signal delay units connected in series, and the output end of each of the first signal delay units forming an acquisition point; multiple acquisition units, the acquisition units being connected to the acquisition points of the first signal delay units to acquire signals at the acquisition points; a clock unit, configured to generate a control signal; a comparison unit, configured to compare the period of the control signal with the period of a standard signal, and generate an adjustment signal according to the comparison result; and an adjustment unit, configured to adjust a power supply voltage for the signal transmission line and the clock unit according to the adjustment signal, so that the ratio of the period of the control signal to the period of the standard signal meets a set threshold range.

Abstract: A hierarchical time step generator circuit is configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator includes a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.

Abstract: A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.

Abstract: A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.

Abstract: A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

Abstract: Embodiments of the present application provide a multi-channel signal synchronization system, circuit, and method. The multi-channel signal synchronization system comprises a clock signal generation module, a synchronization signal generation module, and signal receiving modules; the clock signal generation module is configured to generate a first clock signal; the synchronization signal generation module is configured to generate a synchronization signal based on the first clock signal and transmit the synchronization signal to the clock signal generation module; the clock signal generation module generates second clock signals on the basis of the synchronization signal and transmits the second clock signals to the signal receiving modules; the synchronization signal generation module transmits the synchronization signal to the signal receiving modules.

Abstract: Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF and a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).

Abstract: In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.

Abstract: Provided is a digital fingerprint generator. The digital fingerprint generator includes: a control circuit, configured to generate a control word; a first pulse generation circuit, connected to the control circuit, and configured to output a first pulse signal in response to the control word; a second pulse generation circuit, connected to the control circuit, having a same structure as the first pulse generation circuit, and configured to output a second pulse signal in response to the control word; and an output circuit, connected to the first pulse generation circuit and the second pulse generation circuit, and configured to output a digital fingerprint based on the first pulse signal and the second pulse signal according to a predetermined first rule.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first signal line including a first part and a second part, a second signal line including a third part and a fourth part, a first inverter, a second inverter, and a control circuit. A first signal is input to the first part in a first period. A second signal is input to the third part in a second period. The first inverter outputs, to the second part, a first inverted signal obtained such that a logic of the first signal is inverted. The second inverter outputs, to the fourth part, a second inverted signal obtained such that a logic of the second signal is inverted. The control circuit brings the second signal line into a floating state in the first period, and brings the first signal line into a floating state in the second period.

Abstract: Determining the ratio between two frequencies can be a useful electronic building block in different electronic circuits with very divers functionalities.

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

Abstract: A modular programmable software defined atomic clock system includes an oscillator configured to output a periodic, oscillating electrical signal, an atomic clock physics package system, and a programmable logic controller. The atomic clock physics package system is configured to generate a reference signal based on detected electron spin transitions between two hyperfine energy levels in atoms stored in the atomic clock physics package system. The programmable logic controller is coupled to the oscillator and the atomic clock physics package system. The programmable logic controller is configured to: detect an error signal based on the generated reference signal and the periodic, oscillating electrical signal; adjust the periodic, oscillating electrical signal based on the detected error signal; and generate and output one or more output signals in one or more frequencies from the adjusted periodic, oscillating electrical signal.

Abstract: Disclosed herein is an apparatus that includes: a first input node supplied with a first clock signal; a first clock path configured to output a delayed first clock signal, the first clock path including first and second delay elements coupled in series; a second clock path configured to output additional delayed first clock signal, the second clock path including third and fourth delay elements coupled in series; a first mixer circuit configured to interpolate the delayed first clock signal and the additional delayed first clock signal to reproduce an adjusted clock signal as the first clock signal; and a control circuit configured to control delay amounts of the first, second, third, and fourth delay elements with first, second, third, and fourth codes different from one another.

Abstract: A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.

Abstract: An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.