With Variable Delay Means Patents (Class 327/158)
  • Patent number: 10848299
    Abstract: A phase interpolator includes a phase adjusting circuit. The phase adjusting circuit includes a first phase adjusting module and a second phase adjusting module, the first phase adjusting module outputs a first clock signal, and the second phase adjusting module outputs a second clock signal; the first phase adjustment module and the second phase adjustment module are connected in parallel to output an interpolation signal. Through the first phase adjustment module and the second phase adjustment module the first clock signal and the second clock signal with the same frequency and different phases are mixed in proportion by adopting a voltage mode to generate an interpolation so as to achieve the purpose of phase adjustment, and meanwhile, the circuit can be carried out under lower voltage, so that the power consumption of the phase adjusting circuit is further reduced.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 24, 2020
    Assignee: AMLOGIC (SHANGHAI) CO., LTD.
    Inventor: Ming Shi
  • Patent number: 10841072
    Abstract: An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhiqiang Huang, Hiep Pham, Chih-Wei Yao
  • Patent number: 10795401
    Abstract: A semiconductor device includes a delay-locked clock generation circuit configured to generate a delay-locked clock which is driven by at least one internal clock selected from a plurality of internal clocks in response to a phase control signal. The semiconductor device also includes a latency command generation circuit configured to generate a latency command for generating transmission data from data by latching an internal command sequentially by the at least one internal clock in response to the phase control signal and shifting the sequentially latched internal command by a period set by a shifting control signal in response to the delay-locked clock.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung Chun Jang, Kyung Whan Kim, Hak Song Kim
  • Patent number: 10777243
    Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Min Su Park, Dong Kyun Kim
  • Patent number: 10777242
    Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 15, 2020
    Assignee: SK hynix inc.
    Inventors: Min Su Park, Dong Kyun Kim
  • Patent number: 10761121
    Abstract: In various embodiments, a method for processing a Single-Edge Nibble Transmission Signal is provided. The method includes determining of at least one drop in a signal level of the time-variable Single-Edge Nibble Transmission Signal and at least one next rise in the signal level after the drop in the signal level, determining a time interval between the drop and the next rise in the signal level, and determining a quality of the Single-Edge Nibble Transmission Signal by using the time interval.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 1, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Kolof, Dietmar Koenig
  • Patent number: 10756711
    Abstract: Examples described herein provide determining skew of transistors on an integrated circuit. In an example, an integrated circuit includes a ring oscillator and first and second detector circuits. The ring oscillator includes serially connected buffers. Each buffer includes serially connected inverters that include transistors. A transistor of each buffer has a different strength of another transistor of the respective buffer. The first and second detector circuits are connected to different first and second tap nodes, respectively, along the serially connected buffers. The first detector circuit is configured to count a number of cycles of a reference clock that a cyclic signal on the first tap node is either a logically high or low level. The second detector circuit is configured to count a number of cycles of the reference clock that a cyclic signal on the second tap node is either a logically high or low level.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 25, 2020
    Assignee: XILINX, INC.
    Inventors: Amitava Majumdar, Nui Chong
  • Patent number: 10756723
    Abstract: A semiconductor apparatus includes first and second edge detection signal generators. The first edge detection signal generator may generate a first edge detection signal by gating an input signal and its inverted signal based on a first gating control signal, generated by delaying the input signal, and output the first edge detection signal to an output node. The second edge detection signal generator may generate a second edge detection signal by gating a complementary signal of the input signal and its inverted signal based on a second gating control signal, generated by delaying the complementary signal, and output the second edge detection signal to the output node. An output signal may be generated at the output node.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Hyun Kim
  • Patent number: 10749535
    Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Reuben P. Nelson, Neil E. Weeks
  • Patent number: 10741229
    Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix inc.
    Inventors: Min Su Park, Dong Kyun Kim
  • Patent number: 10727841
    Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das
  • Patent number: 10713409
    Abstract: An integrated circuit (IC) device is disclosed. The IC device includes a global clock source to generate a global clock signal. Multiple local clock sources are employed in the IC device. Each local clock source provides a local clock signal for a partitioned sub-design block in the IC device. Each local clock signal is based on the global clock signal. The IC device includes a clock controller having inputs from the global clock source and the multiple local clock sources. The clock controller (1) measures skew between each local clock source and the global clock source, and (2) generates respective control signals to adjust respective phases of each local clock signal to reduce the measured skew.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: July 14, 2020
    Assignee: Movellus Circuits, Inc.
    Inventors: Jeffrey Fredenburg, Muhammad Faisal, David M. Moore, Ramin Shirani, Yu Huang
  • Patent number: 10707844
    Abstract: A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300).
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: July 7, 2020
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Xueyan Wang, Qiang Chen
  • Patent number: 10686584
    Abstract: Generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: June 16, 2020
    Assignee: Kandou Labs, S.A.
    Inventors: Armin Tajalli, Amin Shokrollahi
  • Patent number: 10680593
    Abstract: A delay locked loop circuit includes a duty detector configured to detect a duty cycle of a clock signal, and to determine whether to perform a coarse duty cycle correction based on the detected duty, and a delay locked loop core. The delay locked loop core is configured to selectively perform the coarse duty cycle correction for the clock signal according to the determination of the duty detector, perform a coarse lock for the clock signal during a first time period different from a second time period in which the coarse duty cycle correction is performed, and perform a fine duty cycle correction and a fine lock for the clock signal.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Kyeom Kim, Won-Joo Yun, SukYong Kang, Ho-Jun Chang
  • Patent number: 10666242
    Abstract: A delay line can include a number of delay elements connected in series, each selected to impart an overall delay to an input signal. The delay line can include delay selection logic to select a subset of the delay elements to delay the input signal. The delay line can include delay element enable logic to enable the selected subset of the delay elements to delay the input signal. Further, the remaining delay elements can be disabled from contributing any delay to the input signal, and a respective periodic signal can be provided to at least one of the remaining delay elements to cause the at least one remaining delay elements to output an output signal that is a function of the respective periodic signal and that has a frequency less than that of the input signal. This configuration can reduce asymmetric aging effects on the delay line.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 26, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventor: Jeffrey Earl
  • Patent number: 10658015
    Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Min Su Park, Sun Myung Choi
  • Patent number: 10651826
    Abstract: A semiconductor device includes a plurality of delay cells coupled in series to each other, each including a pull-up transistor and a pull-down transistor coupled in series to each other; a monitoring control block suitable for controlling the delay cells to perform a monitoring operation based on an enable signal; and a coupling block that is arranged between each input terminal of the delay cells and a gate of the pull-up transistor or pull-down transistor, and suitable for adjusting a turn-on level based on the enable signal.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 12, 2020
    Assignee: SK hynix Inc.
    Inventor: Young-Hoon Kim
  • Patent number: 10637488
    Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Da In Im, Young Suk Seo
  • Patent number: 10637464
    Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Kyu Dong Hwang
  • Patent number: 10623174
    Abstract: Electrical circuits and associated methods relate to performing a phase alignment by providing N copies of clock alignment circuits, enabling and selecting different clock alignment circuits to achieve an initial phase alignment. In an illustrative example, a phase alignment circuit may include a first clock alignment circuit configured to find a first phase alignment point and a second clock alignment circuit configured to find a second phase alignment point. A control circuit may be configured to select a primary clock alignment circuit from the first clock alignment circuit and the second clock alignment circuit and generate a digital command signal to control a phase interpolator. In various embodiments, by setting the control circuit, the same phase alignment circuit may be used to perform phase alignments between clock domains with different frequencies.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: April 14, 2020
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Warren E. Cory, Chee Chong Chan
  • Patent number: 10608648
    Abstract: Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 31, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Jieming Qi, Aaron D. Willey
  • Patent number: 10608645
    Abstract: A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: March 31, 2020
    Assignee: Synopsys, Inc.
    Inventors: Biman Chattopadhyay, Ravi Mehta
  • Patent number: 10608621
    Abstract: The present disclosure relates generally to improved systems and methods for control of one or more timing signals in a memory device. More specifically, the present disclosure relates to configurable duty cycle correction at one or more DQ pins (e.g., data input/output (I/O) pins) of the memory device. For example, the memory device may include a configurable phase splitter and/or selective capacitive loading circuitry implemented to adjust the duty cycle of a timing signal at one or more DQ pins during and/or after manufacture of the memory device. Accordingly, the memory device may include increased flexibility and granularity of control over the one or more timing signals.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gary L. Howe, Jeffrey E. Koelling
  • Patent number: 10605851
    Abstract: A printed wiring board includes: a laminated body that has a plurality of wiring layers laminated therein; a first through hole that electrically connects two or more wiring layers with each other; and a second through hole that has strength to expansion and contraction of the laminated body less than in the first through hole.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 31, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shigeo Iriguchi, Naoki Nakamura, Shigeru Sugino, Takahide Mukoyama, Ryo Kanai, Nobuo Taketomi, Kiyoyuki Hatanaka
  • Patent number: 10601410
    Abstract: Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh
  • Patent number: 10573272
    Abstract: Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Christopher Mozak, Senthil Kumar Sampath
  • Patent number: 10574255
    Abstract: A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 25, 2020
    Assignee: IMEC vzw
    Inventors: Benjamin Hershberg, Jan Craninckx, Ewout Martens
  • Patent number: 10560107
    Abstract: Power supply topologies can leverage relatively smaller component sizes while meeting the power requirements of loads. In a first stage, a determination is made as to whether a high current limit is exceeded for a first duration, or whether an average current provided exceeds an average current limit, such that a power supply component (e.g., inductor) is thermally stressed. In either event, a clock frequency is reduced by a first factor. In a second stage, a determination is made as to whether an output voltage drops below a voltage threshold. If so, the clock frequency may be further reduced by a second factor.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 11, 2020
    Assignee: Apple Inc.
    Inventors: Parin Patel, Jamie L. Langlinais, Mark A. Yoshimoto, Rajarshi Paul
  • Patent number: 10530371
    Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Juho Jeon, Hun-Dae Choi
  • Patent number: 10523224
    Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 31, 2019
    Assignee: Altera Corporation
    Inventors: David Mendel, Carl Ebeling, Dana How, Mahesh Iyer
  • Patent number: 10523220
    Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: December 31, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Zhiyu Ru, Tim Yee He, Siavash Fallahi, Ali Nazemi, Delong Cui, Jun Cao
  • Patent number: 10504569
    Abstract: A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 10, 2019
    Assignee: INVECAS TECHNOLOGIES PVT. LTD
    Inventors: Gyan Prakash, Nidhir Kumar, Muniswara Reddy Vorugu
  • Patent number: 10506318
    Abstract: In accordance with an embodiment, a circuit includes an amplifier and a programmable capacitor coupled between an output of the first non-inverting and the input of the first amplifier.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francesco Polo, Richard Gaggl
  • Patent number: 10491223
    Abstract: A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hangi Jung, Hun-Dae Choi, Juho Jeon
  • Patent number: 10460777
    Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yantao Ma, Huy T. Vo
  • Patent number: 10460790
    Abstract: The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 29, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chuan-Jen Chang, Wen-Ming Lee
  • Patent number: 10446218
    Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim, John D. Porter
  • Patent number: 10447254
    Abstract: An analog-based architecture is used to produce tap spacings in an n-tap UI-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve UI-spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the UI spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: October 15, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Aniket Kadkol, Mahmoud Reza Ahmadi, Echere Iroaga
  • Patent number: 10439619
    Abstract: A recording apparatus is provided. An adjustment unit executes adjustment processing for adjusting a delay amount of a timing signal. An input control unit executes input control to input continuously recording target data to be recorded to a storage medium, to a buffer memory. A recording control unit executes recording control for recording the recording target data held in the buffer memory to the storage medium, using an input/output unit configured to receive data from the storage medium according to the timing signal. A control unit performs control such that the input control is started before a recording start instruction and the recording control is started in response to the recording start instruction, and such that the adjustment processing is executed during execution of the input control and before the recording control is started in response to the recording start instruction.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 8, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Noboru Omori
  • Patent number: 10425091
    Abstract: A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a ?? modulator and a summer to utilize an input N.? control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or ? value of the full quadrant analog interpolator.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: September 24, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dinesh Jain, Markus Friedrich Dietl
  • Patent number: 10425086
    Abstract: A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: September 24, 2019
    Assignee: KaiKuTek Inc.
    Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun-Hung Wang
  • Patent number: 10403679
    Abstract: An integrated circuit device includes a terminal region in which a second signal terminal to which a second signal is input is disposed, an AFE circuit (analog front-end circuit) that performs waveform shaping of the second signal, and a time-to-digital converter that converts a time difference between a transition timing of a first signal and a transition timing of the second signal subjected to waveform shaping, to a digital value. When a direction from a first side of the integrated circuit device toward a second side facing the first side is set as a first direction, the AFE circuit is disposed on the first direction side of the terminal region, and the time-to-digital converter is disposed on at least one side of the first direction side of the AFE circuit and a side of a direction intersecting the first direction.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: September 3, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Fumikazu Komatsu, Akio Tsutsumi
  • Patent number: 10396804
    Abstract: A circuit device includes a first circuit, a second circuit, and a comparator array section. The first circuit has a first DLL circuit having a plurality of delay elements, and delays a first signal. The second circuit has a second DLL circuit having a plurality of delay elements, and delays a second signal. The comparator array section has a plurality of phase comparators arranged in a matrix, the first delayed signal group from the first circuit and the second delayed signal group from the second circuit are input to the comparator array section, and the comparator array section outputs a digital signal corresponding to a time difference in the transition timing between the first signal and the second signal.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: August 27, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Akio Tsutsumi, Katsuhiko Maki
  • Patent number: 10367493
    Abstract: A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: July 30, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Sravanti Addepalli, Ravindra Arjun Madpur, Sridhar Yadala
  • Patent number: 10348278
    Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andreas Arp, Fatih Cilek, Andre Hertwig, Michael Koch, Matthias Ringe
  • Patent number: 10333528
    Abstract: Power supply topologies can leverage relatively smaller component sizes while meeting the power requirements of loads. In a first stage, a determination is made as to whether a high current limit is exceeded for a first duration, or whether an average current provided exceeds an average current limit, such that a power supply component (e.g., inductor) is thermally stressed. In either event, a clock frequency is reduced by a first factor. In a second stage, a determination is made as to whether an output voltage drops below a voltage threshold. If so, the clock frequency may be further reduced by a second factor.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 25, 2019
    Assignee: Apple Inc.
    Inventors: Parin Patel, Jamie L. Langlinais, Mark A. Yoshimoto, Rajarshi Paul
  • Patent number: 10326457
    Abstract: Clock generation from an external reference by generating a reference clock gating signal using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the reference clock gating signal to disable a first buffer of a ring oscillator and to enable a reference clock injection buffer, the first buffer and the injection buffer having parallel connected outputs that connect to a next buffer input; receiving a reference clock transition of a reference clock signal at the injection buffer and injecting it into the next buffer; and enabling a ring-oscillator-closed-loop mode by using the reference clock gating signal to enable the first buffer and to disable the reference clock injection buffer.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 18, 2019
    Assignee: Innophase, Inc.
    Inventor: Roc Berenguer Perez
  • Patent number: 10320398
    Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Juho Jeon, Hun-Dae Choi
  • Patent number: 10297297
    Abstract: A sampling circuit module, a memory control circuit unit, and a data sampling method, where the sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.
    Type: Grant
    Filed: December 21, 2014
    Date of Patent: May 21, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Jen-Chu Wu, Wei-Yung Chen