Abstract: An oscillator circuit includes: an oscillator, oscillating a resonator and generating a first oscillation signal; and a PLL circuit, adjusting a ratio between a first frequency of the first oscillation signal and a second frequency of a second oscillation signal output from a voltage controlled oscillator, and controlling the oscillator based on a loop filter voltage being an input voltage of the voltage controlled oscillator.

Abstract: The present invention discloses a comparison circuit having adaptive comparison mechanism is provided. A comparator is enabled by an enabling signal having an enabling state during a comparison stage to compare a first voltage and a second voltage to generate a comparison result. A comparison determining circuit sets a stage indication signal at an unfinished state and a finished state before and after the comparison result is generated. A time accumulating circuit starts to accumulate an accumulated time when the enabling signal is at the enabling state and stops accumulating when the stage indication signal is at the finished state to generate a comparison time. A determining circuit performs statistics on the comparison time to generate a predetermined threshold time and sets a predetermined comparison result as the comparison result under the condition that the comparison result is not generated and the accumulated time exceeds the predetermined threshold time.

Abstract: A semiconductor device includes an oscillator configured to generate a first clock signal, a first terminal via which an input clock signal is fed in from the outside, a first counter configured to count a clock signal based on the first clock signal between edges in the input clock signal, and a controller configured to send to the oscillator an instruction to adjust the frequency of the first clock signal based on the result of comparison of the count value by the first counter with an expected value.

Abstract: Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: A fractional-N all digital phase locked loop (ADPLL) includes a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL to reduce spurious tones introduced by delta-sigma modulation of a frequency control word without requiring active control or calibration. In some embodiments, a delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter.

Abstract: A frequency locking method for a phase-locked loop comprises the following steps: S1, a frequency control module controls a numerically controlled oscillator to obtain an maximum output frequency and a minimum output frequency; S2, obtain a minimum frequency ratio and a maximum frequency ratio by means of a time-to-digital converter and the frequency control module; S3, calculate a first frequency control word and a first frequency ratio according to the minimum frequency ratio and the maximum frequency ratio; S4, the frequency control module uses the Newton's iterative method to recalculate a new frequency control word; S5, obtain a new frequency ratio according to the new frequency control word; S6, if the new frequency ratio is within an error range, end iteration and stably output the new frequency control word, and otherwise, jump to step S4.

Abstract: A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.

Abstract: The present disclosure discloses a Beidou signal tracking system with a nonlinear phase-locked loop. A nonlinear element and a low-pass filter are added behind a loop filter to adapt to an output from control of the loop filter, and then to control a phase of an output signal. An in-phase branch pre-filtering link is added before the loop filter to smoothly processing an input signal, and a loop filter of a third-order phase-locked loop assisted by a second-order frequency-locked loop is selected to ensure basic performance index of an algorithm. The in-phase branch pre-filtering link controls signal change of an in-phase branch signal within a reasonable range. The nonlinear element and the low-pass filter behind the loop filter, after proper selection of parameters, can make the phase-locked loop quickly lock within the range where the phase-locked loop could not be locked originally.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract: A clock-data recovery circuit includes a variable data path delay, an injection-locked oscillator having a free-running frequency, and circuitry for adjusting at least one of the variable data path delay and the free-running frequency, including a counter configured to count repetitions of a bit value in an input data signal, and further being configured to, on occurrence of a first data pattern in the input data signal, indicative of saturation of inter-symbol interference, measure the input data signal at a first clock edge to determine a first data phase measurement value, measure the input data signal at clock centers immediately preceding and immediately following the first clock edge to determine second and third data phase measurement values, and based on first predetermined relationships among the first, second and third data phase measurement values, adjust the variable data path.

Abstract: A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.

Abstract: Mobile device feature disablement is provided through a method that identifies, by a mobile device, a mobile device feature of which usability is to be disabled. The method includes identifying one or more hardware devices of the mobile device that the mobile device feature relies on for proper usability of the feature. The method also includes disabling, by the mobile device, one or more drivers of the one or more hardware devices, the disabling the one or more drivers disabling usability of the mobile device feature.

Abstract: An apparatus comprising a frequency standard circuit and a tracking circuit. The frequency standard circuit may be configured to generate an internal frequency standard and adjust the internal frequency standard in response to a tuning signal. The tracking circuit may be configured to receive a reference signal from an external source and a feedback signal of the internal frequency standard and generate the tuning signal. The tuning signal may be configured to synchronize the internal frequency standard to the reference signal. The internal frequency standard may be implemented local to a frequency converter. The tracking circuit may have a bandwidth that prevents unwanted content on the reference signal from corrupting the internal frequency standard.

Abstract: In an embodiment, a duty cycle controller comprises a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal by a time less than the predetermined delay time and configured to delay the feedback clock signal by the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.

Abstract: In one embodiment, a method includes monitoring, by a control loop including a processor and a memory, a first environment. The control loop includes one or more predetermined control loop parameters. The method also includes receiving, by the control loop and in response to monitoring the first environment, first data from the first environment and receiving, by the control loop, information from an adaptation control loop. The method also includes determining, by the control loop, to automatically adjust at least one of the one or more predetermined control loop parameters based at least in part on the information received from the adaptation control loop and automatically adjusting, by the control loop, the one or more predetermined control loop parameters. The method further includes determining, by the control loop, to initiate an action based on the first data collected from the first environment and the one or more adjusted control loop parameters.

Abstract: A delay line circuit with a calibration function, includes N delay modules and a calibration module. The N delay modules are serially coupled to each other. The calibration module generates a calibration start signal and a calibration stop signal according to a calibration signal and a clock signal, and the calibration start signal is outputted to the N delay modules, so that the N delay modules output N delay signals according to N control signals and the calibration start signal. The calibration module calibrates the N control signals according to the N delay signals and the calibration stop signal, so that the N delay modules generate N calibrated delay signals according to the N calibrated control signals and the clock signal. A generation time instant of the calibration stop signal is later than a generation time instant of the calibration start signal.

Abstract: Techniques are described for peak-adaptive sampling demodulation for radiofrequency transceivers. For example, a tag input signal is received via an antenna, from which a clock input signal can be extracted. Multiple clock output signals can be generated responsive to the extracted clock input signal, such that each has a different respective phase. A multiphase selector can identify the one of the clock output signals that has the respective phase that is closest to the phase of the tag input signal and is best suited for sampling the peak of the tag input signal, accordingly. A single-path detector can generate a data output signal by using the identified clock output signal to sample the tag input signal, and the detector can filter and amplify the data output signal using small-signal devices.

Abstract: A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.

Abstract: Mobile device feature disablement is provided through a method that identifies, by a mobile device, a mobile device feature of which usability is to be disabled. The method includes identifying one or more hardware devices of the mobile device that the mobile device feature relies on for proper usability of the feature. The method also includes disabling, by the mobile device, one or more drivers of the one or more hardware devices, the disabling the one or more drivers disabling usability of the mobile device feature.

Abstract: A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.

Abstract: A charge pump unit including a capacitor that accumulates a charge on an output node according to a first clock signal and a transfer gate that takes in and applies a voltage of an input node to the output node according to a second clock signal received at a control terminal is controlled in the following manner. If the ratio of the total time of periods in which the voltage of the output node is higher than a target voltage in a predetermined monitoring period is smaller than or equal to a first threshold, i.e., if the charge pump unit executes a boosting operation for a relatively long period, a pulse voltage value of the second clock signal is increased.

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Abstract: Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.

Abstract: The invention relates to a radar unit for transmitting and receiving a signal in a frequency band. The invention includes a control means and each of a transmission path and a receiving path. The transmission path includes an output unit for generating a transmission signal and a transmission antenna for emitting a transmission signal. The receiving path receives, processes, and relays a received signal, and has at least one receiving antenna for receiving the received signal. The control means is configured to activate the transmission path and to process the received signal. The transmission path, the receiving path, and the control means are configured to toggle the transmission output by means of a mono-frequency switching sequence, and to detect the frequency of the switching sequence in the receiving path. Furthermore, the invention provides a method for operating a radar unit, in particular, a method for monitoring a transmission output of the radar unit.

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Abstract: To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

Abstract: A comparator circuit includes a differential circuit unit which detects a difference between two input signals, a current supply unit which supplies a current to the differential circuit unit, and a control unit which detects an operation timing of the differential circuit unit and controls the current supplied to the differential circuit unit by the current supply unit according to a detection result thereof.

Abstract: A clock modulation module and method for generating a modulated clock signal are provided. The clock modulation module comprises a comparator arranged to receive at a first input thereof a waveform signal, the waveform signal comprising a frequency representative of a frequency of a reference timing signal. The comparator is further arranged to receive at a second input thereof a reference voltage signal, and to output a modulated timing signal based on a comparison of the waveform signal and the reference voltage signal. Wherein the clock modulation module is arranged to output a modulated clock signal derived at least partly from the modulated timing signal output by the comparator.

Abstract: A method and apparatus for calibration of a clock signal used in data transmission is disclosed. The method includes a calibration having coarse and fine grain procedures. The coarse grain procedure begins from the center of a current eye and performs reads while decrementing the delay provided to the clock signal until at least one bit fails. This is repeated, from the center of the eye, incrementing until again at least one bit fails. The lower and upper last passing points are recorded. A fine grain procedure includes performing reads while decrementing, from the lower last passing point, recording points at which each bit fails until all fail. The fine grain procedure further includes incrementing, from the upper last passing point, recording points at which each bit fails until fail. Thereafter, a clock delay corresponding to the center of the new eye is determined based on the calibration data.

Abstract: A phase detecting apparatus and a phase adjusting method are provided. Determine whether to output a phase adjusting control signal according to a first data sampling value, a second data sampling value and a third data sampling value that are successively generated, so as to adjust a phase of a sampling clock signal used to sample a data signal.

Abstract: An electronic device includes a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; a duty cycle corrector coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector being configured to: assign and store a first duty cycle correction code in response to the first clock signal; assign and store a second duty cycle correction code in response to the second clock signal; calculate an offset code based on the first and second duty cycle correction codes; and negate the offset code from results of duty cycle correction operations.

Abstract: An improved Eighth-Order Statistics (EOS) blind phase recovery method is proposed for high-order coherent modulation formats. The method combining EOS blind phase estimate with maximum-likelihood (ML) carrier phase estimate uses multi-stage feed-forward carrier phase recovery algorithm. Experimental results show that the proposed new algorithm can reduce the required computational effort by more than a factor of 3 for 16-QAM system.

Abstract: Signal-alignment circuitry, comprising: phase-rotation circuitry connected to receive one or more input clock signals and operable to generate therefrom one or more output clock signals; and control circuitry operable to control the amount of phase rotation applied by the phase-rotation circuitry to carry out a plurality of alignment operations, the alignment operations comprising: one or more first operations each comprising rotating one or more of said output clock signals relative to one or more of the other said output clock signals, to bring a phase relationship between said output clock signals, or clock signals derived therefrom, towards or into a given phase relationship; and one or more second operations each comprising rotating all of said output clock signals together, to bring a phase relationship between said output or derived clock signals and said input clock signals or an external-reference signal towards or into a given phase relationship.

Abstract: According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path.

Abstract: Disclosed embodiments may include a circuit having a clock-to-output (TCO) compensation circuit coupled to a RAM pull-up transmitter and a RAM pull-down transmitter. The TCO compensation circuit may be configured to compare a first output with a second output and to generate a delay code, based on the comparison, for at least one other RAM transmitter on the die to adjust a duty cycle of a third output associated with the at least one other RAM transmitter. Other embodiments may be disclosed.

Abstract: A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.

Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

Abstract: An electronic device includes a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; a duty cycle corrector coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector being configured to: assign and store a first duty cycle correction code in response to the first clock signal; assign and store a second duty cycle correction code in response to the second clock signal; calculate an offset code based on the first and second duty cycle correction codes; and negate the offset code from results of duty cycle correction operations.

Abstract: Apparatuses and methods for mitigating uneven circuit degradation of delay circuits are disclosed. In an example method, an imbalance in transistor threshold voltages is detected between a transistor of a first delay circuit and a transistor of a second delay circuit that is series coupled to the first delay circuit, and a clock level of an input clock signal to the first delay circuit is switched responsive to detecting the imbalance.

Abstract: An oscillator circuit includes an adjustable frequency oscillator configured to free-run at a first frequency below a desired second target frequency. This adjustable frequency oscillator is configured to modulate a frequency of its periodic output signal upwards from the first frequency to the second frequency in response to a feedback bias current. A divider is also provided, which is configured to convert the periodic output signal to a reduced-frequency control signal. This reduced-frequency control signal is provided to a frequency-to-current (F2C) converter, which is configured to drive the adjustable frequency oscillator with the feedback bias current (e.g., pull-down current) in response to the reduced-frequency control signal.

Abstract: A controlled oscillator is tuned to produce a desired, temperature independent frequency. A first frequency ratio is determined between a first frequency of the output signal generated by the controlled oscillator and a frequency of an output signal from another oscillator. The first frequency is determined based on a sensed temperature. A desired frequency of the output signal of the controlled oscillator is used to determine a desired frequency ratio between the desired frequency and the frequency of the output signal from the other oscillator. The controlled oscillator is tuned and the frequency ratio measured until the tuning has caused the desired frequency ratio to be achieved, thereby causing the controlled oscillator to provide the desired frequency.

Abstract: A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.

Abstract: Exemplary embodiments are related to a clock doubler. A device may include a duty cycle correction circuit configured to receive an input clock signal and convey a corrected clock signal. The duty cycle correction circuit may include a first circuit to convey an output voltage during a first cycle of the input clock signal and correct a current mismatch of the first circuit during a second cycle of the input clock signal. The duty cycle correction circuit may also include a second circuit to convey the output voltage during the second cycle and correct a current mismatch of the second circuit during the first cycle. Further, the device may include a clock generator for receiving the corrected clock signal and generating an output clock.

Abstract: A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction

Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

Abstract: A method and apparatus for aligning an input signal to a clock signal in an integrated circuit are disclosed. The method includes receiving an input signal; determining whether the input signal is arriving too early or too late via a plurality of delay lines; and adjusting a delay of the plurality of delay lines in accordance with a result of the determining.

Abstract: Disclosed are various embodiments for a clock and data recovery (CDR) system. The CDR system comprises a transition detection stage and a clock recovery stage. The transition detection stage is responsible for receiving the data signal and detecting whether a transition exists in the data signal by oversampling the data signal. The clock recovery stage generates a recovery clock based on whether there is a transition in the data signal.