Abstract: A recording apparatus is provided. An adjustment unit executes adjustment processing for adjusting a delay amount of a timing signal. An input control unit executes input control to input continuously recording target data to be recorded to a storage medium, to a buffer memory. A recording control unit executes recording control for recording the recording target data held in the buffer memory to the storage medium, using an input/output unit configured to receive data from the storage medium according to the timing signal. A control unit performs control such that the input control is started before a recording start instruction and the recording control is started in response to the recording start instruction, and such that the adjustment processing is executed during execution of the input control and before the recording control is started in response to the recording start instruction.

Abstract: A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a ?? modulator and a summer to utilize an input N.? control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or ? value of the full quadrant analog interpolator.

Abstract: A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.

Abstract: An integrated circuit device includes a terminal region in which a second signal terminal to which a second signal is input is disposed, an AFE circuit (analog front-end circuit) that performs waveform shaping of the second signal, and a time-to-digital converter that converts a time difference between a transition timing of a first signal and a transition timing of the second signal subjected to waveform shaping, to a digital value. When a direction from a first side of the integrated circuit device toward a second side facing the first side is set as a first direction, the AFE circuit is disposed on the first direction side of the terminal region, and the time-to-digital converter is disposed on at least one side of the first direction side of the AFE circuit and a side of a direction intersecting the first direction.

Abstract: A circuit device includes a first circuit, a second circuit, and a comparator array section. The first circuit has a first DLL circuit having a plurality of delay elements, and delays a first signal. The second circuit has a second DLL circuit having a plurality of delay elements, and delays a second signal. The comparator array section has a plurality of phase comparators arranged in a matrix, the first delayed signal group from the first circuit and the second delayed signal group from the second circuit are input to the comparator array section, and the comparator array section outputs a digital signal corresponding to a time difference in the transition timing between the first signal and the second signal.

Abstract: A first integrated circuit configured to send data to a second integrated circuit may perform a duty cycle correction process and/or a skew correction process. For duty cycle correction, a data-in input buffer is enabled to feedback an output clock signal from an output clock node to a duty cycle correction circuit that adjusts a delay of a clock signal received from a delay-locked loop circuit. For skew correction, data-in input buffers are enabled to feedback an output clock signal and an output data signal to adjust delay amounts of delay circuits that adjust delays of clock signals output to clock inputs of output path circuits.

Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.

Abstract: Power supply topologies can leverage relatively smaller component sizes while meeting the power requirements of loads. In a first stage, a determination is made as to whether a high current limit is exceeded for a first duration, or whether an average current provided exceeds an average current limit, such that a power supply component (e.g., inductor) is thermally stressed. In either event, a clock frequency is reduced by a first factor. In a second stage, a determination is made as to whether an output voltage drops below a voltage threshold. If so, the clock frequency may be further reduced by a second factor.

Abstract: Clock generation from an external reference by generating a reference clock gating signal using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the reference clock gating signal to disable a first buffer of a ring oscillator and to enable a reference clock injection buffer, the first buffer and the injection buffer having parallel connected outputs that connect to a next buffer input; receiving a reference clock transition of a reference clock signal at the injection buffer and injecting it into the next buffer; and enabling a ring-oscillator-closed-loop mode by using the reference clock gating signal to enable the first buffer and to disable the reference clock injection buffer.

Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

Abstract: A sampling circuit module, a memory control circuit unit, and a data sampling method, where the sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.

Abstract: A delay control device and method are disclosed, which relate to a technology for compensating for a delay difference of a delay locked loop (DLL). The delay control device may include a delay locked loop (DLL) configured to adjust a delay time of a delay line, and compensate for a delay time of a replica delay circuit based on a calibration signal. The delay control device may include a real clock path delay circuit configured to delay an output of the delay locked loop (DLL. The delay control device may include a control signal generator configured to generate the calibration signal in consideration of a difference between the delay time of the replica delay circuit and the delay time of the real clock path delay circuit.

Abstract: A system for controlling a hold-margin in a semiconductor memory device includes a programmable RC network communicatively coupled to a delay logic circuit, a latch clock generator and a latch circuit. A delay associated with a clock path is induced using a combination of a logic circuit and a wire placed across at least one of a column and a row of the semiconductor memory device. A delay associated with the data path is induced using a combination of the delay logic circuit and at least one of the load cell and a wire routed across at least one of a column and a row of the semiconductor memory device. The system controls the hold-margin based on the delay associated with the data path and the delay associated with the clock path.

Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify vertical alignment between data transmitted using multi-level signaling. Such multi-level signaling may be configured to capture transmitted data during a single clock cycle of a memory controller. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

Abstract: An interpolative divider includes a look ahead sigma delta modulator circuit to generate divide values according to a divide ratio. A plurality of M storage elements are coupled to the sigma delta modulator to store the divide values, M being at least 2. A selector circuit selects the respective divide values and supplies the divide values to a portion of an interpolative divider circuit, the portion including a divider and a phase interpolator. The interpolative divider generates an output clock signal having a first clock period that may be determined by the first and second divide values. The M storage elements are loaded by a clock signal that is slower than the output clock signal by at least half.

Abstract: A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.

Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

Abstract: An analog-based architecture is used to produce tap spacings in an n-tap fractionally-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve fractionally spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the fractionally spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

Abstract: The present invention relates to pulse power technology. The system includes an input channel, a pulse edge detector (2) connected in series with two inputs, a filter (3), a variable delay unit (4), and a feedback channel from the generator to one of the inputs of the pulse edge detector (2). The system comprises a reference delay unit (1), and the input channel is connected both to the variable delay unit (4) and to a reference delay unit (1) for simultaneous supply of input to said units. Signals to both inputs of the pulse edge detector (2) are synchronous on average, i.e. tstab.avg=1/??tstab dt=tref with ?>>?est.oper where: tstab.avg—generator output delay relative to the input signal, averaged over the operation time of the system ? at a given tref; tref—reference unit (1) output delay relative to the input signal; ?est.

Abstract: A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.

Abstract: An apparatus comprises: a main frequency quadrupler configured to receive a first clock and output a second clock of a quadruple frequency in accordance with a first control signal and a second control signal, wherein a timing difference between a first rising edge and a second rising edge of the second clock is controlled by the second control signal, and a timing difference between the first rising edge and a third rising edge of the second clock is controlled by the first control signal; an auxiliary frequency quadrupler configured to receive the first clock and output a third clock of the quadruple frequency with a timing offset controlled a third control signal; and a calibration circuit configured to generate and output the first control signal, the second control signal, and the third control signal in accordance with a timing difference between the second clock and the third clock.

Abstract: A memory device includes a delay locked loop (DLL) circuit to receive an external clock, and delay the external clock by a DLL delay time to provide a DLL clock, an output driver to output the DLL clock as a data strobe signal, and a DLL offset control circuit configured to receive at least one of a plurality of functional statement commands, and adjust the DLL delay time based on the at least one of the functional statement commands. Each one of the DLL circuit and the output driver is selectively powered according to the at least one of the functional statement commands.

Abstract: Described is an apparatus comprising: a multi-modulus divider; and a phase provider to receive a multiphase periodic signal and operable to rotate phases of the multiphase periodic signal to generate an output which is received by the multi-modulus divider.

Abstract: A semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal.

Abstract: The present disclosure includes circuits and methods that adjust and correct duty cycles of circuits. The circuits and methods receive a signal from a first circuit and forward the received signal to a second circuit that retrieves a first setting (X) that provides a measure of duty cycle of the received signal. The circuits and methods then invert the received signal, retrain the second circuit based upon the inverted received signal, and retrieve a second setting (Y) of the retrained second circuit. The second setting (Y) provides a measure of duty cycle of the inverted received signal. The circuits and methods then adjust the duty cycle of the received signal based upon the first and second settings (X, Y) and further retrain of the second circuit to provide an improved duty cycle in a direction closer to 50 percent.

Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

Abstract: The embodiments of the present invention provide an apparatus of an efficient digital duty cycle adjuster and the method of operation thereof. The method includes: providing an input clock having an input clock duty cycle; inserting at least one programmable delay of a programmable delay line to the input clock, the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and adjusting an output clock duty cycle of an output clock by configuring the programmable delay, the output clock is generated by a selecting circuit, the selecting circuit includes a select signal, and the select signal is determined in accordance with the first delay and the second delay.

Abstract: Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

Abstract: A phase locked loop (PLL) for a carrier generator includes a front-end circuit that receives a frequency reference signal and generates a control signal based on the frequency reference signal and a feedback signal. A demultiplexer selectively outputs the control signal to a plurality of tuning arrangements. The plurality of tuning arrangements includes a first tuning arrangement that generates a first carrier signal based on the control signal and a second tuning arrangement that generates a second carrier signal based on the control signal. A multiplexer outputs the feedback signal based on the first carrier signal and the second carrier signal.

Abstract: An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information.

Abstract: An embodiment circuit includes a first voltage-controlled delay line (VCDL), a second VCDL, and a first flip-flop. The first VCDL includes a first input terminal configured to receive a first input voltage, and a second input terminal configured to receive a clock signal. The second VCDL includes a first input terminal configured to receive a second input voltage, and a second input terminal configured to receive the clock signal. The first flip-flop includes a reset pin coupled to an output terminal of the first VCDL, and a clock pin coupled to an output terminal of the second VCDL.

Abstract: A comparator circuit outputs a comparison result obtained by comparing a data signal with a threshold whose magnitude is adjusted based on a first offset value at a timing synchronized with a second clock signal whose phase is adjusted based on a difference in phase between the data signal and a first clock signal and a second offset value. An eye monitor circuit thins comparison results obtained in a clock data recovery (CDR) circuit for individual symbols of the data signal by comparing the data signal with a threshold, selects a comparison result corresponding to a symbol for which the comparison result is obtained by the comparator circuit, determines, by comparing the selected comparison result with the comparison result obtained by the comparator circuit, whether or not an error has occurred due to the first or second offset value, and outputs the number of times the error has occurred.

Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.

Abstract: A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

Abstract: A semiconductor device for controlling a display device includes a generation unit configured to generate a reference voltage, a booster unit configured to boost the reference voltage to generate a bias voltage, and a conversion unit. The conversion unit receives a status signal generated from a power supply voltage and is configured to boost a voltage level of the status signal to that of the bias voltage for controlling drive of the display device. A control unit is configured to stop operation of at least one of the generation unit and the booster unit when one of a value of the power supply voltage and a value of a power supply current flowing from a power supply that generates the power supply voltage is lower than a predetermined threshold.

Abstract: Phase synthesis techniques (PST) useful in a wide variety of communication systems based on wireless, optical and wireline links, disclose methods and circuits for a programmable synthesis of a waveform from a referencing clock with phase resolution matching a single gate delay.

Abstract: Programmable logic units are described. A described unit includes one or more input interfaces to receive one or more input signals; logic elements that are individually programmable; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that is configured to selectively form one or more interconnections within the unit based on one or more programming settings. The programmable interconnect array can be programmable to route the one or more input signals from the one or more input interfaces to at least a portion of the logic elements, programmable to route one or more intermediate signals among at least a portion of the logic elements, and programmable to route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface.

Abstract: A clock generation circuit may include a first clock generator and a second clock generator. The first clock generator may generate a first output clock toggling in synchronization with a rising edge of a first input clock. The second clock generator may generate a second output clock based on a second input clock and the first output clock. The second output clock may have a level changing based on the first output clock, and may be generated at a rising edge of the second input clock.

Abstract: A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.

Abstract: An inductor-less local oscillator (LO) signal generation apparatus configured to generate one or more output signals which reduce a frequency pulling effect. The LO signal generation apparatus includes a multi-phase signal generation circuit, a phase signal generation circuit and one or more output circuits. The multi-phase signal generation circuit receives an input clock signal having a first frequency to generate a multi-phase clock signal. The multi-phase clock signal includes a plurality of clock signals each having the first frequency and different phases. The phase signal generation circuit is coupled to the multi-phase signal generation circuit to receive the multi-phase clock signal and output a plurality of phase signals indicating the phases of the clock signals. The one or more output circuits output the one or more output signals according to the clock signals and the phase signals without receiving feedback of any of the one or more output signals.

Abstract: An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.

Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

Abstract: An operation control method of a semiconductor memory device includes executing a Delay Locked Loop (DLL) locking in response to a DLL reset signal and measuring a loop delay of a DLL. The operation control method further includes storing measured loop delay information and DLL locking information; and performing a delay control of a command path using the stored loop delay information and DLL locking information independent of the DLL, during a latency control operation.

Abstract: An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.

Abstract: A system for controlling a multi-element antenna array comprising a plurality of elements each arranged to receive a signal from a signal source, wherein each of the plurality of elements includes a frequency locking module arranged to lock the frequency of the signal received by each of the elements, and, a phase control module being in communication with each of the frequency locking modules to control the phase of the signal received by each of the elements.

Abstract: A method includes, in at least one aspect, determining a relative delay of a signal path with respect to a timing budget; determining that the signal path is active; determining a value of a voltage being supplied to the signal path; and causing an adjustment in the voltage being supplied to the signal path based on the relative delay, the signal path being active, and the value of the voltage being supplied to the signal path.

Abstract: A system for measuring an access time of a memory includes a first delay unit configured to delay a clock signal by a first delay time and to output a first delayed clock signal, a second delay unit configured to delay the clock signal by a second delay time greater than the first delay time and to output a second delayed clock signal, a memory configured to store data, the data being read from the memory in response to the first delayed clock signal, a detection data storage configured to store the data read from the memory in response to the second delayed clock signal, and a controller configured to measure an access time of the memory based on a comparison of the data in the detection data storage and the data in the memory, the first delayed clock signal and the second delayed clock signal.

Abstract: A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.

Abstract: The display driving circuit including a type detector for receiving a data packet including a 2-bit embedded signal, in which a clock signal embedded in a data signal, and outputting a first reference clock or a second reference clock different from the first reference clock according to a type of the data packet, a window generator for receiving multi-phase clocks and providing to the type detector a first window reference and a second window reference different from the first window reference to be used in determining the type of the data packet, a buffer for delaying the first reference clock by a first interval and delaying the second reference clock by a second interval different from the first interval, and a multiplexer for multiplexing the delayed first and second reference clocks and outputting a multiplexed reference clock may be provided.