Abstract: A pulse stretcher is disclosed comprising, a stretcher input (10) and a stretcher output (20); an asynchronous finite state machine; and a delay generator (40) having a delay input connected to the stretcher output, and a delay output connected to a second input of the FSM. The asynchronous FSM comprises: a first Muller C-element gate (250) having an output connected to the stretcher output, a second Muller C-element gate (260) having an output; and a combinatorial logic circuit (270) connected to the stretcher input, to first and second inputs of each of the first and second C-elements. The first and second Muller C-element gates are cross-coupled via the combinatorial logic, such that the respective outputs of the C-element gates are complementary and, in response to receiving the input pulse at the stretcher input, the output of the first Muller C-element gate provides a stretched version of the input pulse.

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

Abstract: A modulator includes an oscillator to start an oscillation operation when an input data changes from a first logic to a second logic, and stops the oscillation operation when the input data changes from the second logic to the first logic, a pulse generator to output a predetermined number of pulses of a pulse signal having a predetermined pulse width when the input data changes from the second logic to the first logic, and a signal selector to select an oscillation signal outputted from the oscillator when the input data has the second logic, and selects the pulse signal outputted from the pulse generator when the input data has the first logic.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: The instant disclosure relates to a circuit for comparing a voltage with a first threshold, in which said first threshold depends on a second threshold of opening at least one first normally closed breaker.

Abstract: An auto-tuned ramp generator and a method for generating a sawtooth signal are provided. In the method and apparatus, a sawtooth signal is compared to a first reference voltage and a second reference voltage. In response to determining that the sawtooth signal does not exceed the first reference voltage, the voltage level of the sawtooth signal is increased. In response to determining that the sawtooth signal exceeds the second reference voltage, the voltage level of the sawtooth signal is decreased. The voltage level the sawtooth signal is retained if the sawtooth signal remains between the first and second reference voltages.

Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

Abstract: The present invention provides systems and methods for reducing harmonics, for example when using an AC to AC converter to drive a load such as a motor drive. In a first embodiment, a plurality of load driving circuits is provided, each drawing current from a 3-phase AC supply and driving an AC load, wherein each of said load driving circuit includes a 3-phase rectifier, with the rectifiers of the load driving circuits being controlled such that the rectification of the AC supply by the load driving circuits is staggered. In a second embodiment, a load driving circuit comprises an electronic inductor configured to control the DC link voltage and/or current such that the current drawn from the AC supply by the load driving circuit has a stepped profile. The first and second embodiments may be combined.

Abstract: Systems and apparatuses for a configurable, temperature dependent reference voltage generator are provided. An example apparatus includes control logic configured receive temperature data, and produce a signal, based on the temperature data, indicative of the temperature data, a temperature dependence and a temperature slope. The apparatus may also include a temperature slope reference generator configured to produce a reference voltage having the temperature dependence and the temperature slope, based on the signal from the control logic.

Abstract: A programmable logic device (PLD) includes a programmable fabric, a plurality of input/output (I/O) blocks, and a plurality of high voltage power field effect transistors (FETs). The PLD can be programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric. Each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.

Abstract: An apparatus and a method for selective and adaptive slope compensation in peak current mode controlled power converter are disclosed. The selective and adaptive slope compensation in peak current mode controlled power converter is implemented by hardware, software, and/or combination of both to carry out start of a pulse width modulated period and delay of a start of slope compensation by a first time from the starting of the pulse width modulated period.

Abstract: A display device includes a display panel and a chip-on-film (COF) bonded to the display panel. The chip-on-film includes a film on which a driving chip is mounted, a plurality of film lines on the film, and at least one dummy pattern on the film between an adjacent pair of films in the plurality of film lines.

Abstract: A miniature intelligent circuit breaker, including a box body, the box body including an upper cover and a bottom box, and a circuit breaker actuating mechanism for switching on/off the circuit breaker, a wire inlet end, and a wire outlet end being arranged in the box body. An automatic closing function part is arranged inside the box body and includes an automatic closing mechanical unit and an automatic closing control unit. The automatic closing mechanical unit includes a motor and an intermediate transmission mechanism. The operation of the motor is realized through the automatic closing control unit. The circuit breaker actuating mechanism is driven to move through the transmission of the intermediate transmission mechanism, such that the closing action of the circuit breaker is ultimately realized.

Abstract: Techniques are provided that can extend the efficiency of a switching regulator further into the low current region by making use of the available knowledge on predictable load variations and voltage ripple tolerance across different states, providing improved efficiency and reducing total current consumption. The load current requirement in low power states is provided using switch mode rather than linear regulation, the switch mode operation being controlled by a mode dependent control circuit so as to minimize the energy cost of the switching operation in each mode and thus obtain improved efficiency from the power source.

Abstract: An electromechanical switching circuit comprises an integrated circuit (IC) having an input terminal, an output terminal and a control terminal. The IC is arranged based on a voltage transition at the control terminal, sampling the voltage level at the input terminal and supplying it at the output terminal. The output voltage level is maintained at the output terminal until a voltage transition at the control terminal. A control circuit connected to the control terminal includes a first monostable switch whose actuation causes a voltage transition at the control terminal so the voltage level applied at the input terminal is supplied at the output terminal. An output circuit includes a second, electromechanical, monostable switch whose contacts are moved to their unstable state in response to a first voltage level at the output terminal and allowed to resume their stable state in response to a second voltage level at the output terminal.

Abstract: A semiconductor diode scintillation detector probe, in conjunction with a base-line-stabilized, wide-bandwidth first amplifying circuit DC-coupled to a constrained-bandwidth second amplifying circuit DC-coupled, in turn, to a novel analog threshold discriminator circuit, suppresses base-line fluctuation and noise at low input count-rates, while providing a linear rate-meter response for time-random input pulse rates far in excess of what would otherwise—as in the prior art—be 100% saturation.

Abstract: The semiconductor device includes a pulse width comparator suitable for generating an internal pulse signal having the same pulse width as an output pulse signal whose pulse width is controlled by first and second control signals during a predetermined period and suitable for generating first and second digital signals and a comparison pulse signal from the internal pulse signal according to a delay time which is set by the first and second control signals, an output pulse signal generator suitable for retarding the comparison pulse signal by the delay time determined by first and second control signals to generate the output pulse signal, and a control signal generator suitable for generating the first and second control signals which are sequentially enabled in response to pulses of the output pulse signal.

Abstract: In one embodiment, method of signal processing can include: (i) determining a high level sampling pulse amount by counting a number of pulses of a first clock signal during a high level portion of a period of a first PWM; (ii) generating a first pulse signal based on a second clock signal and the high level sampling pulse amount; (iii) determining a low level sampling pulse amount by counting a number of pulses of the first clock signal during a low level portion of the period of the first PWM signal; (iv) generating a second pulse signal based on the second clock signal and the low level sampling pulse amount; and (v) generating a second PWM signal based on the first and second pulse signals.

Abstract: A circuit configuration for generating pulses within a time interval on the basis of an input signal includes a counting unit, a comparator unit and a first adder circuit; the time interval being predicted on the basis of at least two defined changes in input signals; the circuit configuration being configured for triggering at the beginning of the time interval by the first adder circuit on the basis of clock pulses, for generating and outputting pulses; for counting a number of generated and output pulses using the counting unit; for comparing the counted number to a setpoint value using the comparator unit; and for ending the generation and outputting of the pulses in response to the reaching of the setpoint value or the ending of the time interval.

Abstract: A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. The first and second temperature-dependent voltages varying according to a temperature and the third temperature-dependent voltage is constant regardless of variation of the temperature. The period controller configured to determine an amount of a current discharging from an internal node in response to the control voltage and outputs a periodic signal whose cycle time is determined according to a level of an internal signal induced at the internal node.

Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

Abstract: A pulse width modulation signal with a less distortion component that is not influenced by a common-mode noise or an offset voltage is generated. Pulse signal generation circuits 6, 7 generate pulse signals S1, S2 whose pulse widths are discharge times t1, t2 of integrators 3, 4, respectively, a PWM signal generation circuit 8 detects discharge end timings of the integrators 3, 4 based on the pulse signals S1, S2, and a pulse whose pulse width is a time between discharge end timing of one of the integrators 4 and discharge end timing of the other one of the integrators 3 is generated so as to be output as a PWM signal Spwm.

Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.

Abstract: A device and a method for pulse width modulation is disclosed, wherein the temporal occurrence of both the respectively rising and the respectively falling edges of a pulse signal is varied.

Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.

Abstract: A duty cycle corrector includes an SR latch, a first switch and a second switch. The SR latch is configured to generate first and second control signals according to first and second clocks. The first switch is coupled between a work voltage and an output node, and selectively closes and opens according to the first control signal. The second switch is coupled between the output node and a ground voltage, and selectively closes and opens according to the second control signal. The output node is used to output an output clock.

Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

Abstract: The frequency characteristic of a voltage-feedback class-D amplifier circuit for driving an output load is improved. A triangular-wave correction circuit which compensates a gradient of a triangular wave is provided to a triangular-wave signal generator which supplies a triangular wave signal used as a PWM carrier to a comparison circuit for performing PWM modulation of an input signal. In an area where a duty of a command value for an output circuit drive becomes about 50%, a slew rate (gradient) of the triangular wave is decreased.

Abstract: An IC generally comprises enable pin, ground pin, input pin, output pin, load switch, control circuitry, and level shifter. Load switch is coupled between the input pin and output pin and receives a negative voltage through the input pin. The control circuitry is coupled to the enable pin, the ground pin, and the load switch and controls the load switch and uses ground pin as positive supply rail and input pin as an internal ground. Voltage applied to the input terminal is negative, enabling pulling of the gate of a transistor of a level shifter to ground turns transistor as “on,” enabling a negative output signal to be provided through output pin VOUT. Therefore, the output signal (at output pin VOUT) can be ground (applied to the ground pin GND) when the transistor is “off” and can be the negative voltage (applied to the input pin VIN) when transistor is “on.

Abstract: The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b1, b2, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b1, b2, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate.

Abstract: Systems and methods are disclosed including a duty cycle module having two timer circuits to measure pulse widths of a clock signal. Two comparators are used to generate control signals depending upon comparisons of the pulse width measurements. In response to the control signals, either the clock signal or an inverted clock signal may be programmably delayed such that combination of the clock signal and the inverted clock signal results in a corrected clock signal. Systems and methods are also disclosed for verifying operation of a duty cycle module.

Abstract: The clock circuit of an integrated circuit operates with tolerance of variation in power. A compensation circuit is powered by a supply voltage. The compensation circuit generates a compensated voltage reference, which is compensated for variation in the supply voltage. The compensated voltage reference is compared by comparison circuitry against an output of timing circuitry, to determine timing of the clock signal.

Abstract: A method and a system for determining the observability of faults in an electronic circuit include a processor that simulates, in a simulation phase, a behavior of the electronic circuit using a simulation model, and that determined, in an analysis phase, based on the simulation, and for each of a plurality of elements of the electronic circuit, time periods in which an occurrent fault could cause a deviation in analysis output signals, where the occurrent fault is determined not to cause any deviation in output signals in other time periods.

Abstract: An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier.

Abstract: A clock system includes a local clock buffer adapted to receive a variable global clock signal. The local clock buffer produces a first local clock signal from the variable global clock signal. The clock system includes a pulse width logic control circuit in operable communication with the local clock buffer. The pulse width logic control circuit may be adapted to limit the first local clock signal pulse width to be less than the variable global clock signal pulse width during a slow mode. The pulse width logic control circuit may be adapted to expand the first local clock signal pulse width to be greater than the variable global clock signal pulse width during a fast mode. The limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line.

Abstract: A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.

Abstract: A counter circuit includes two pairs of registers configured to swap contents based on a timer overflow or underflow condition. The counter circuit also includes a waveform generator that generates a composite pulse width modulated signal with a period and duty cycle specified by values stored in the registers. A demultiplexing circuit generates first and second signals from the composite signal.

Abstract: A PWM-signal-output circuit includes a first output unit to output a PWM signal with a first duty cycle, in a first period in which a motor starts rotating, a second output unit to output the PWM signal whose duty cycle increases toward a second duty cycle and decreases from the second duty cycle in a period from a logic level change in speed signal until its subsequent logic level change, in a second period following the first, the speed signal having a period corresponding to a motor-rotation speed and a logic level changing alternately, and a third output unit to output the PWM signal whose duty cycle increases toward that of the input signal and thereafter decreases from that of the input signal in a period from a logic level change in the speed signal until its subsequent logic level change, after the second period elapses.

Abstract: In one embodiment, an apparatus may include a clock generator to generate a format clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the format clock signal and the serial data.

Abstract: A pulse generator is provided. The pulse generator includes: a time delayed pulse generation unit including a plurality of delay cells for receiving a first pulse having a first pulse width and outputting pulses delayed by a particular time delay value on the basis of one of a rising edge and a falling edge of the first pulse; an edge combiner configured to receive the plurality of time delayed pulses from the time delayed pulse generation unit and generate second pulses having a second pulse width; and a channel selector configured to regulate the number of outputs of the second pulses generated by the edge combiner.

Abstract: A pulse width modulation circuit of the present invention changes a voltage of a charging circuit based on an input signal voltage and in synchronization with a first switching signal; changes, during a predetermined second period following a first period during which the voltage of the charging unit is changed, the voltage of the charging unit in an opposite direction to a direction in which the voltage is changed during the first period, based on a constant bias current; detects time starting from when the second period starts to when the voltage of the charging unit reaches a predetermined reference voltage; and generates, based on the detected time which is repeatedly output each time the first switching signal is output, a pulse signal having a pulse width of the time.

Abstract: A method and apparatus to drive a load using a pulse-width modulated (PWM) signal and spread a spectrum of the PWM signal across a plurality of frequencies while maintaining a constant duty cycle for the load.

Abstract: A semiconductor integrated circuit according to an embodiment includes a clock signal generation section, a clock waveform shaping section and a plurality of function blocks. The clock signal generation section generates a clock signal of a predetermined frequency. The clock waveform shaping section generates a plurality of clock signals having the same phase as a phase of the clock signal generated by the clock signal generation section at rising edges and different phases at falling edges. Each of the plurality of function blocks has a plurality of flip flops that operate with any one of the plurality of clock signals generated by the clock waveform shaping section.

Abstract: A digital sensing apparatus includes a sensing unit capable of providing a sensing response associated with an environmental parameter, and a digital readout module including a reading unit for generating a pulse signal having a pulse width as sociated with the sensing response, and a converting unit. The converting unit includes a clock signal generator for generating a variable-frequency clock signal, and a counter operable to count a width value of the pulse width of the pulse signal using the clock signal, so as to generate a digital sensing code. The frequency of the clock signal from the clock signal generator is adjustable to adjust resolution of the width value of the pulse width of the pulse signal.

Abstract: The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.

Abstract: A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.

Abstract: An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.

Abstract: There is described a method and corresponding pulse generating device, for generating an output pulse signal having an output pulse duration. The method comprises: receiving at an input port an input pulse signal comprising an input pulse duration; duplicating the input pulse signal into a first digital pulse signal and a second digital pulse signal each comprising the input pulse duration; delaying at least one of the first and the second digital pulse signals by a time delay to obtain respectively a first and a second delayed digital pulse signal, a time delay difference between the first and the second delayed digital pulse signals being substantially equal to the output pulse duration; logically combining the first and the second delayed digital pulse signals to generate the output pulse signal with the output pulse duration smaller than the input pulse duration; and outputting the output pulse signal at an output port.

Abstract: A method and a circuit configuration are provided for generating a multiphase PWM signal. For this purpose a number of PWM generators are provided, which respectively have one counter, two comparators and one state memory, each PWM generator outputting a PWM signal, which represents a phase of the multiphase PWM signal, the PWM generators being coupled with one another via multiplexers such that the counters of the PWM generators that are coupled with one another are clocked identically.