Abstract: A clock frequency multiplier design is provided. The clock frequency multiplier includes an input stage arranged to receive an input clock signal, a first clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a first signal dependent on a low phase of the input clock signal, a second clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a second signal dependent on a high phase of the input clock signal, and an output stage operatively connected to the first clock cycle generator stage and the second clock cycle generator stage and arranged to output a high pulse on an output clock signal for every low pulse on the first signal and the second signal.

Abstract: The present invention provides a mechanism for combining programming signals to provide an output signal, the properties of which depend only on selected properties of the programming signals. An embodiment of the invention includes first and second edge-to-pulse converters. The first edge-to-pulse converter generates an intermediate signal having a width determined by received initiation and termination signals. The second edge-to-pulse converter generates an output signal, responsive to the intermediate signal and the termination signal. The output signal has a width determined by a first edge of the initiation signal and a first edge of the termination signal.

Abstract: A switching regulator control circuit for PFM control of a DC-DC converter includes a reference voltage producing circuit, a voltage dividing circuit for dividing an output voltage of the DC-DC converter, a comparator for comparing the reference voltage and the divided voltage and outputting a comparison signal, a ring oscillator for outputting a signal for controlling the output transistor, which controls the output voltage of the DC-DC converter, and a logic OR circuit having a first input connected to an output of the ring oscillator and a second input connected to the comparison signal and an output connected to an input of the ring oscillator. Even when the output of the comparator varies frequently, such as when an output voltage closely approaches a set voltage, the ON period of the output transistor remains stable.

Abstract: A method for characterizing a change in delay induced by a switching history of a circuit includes the steps of generating a first signal having a pulse width that is selectively adjustable, the first signal having a first edge and a second edge associated therewith, the first and second edges being opposite in polarity with respect to one another; generating a second signal having a first switch delay characteristic of the first edge of the first signal and a second switch delay characteristic of the second edge of the first signal, wherein the pulse width of the first signal is less than the first switch delay associated with the second signal; varying the pulse width of the first signal; monitoring the second signal; determining a value of the pulse width that defines a boundary of when the second signal is present and when the second signal is not present; and determining a ratio of the value of the pulse width that defines the boundary to the first switch delay and/or the second switch delay, whereby the

Abstract: A system and method for providing synchronous clocking allows for precise control of the phase relationship of the clocking signals to thereby provide accurate duty cycles for proper system operation. A digital logic circuit, such as a D-type flip-flop, is provided with a phase signal and clock signal having a frequency relationship. The output of the digital logic circuit is a function of the phase signal and clock signal. The synchronous output may be provided to multiple locations within a system to allow for a synchronous local clock in each of the locations.

Abstract: An apparatus and method for providing an input signal having a desired pulse width and amplitude to atomic force miscoscopes (AFMs) for use in nano-lithography are provided. An input signal providing apparatus for a contact type AFM includes: a pulse width adjusting unit which adjusts the width of a positive pulse of an input square wave to a predetermined pulse width; and an amplitude adjusting unit which adjusts the amplitude of the positive pulse of the square wave to a predetermined voltage. An input signal providing method for the contact type AFM uses the apparatus having this structure. An input signal providing apparatus for a non-contact type AFM further includes a square pulse generating unit which generates a square pulse having a predetermined phase in synchronization with an input resonance signal, and an input signal providing method for the non-contact type AFM further involves generating the square pulse having a predetermined phase in synchronization with the input resonance signal.

Abstract: A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The circuit combines groups of set and reset signals. The edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap. This circuit allows for a low cost and low power CMOS implementation of an output signal formatter.

Abstract: A clock generating circuit of a semiconductor integrated circuit device includes a plurality of stages of frequency-dividing circuits connected in series, of which a first stage receives a reference clock signal, each frequency-dividing circuit requiring no reset signal; and a plurality of buffers respectively transmitting a reference clock signal and output clock signals of the plurality of frequency-dividing circuits to an internal circuit of the semiconductor integrated circuit device. Therefore, a plurality of clock signals having different frequencies with aligned edges can be generated without the need for separately providing an external pin for inputting the reset signal or a circuit for generating the reset signal.

Abstract: A programmable current reference circuit is described. The programmable current reference circuit includes a programmable resistance, where the programmable resistance is programmable to provide one of a plurality of resistances, where each of the plurality of resistances corresponds to one of a plurality of programmable current reference circuit outputs. In one embodiment, the programmable current reference circuit includes a current source coupled to the programmable resistance. In one embodiment, the plurality of programmable current reference circuit outputs includes a plurality of reference currents. A phase locked loop including the programmable current reference circuit is also described.

Abstract: In a clock squarer having a semiconductor chip pad and a square wave generating circuit, the clock squarer can generate a square wave having stable duty, irrespective of variation in temperature, process or supply voltage. In the clock squarer, a capacitor is provided between the chip pad and the square wave generating circuit. The clock squarer in accordance with the present invention is especially applicable to processes that involve high leakage current or a fabrication process for products requiring high-speed operation.

Abstract: A method for driving a plurality of circuit units to be controlled includes applying a control signal to a control signal connection unit and an activation signal to an activation connection unit. A hold signal is the generated on the in response to the activation signal. This hold signal is combined with the control signal to obtain a modified control signal, which is then made available at an output.

Abstract: A duty cycle correction circuit is provided for converting a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction circuit includes a first differential-to-single-ended buffer circuit, a second differential-to-single-ended buffer circuit, a first frequency divider, a second frequency divider and a symmetrical exclusive OR element. The first and the second differential-to-single-ended buffer circuits are used for processing the pair of differential analog signals into a first and a second digital pulse signals, respectively. The first and the second frequency dividers are employed for frequency-dividing the first and the digital pulse signal into a third and a fourth digital pulse signal, respectively. The symmetrical exclusive OR element is used for performing an exclusive OR operation so as to produce the output pulse signal.

Abstract: A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.

Abstract: A one-shot circuit provides a pulse on receipt of a first edge, and removes the pulse after a delay generated by a delay chain. However, a second, opposite edge resets the circuit without an intervening delay chain delay. The delay chain can be implemented using a chain of AND circuits (one-shot high) or OR circuits (one-shot low), each driven by the preceding circuit in the chain and by the input signal. In some embodiments, an output circuit includes a pass gate coupled between the one-shot input and output terminals and a pulldown (one-shot high) or pullup (one-shot low) that provides an inactive value when the pulse is not being applied. The pass gate and pullup or pulldown are controlled by the output of the daisy chain. Other embodiments offer programmable capabilities, such as the ability to correct for process shift by altering the effective delay of the delay chain.

Abstract: A current controlled oscillator is described comprising: a latch comprising two logic inverters to maintain a switch state for a determined duration, the latch having two complementary output voltages; a differential switch pair comprising a first and a second switch controlled by the two complementary output voltages respectively to steer a control current to a first and a second node alternatively; a third and fourth switch driven on by a high level voltage at one of the first and second node to set and reset the latch; and a fifth and sixth switch controlled by the two complementary output voltages respectively to pull down voltages at the first and second node alternatively, wherein the first and fifth switch are controlled by a same control signal and the second and sixth switch are controlled by a same control signal; whereby the frequency of switching is a function of the capacitance of the first and second node and the control current.

Abstract: A generating a digital wave apparatus is provided. The period of a basic clock signal is divided into a plurality of time points, and the level of the highly accurate digital wave is toggled at these time points. The apparatus comprises a delay phase lock loop, for generating a plurality of delayed clock signals according to the basic clock signal; a first multiplexer and a second multiplexer for outputting one of the delayed clock signals according to a first select signal and a second select signal, respectively; a first edge-triggered flip-flop and a second edge-triggered flip-flop for receiving the output signals of the first multiplexer and the second multiplexer respectively; and a logic gate for outputting the digital wave according to the outputs of the first and the second edge-triggered flip-flops. The digital wave is toggled according to the first select signal, and further toggled according to the second select signal.

Abstract: Two synchronizing flip-flops synchronize the transitions of a slow clock to a fast clock. The state of a version of the synchronized slow clock is stored by a last-state flip-flop that is clocked on an edge of the fast clock. The last-state flip-flop is compared by logic to a version of the synchronized slow clock to produce a pulse with a width determined by either a phase of the fast clock or a cycle of the fast clock.

Abstract: The present invention provides a mechanism for combining programming signals to provide an output signal, the properties of which depend only on selected properties of the programming signals. An embodiment of the invention includes first and second edge-to-pulse converters. The first edge-to-pulse converter generates an intermediate signal having a width determined by received initiation and termination signals. The second edge-to-pulse converter generates an output signal, responsive to the intermediate signal and the termination signal. The output signal has a width determined by a first edge of the initiation signal and a first edge of the termination signal.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: A clock signal correction circuit which corrects duty cycle distortions of a clock signal in a simple and accurate way. A frequency divider divides the frequency of a given input clock signal by a natural number n, thereby producing a divided clock signal. The phase of this divided clock signal is identified by a phase detector. By adding an appropriate delay to the divided clock signal according to the identified signal phase, a delay unit produces a delayed divided clock signal. A logical operator creates an output clock signal by performing a logical operation on the original divided clock signal and the delayed divided clock signal.

Abstract: A duty-cycle regulation method for deriving an output clock signal having a predetermined duty cycle from an input clock signal having an arbitrary duty cycle. Once the input clock signal is received, an output clock storage element is switched to a first state upon detecting a transition in the input clock signal for driving the output clock signal to a first signal level. The output clock storage element is then switched to a second state after a delay interval equal to a fraction of the period for driving the output clock signal to a second signal level. The fraction of the period can be programmed to a pre-selected value.

Abstract: A circuit for limiting loss in a second circuit. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reaches a first predetermined amount of time, where the first predetermined amount of time is related to a parameter of the second circuit. The second timer may produce a second output in the given state if the first timer does not produce the first output in the given state when the duration of the pulse reaches a second predetermined amount of time. The one or more logic gates may have an output that is the same as the pulse unless and until the output of the first timer or the second timer is in the given state, at which time, the output of the one or more logic gates is forced to a non-pulsed state.

Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: A pulse-controlled analog flip-flop includes a charge element; a charge storage element connected to the charge element; an element for detecting the voltage across the storage element; and an element for discharging the storage element when the detection element has detected that the voltage across the storage element has reached a predetermined threshold.

Abstract: A circuit to synchronously select one of the multiple clocks is presented. In one embodiment the selection circuit consists of four main blocks. These are the stable selects block, the decoder block, the synchronous selects block, and the output block. The stable selects block takes select signals as inputs and outputs a signal indicating whether the selects are stable or not, in addition to producing select signals that are synchronous to the current selected clock. The decoder block, decodes the select signals if they are stable, otherwise it re-circulates the previous values of the decoded clock select signals. The stable decoded select signals are then passed on to the synchronous selects block. This block outputs select signals in synchrony with their respective clocks. The synchronous select signals along with the stable decoded signals are used in the output block along with the clocks themselves to generate the final output clock.

Abstract: An apparatus and method for providing a gated output timing signal within a gated clock distribution tree. In accordance with the present invention, a gated clock splitter includes a timing signal input and a combinatorial logic block coupled to the timing signal input that generates a gated timing signal. A gating signal input is coupled to the combinatorial logic block for selectively enabling and disabling the output from the combinatorial logic block. A gate control circuit is coupled to the gating signal input for providing a gate signal to the combinatorial logic block, wherein the gate control circuit provides a full-cycle path for said gate signal to the gating signal input.

Abstract: A single event effect immune oscillator circuit is disclosed. The single event upset immune oscillator circuit includes an odd number of logic circuit blocks connecting in series to provide a continuous pulse signal at an output of the oscillator circuit. Each logic circuit block has a first input, a second input, and an output. For a series of logic circuit blocks i, where i=1 to n (n is an odd number), the output of a logic circuit block i is connected to a first input of a logic circuit block i+1. The output of the logic circuit block i is also connected to a first input of a logic circuit block i+x, wherein x is an odd number greater than one and less than or equal to n.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: A power-on circuit and a resetting method by which resetting of a circuit through which flows direct current upon resetting can be achieved stable state without causing a large current to flow in the circuit. For resetting a circuit through which flows the direct current at the time of resetting, such as a circuit for resetting a fuse on power source on, there is provided a power-on circuit generating a one-shot signal on power source on, in which two or more one-shot signals are provided and resetting is carried out by at least two partial operations to achieve stable resetting without flowing a larger current.

Abstract: A digital clock throttling device, for gating a clock signal of a circuit, at least includes an accumulator and a gating circuit. The accumulator responsive to a throttling value generates a first output signal. The first output signal is divided into a throttling signal with a most significant bit and a feedback signal with rest bits of the first output signal except for the most significant bit. The feedback signal is sent to the accumulator back for accumulating to the throttling value as the first output signal. The gating circuit coupling with the accumulator responsive to the throttling signal and clock signal gates out some clock cycles of the clock signal, thereby providing a gated clock signal in an adjusted frequency.

Abstract: The present invention discloses a floating body architecture CMOSFET inverter with body biasing inverters added for controlling the delay time of the inverter. At least one body biasing inverter is connected between the main inverter's input and the body terminals of the FETs of the inverter. By supplying a representation of the input voltage to the body terminals of the p-channel and n-channel FETs, the preferred embodiment of the present invention is able to control the history dependent delay time associated with the variable source-to-body voltages in floating body CMOSFET inverters. The delay time is minimized by adding an odd number of body biasing inverter stages into the main inverter circuit. The delay time can also be maximized by adding an even number of body biasing inverter stages into the circuit.

Abstract: Even if duty is shifted to either a state in which an “H” period is long or a state in which an “L” period is long, the duty is recovered to about 50%. A duty correction circuit corrects a duty shift or deviation developed when analog complementary cycle signals having a phase difference of about half cycle therebetween and a duty ratio of about 50% are converted to logic levels, through the use of, for example, serial two-stage NAND gate static latches.

Abstract: A circuit for generating a clock signal is provided. The circuit includes a flip-flop having a first input and a second input. The flip-flop is operable to generate a first output signal and a second output signal. The circuit also includes a first delay chain and a second delay chain. The first delay chain is operable to receive the first output signal and generate a first delayed signal. The first delayed signal is then received by the first input of said flip-flop. The second delay chain is operable to receive the second output signal and generate a second delayed signal. The second delayed signal is then received by the second input of said flip-flop.

Abstract: A control method and system are used for signal transmission when a data signal is transmitted between two circuits on the basis of a reference clock in a system. The sending side circuit transmits a clock signal together with the data signal to a clock transmission line of the same course with a data transmission line for the data signal by using a sender side reference clock. The receiving side circuit adjusts phases of the clock signal and the data signal at input points of transmission lines respectively so as to be in accordance with a receiver side reference clock. Then the receiving side circuit reads out data from an adjusted data signal by using an adjusted clock obtained by above the aforementioned adjusting step. The adjustment is performed comparing a phase of an adjusted clock with a phase of the receiver side reference clock. The second adjustment involves generating a feedback clock signal including a phase difference between the above signals.

Abstract: A method and apparatus for generating a timing signal for a semiconductor device, wherein the timing of rising and falling edges in the timing signal can be very precisely controlled. In one embodiment, a serial data stream derived from data stored in a memory device is applied to the inputs of first and second programmable delay elements each adapted to introduce a delay into the serial data stream. The resulting first delayed serial data stream is applied to the SET input of a flip-flop circuit; the resulting second delayed serial data stream is applied to the RESET input of the flip-flop. The output of the flip-flop constitutes the generated timing signal. The rising and falling edges of the timing signal are controlled through manipulation of the lengths of the delays introduced by the first and second delay elements into the serial data stream. Manipulation of the delay times is accomplished through adjustment of analog programming voltages applied to the respective delay elements.

Abstract: A duty cycle regulator derives from an input clock of arbitrary duty cycle an output clock having an adjustable duty cycle of similar frequency. The duty cycle regulator includes a bistable circuit for receiving an input clock pulse and providing the output clock, coupled through a feedback loop to an adjustable delay unit having a delay interval equal to an adjustable fraction of the input clock period. When an input clock pulse is received, the bistable circuit is set giving high signal to the delay unit, which after the delay interval resets the bistable circuit to give a low signal. The delay unit includes two charge pumps alternately feeding and draining electric charges into and from a low-pass filter. The delay interval can be adjusted to a desired duty cycle independent of the input clock frequency, by setting the ratio of electric currents through the two charge pumps.

Abstract: A variable delay circuit has a positive logic variable delay circuit which delays an edge of a signal which is input through an input terminal and a negative logic variable delay circuit which delays an edge of the signal input through an input terminal. Only an edge delayed in accordance with the set time is extracted from all the edges of a signal supplied from the positive logic variable delay circuit and all the edges of a signal supplied from the negative logic variable delay circuit in an extracting circuit of the variable delay circuit.

Abstract: A clock monitor circuit includes a first and second delay and clock signal generating unit for receiving a clock signal and an inverted clock signal, respectively. The first and second delay and clock signal generating units generate a first and second signals, respectively. A logic sum unit logically-sums the first and second signals to generate a stop clock signal. The clock monitor circuit according to the present invention can monitor the presence of a clock signal irrespective of an operation cycle of the clock signal. Further, the synchronous semiconductor memory device utilizing the clock monitor circuit according to the present invention is adapted to consume electric current only when a clock signal is present. That is, the device does not consume electric current when the clock signal is not present thereby reducing unnecessary waste of electric power in the stand-by mode.

Abstract: A duty cycle correction circuit and method that accept an unsymmetrical input clock signal and provide therefrom an output clock signal having a 50% duty cycle. One circuit according to the invention includes an input clock terminal supplying a input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that is most nearly 180 degrees offset from the input clock signal. The selected clock signal is then combined with the input clock signal in an output clock generator to generate an output clock signal having a 50% duty cycle. In one embodiment, the duty cycle correction circuit includes a delay stage comprising a delay element that can selectively add a half-unit delay to the input clock signal.

Abstract: A pulse duration changer generates an output pulse signal longer in pulse duration than an input pulse signal, wherein the pulse duration changer firstly produces a first control pulse signal synchronous with the input pulse signal and shorter in pulse duration than the input pulse signal, thereafter, produces a second control pulse signal synchronous with the first control pulse signal and longer in pulse duration than the input pulse signal, and finally defines the pulse duration of a preliminary output pulse signal as long as the second control pulse signal, thereby keeping the pulse duration of the output signal constant when the input pulse signal has an ultra high frequency.

Abstract: To prevent a deadlock in a latch circuit for deciding an input state of an SDA terminal in a system initialization state. An input/output control circuit 5 for always determining a data state in the system initialization state is provided.

Abstract: A circuit arrangement for generating an output signal at an output by combining at least a first and a second input signal, includes controllable switches for applying a respective one of the input signals to the output, in which, for the purpose of switching the output from one of the input signals to the other, a first one of the controllable switches is gradually switched from the blocked to the conducting state and a second one of the controllable switches is switched complementarily thereto from the conducting to the blocked state. To implement such a circuit arrangement in such a way that distortions produced by tolerances and inaccuracies in matching the characteristics of the components used for switching can be avoided, while using a small number of components, the controllable switches are switched oppositely to each other between their completely conducting and their completely blocked state with a mutually complementary, gradually changed duty cycle.

Abstract: When a sub-clock signal is generated in synchronization with an external main clock signal from the main clock signal and its inverted delay signal, the signal width of the sub-clock signal is constant even when the high level or the low level of the main clock signal is shorter than the inverted delay time. A holding 20 circuit is provided so that a high level time period of the system clock signal CLK1 is extended beyond the delay time of the delay circuit 30. A complex gate including OR gates 25 and 27 is provided in a delay gate chain of a non-inversion in the holding circuit. If the high level width of the main clock signal CLK1 is not less than a time corresponding to four stages of the NAND gates 21 to 22, it is possible to extend the high level width of the gate chain output signal S28 to a time corresponding to twelve stages. A complex gate including NAND gates 31 and 32 is provided in the gate chain of the delay circuit 30 for the inversion and delay.

Abstract: A single large register increments ticks of a high-speed clock. A single compare register is associated with the clock register, the compare register preferably being of equivalent length to the clock register. Successive previously-stored timing values are then loaded into the compare register. Typically the timing values are pre-sorted in chronological order. A comparator monitors the clock register's current value and compares it with the timing value currently loaded in the compare register. As the clock register's value reaches the current timing value in the compare register, an alert signal is generated and sent out to activate a particular timed operation identified by an event ID (“EID”) associated with the timing value in the compare register. The current timing value in the compare register is then discarded, and the next timing value in sequence is retrieved into the compare register. In a first embodiment, timing values are stored in a hardware stack.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: A duty cycle control circuit that consumes lower power and smaller silicon area, and is less susceptible to noise or jitter. In one embodiment, the invention includes a divide-by-two circuit that is edge triggered and generates a signal at its output with half the frequency of the input signal but with a 50% duty cycle. The divide-by-two circuit is followed by a frequency restore circuit that restores the original frequency of the input signal but with its duty cycle regulated at about 50%, or any other desired level.

Abstract: A timing circuit can be selectively configured to generate output pulses in response to either the falling edges or the rising edges of an input signal. The timing circuit includes a multiplexer, an output pulse width controller (OPWC), a gating circuit (GC) and a latch circuit. The OPWC includes a delay circuit that can be configured to provide a predetermined delay .delta. that can be larger than the pulse width of the input signal pulses. The multiplexer is connected to receive a first input signal and an inverted version of a second input signal. The first input signal is used in a rising edge triggered mode, whereas the second input signal is used in a falling edge triggered mode. The multiplexer receives a mode signal to selectively output one of the input signals to the GC. The GC is also connected to receive the output signal from the OPWC.

Abstract: A pulse width control system, to control an output pulse width on a pulse output circuit to be a predetermined value, including a first circuit outputting a pulse output signal corresponding to an input pulse, a second circuit for detecting a phase difference between an input data pulse and the pulse output signal, and a third circuit receiving the input data pulse and outputting the input pulse as a signal based on the input data pulse, wherein a pulse width of the input pulse varies based on the detected phase difference.

Abstract: A circuit and method comprising (a) a first circuit configured to generate an output signal having a variable pulse width in response to an (i) input signal and (ii) a control signal and (b) a second circuit configured to generate the control signal in response to (i) the input signal and (ii) a test input. In one example, the first circuit may comprise a register configured to present the output signal and an edge detection circuit configured to present a second control signal to said second circuit. In another example, the second circuit may comprise a plurality of first gates that may generate the output signal in further response to the second control signal.