Abstract: There is disclosed a synchronizing pulse generating circuit wherein a synchronization lack correcting portion (600) processes a synchronizing signal (S601) to provide a corrected synchronizing signal (S600), and a synchronizing clock generating portion (700) generates a synchronizing clock (S700) accurately synchronized with the corrected synchronizing signal (S600), and then a synchronizing pulse generating portion (800) counts the synchronizing clock (S700) to provide a synchronizing signal (S800) accurately synchronized with the synchronizing signal S601, whereby the synchronizing pulse generating circuit generates high-accuracy synchronizing pulses without exteriorly attached parts and is adapted for generation of HD pulses for use in a deflecting system of a multi-synchronization type display monitor.

Abstract: A sensor circuit is disclosed for use with a clock circuit providing a periodic timing signal to a clock output, wherein a timing reference for the periodic timing signal is provided by a crystal connected between a crystal input and a crystal output of the clock circuit, or alternatively provided by an external periodic logic signal coupled to the crystal input. The sensor circuit provides a sensor output in a first state, thereby indicating the presence of an external periodic logic signal timing reference, in response to at least a given number of large-signal voltage transitions on the crystal input within a certain period of time, and otherwise provides a second state on the sensor output, typically to indicate the presence of a crystal timing reference. Also disclosed is a clock circuit including a sensor circuit, and further including means for disabling a feedback resistor necessary for crystal operation when the timing reference is determined to be provided by an external periodic logic signal.

Abstract: A pulse detection circuit detects one different pulse within a string of similar pulses for a once per revolution index. The pulse detection circuit comprises a DC averaging means for generating a first threshold voltage from a raw signal. An average comparator receives the first threshold voltage and generates a first output voltage indicative of signal amplitude of the raw signal, as compared to the first threshold voltage. A zero comparator receives the raw signal, compares it to zero, and generates a second output voltage indicative of a pulse. The first and second output voltages are input to a logic sequence to generate a logic output when the one different pulse within the string of similar pulses is detected.

Abstract: A time of arrival detector for an analog pulse signal digitizes the pulse, digitally delays the digitized signal in one path and converts the delayed signal back to a delayed analog version of the input signal. In a second path an undelayed analog version of the input signal is provided. A scaling offset is established to scale the delayed signal larger than the undelayed signal, and the delayed and undelayed signals are then compared to establish a time of arrival for the input pulse. A delta modulator is preferably used to provide the digitized signal, and also to provide the undelayed analog version of the input signal as the smoothed output of an integrator within the delta modulator. The undelayed modulator output is preferably attenuated by -3 dB, with the pulse's time of arrival obtained from the time at which the delayed analog signal rises above the undelayed but attenuated signal.