Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and/SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and/SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against/SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and/SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and/SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A device which reduces jitter and narrows the frequency spectrum of a jitter-ridden clock signal includes a basic unit having a plurality of series connected delay elements outputs from each delay element are all connected to an AND/NAND gate. A front end of the device locates missing clock pulses and ensures regular clock pulses are relayed to the remainder of the device. A succeeding section including plural basic units hones the signal such that jitter elements are removed. By the output of this section time duty cycles are uneven, a positive edge triggered flip-flop is then used to obtain 50% duty cycles at the expense of halving the clock signal's frequency. Optionally a frequency doubler can be employed to regain the clock signal's original frequency.

Abstract: An improved pulse detection circuit provides for a reduced delay response and noise immunity. The pulse detection circuit includes a comparator with a biasing circuit providing first and second biasing signal states. The biasing signal states are adjustably delayed relative to the detected signal.

Abstract: A circuit arrangement for monitoring a load operated with a clock signal is provided. The circuit arrangement may be applied to the field of automotive engineering. The circuit arrangement includes a comparator having at least two inputs and one output. The circuit arrangement further includes a D-flip-flop having one clock input, one signal input, and one output. At least a first input of the comparator is coupled to the load signal. The output of the comparator is coupled to the signal input of the D-flip-flop. The clock input of the D-flip-flop is coupled to the clock signal. The output of the D-flip-flop delivers a monitoring signal.

Abstract: A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current" power consumption when docks to the logic circuit are stopped, and allows the circuit to be powered down when idle. The system includes a circuit for forcing clock phases to an active state, a circuit for breaking feedback paths within the logic circuit, and an optional clock loss detector for detecting clock inactivity and automatically initiating the static mode.

Abstract: An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.

Abstract: The electronic circuit contains dual edge triggered flip-flop, which loads data on both the rising edge and the falling edge of a clock signal. The clock signal is supplied by a clock supply circuit with an enable input and a source input for receiving a source signal. The clock supply circuit toggles the clock signal as from an earliest available edge of the source signal after the enable signal at the enable input switches to an active state, irrespective of a polarity of said earliest available edge.

Abstract: A circuit and method for generating an evaluation signal used to turn OFF one or more sense amplifiers. The sense amplifiers may be configured to present a first and second output in response to (i) an input signal and (ii) an enable signal. A detect circuit may be configured to present a detect signal in response to the first and second outputs. A control circuit may be configured to present the enable signal in response to (i) the detect signal and (ii) a wordline signal.

Abstract: The invention relates to apparatus for detecting the presence or the absence of a signal carrier wave received by a receiver. The carrier wave is modulated by a digital signal at a symbol clock frequency. According to the invention, the apparatus includes:a non-linear circuit receiving the received signal or the received signal after it has been frequency transposed, the non-linear circuit supplying in particular a signal whose frequency corresponds to the symbol clock frequency;a narrow-band filter centered on the symbol clock frequency and supplying a filtered signal;detection means for detecting the filtered signal and for supplying a detection signal; andcomparator means for comparing the detection signal with a reference value, the output signal from the comparator means constituting a signal indicating the presence or the absence of the carrier wave.

Abstract: An address transition detection summation circuit is provided that selectively maintains an input voltage of a pull-up circuit at an intermediate level during a pull-up time. The address transition detection summation circuit includes a pull-up circuit and an address transition detection summation unit for summing a plurality of ATD signals. A delay unit delays an address transition detection summation node signal and can determine a pulse width of the address transition detection summation signal. An input signal generation unit can maintain the input level of the pull-up circuit at an intermediate level. Thus, although a short pulse ATD signal or a standard pulse ATD signal is inputted, a width of an address transition detection summation signal is made as wide as the ATD signal. Thus, the address transition detection summation signal more rapidly responds to the short pulse, which can prevent a failure of a chip operation.

Abstract: An input signal reading circuit includes an up-down counter receiving an input signal and a sampling clock to count up the samplig clock when the input signal is at a high level and to count down the sampling clock when the input signal is at a low level. The up-down counter outputs an underflow signal when a count value of the up-down counter becomes zero. A comparator compares the count value of the up-down counter with a reference value held in a register, to generate a coincidence signal when the count value of the up-down counter becomes coincident with the reference value. A RS flipflop is set by the coincidence signal to bring the read-out signal into a high level, and is reset by the underflow signal to bring the read-out signal into a low level.

Abstract: A transmission line sampling circuit for a T1 line is disclosed. A multi phase oscillator is connected to a plurality of state machines which are connected in parallel to a transmission line. The use of a plurality of state machines to sample the transmission line effectively increases the sample rate of the transmission line beyond that which can ordinarily be supported by a single phase oscillator running at the same frequency of the multi phase oscillator. The outputs of the plurality of state machines are provided to an arbitrator and to a MUX wherein the arbitrator decides which of the four state machines outputs should be switched through the MUX and produced transmitted on an output line.

Abstract: This invention relates to a digital circuit for controlling the power usage of an electronic device such as a read only memory (ROM) for a computer device, particularly a portable computer device that relies on a battery power source. The circuit includes the latch, a positive edge detecting circuit, a negative edge detecting circuit, a guaranteed reset circuit, and a delay circuit. Control signals from the device open and close the latch when either a rising or falling edge of these control signals is detected by the edge detecting circuits. The latch itself includes a three input NAND gate and a two input NAND gate. The guaranteed reset circuit ensures that the circuit is initiated. The delay circuit includes a series of inverters and loads. The edge detecting circuits generate a pulse when a rising or falling edge is detected, and include a pulse generating portion, a NAND gate and inverters.

Abstract: An input signal variation detection circuit effectively detects transitions of input signals from a memory apparatus. The circuit includes a plurality of unit blocks for detecting transitions of input signals and for outputting transition detection signals corresponding to the transition direction, e.g., from high to low level or from low to high level, a first transistor having a drain coupled for receiving a transition detection signal from the unit blocks, a gate coupled for receiving a first prescribed voltage, and a source coupled for receiving a second prescribed voltage, and an OR-gate for ORing a transition detection signal from the unit blocks and outputting a summation signal.

Abstract: A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.

Abstract: An interpolating process is performed on an input periodic signal using at least one first circuit board and a second board. Each first circuit board includes a partial circuit for performing the interpolating process. A plurality of these first boards can be mounted on the second board, and a divisional number of the interpolating process can be selected in accordance with the number of first boards mounted on the second board.

Abstract: The drain electrodes of HNMOS transistors (2) and (3) are connected to the first ends of resistors (4) and (5), and to the inputs of inverter circuits (6) and (7) respectively. The outputs of the inverter circuits (6) and (7) are connected to the inputs of a protection circuit (27). The outputs of the protection circuit (27) are connected to the set and reset inputs of a flip-flop circuit (10A). The protection circuit (27) serves to prevent the malfunction of the flip-flop circuit (10A) from occurring and is formed by a logic gate. Having this configuration high potential side power device driving circuit is provided wherein the pulse widths of signals input to the gate electrodes of transistors for level shift can be set optionally, the lag time of the signal is not caused by a passage through a filter circuit, and the malfunction of a flip-flop circuit can be prevented from occurring due to a dv/dt current without lowering the response performance of a power device.

Abstract: There is disclosed a pulse-width controller which includes a first pulse-width adjusting section which adjusts the pulse width of a main pulse signal, a second pulse-width adjusting section which adjusts the pulse width of a reference pulse signal, a pulse-width measurement section which measures the pulse width of the reference pulse signal adjusted by the second pulse-width adjusting section, a target pulse-width setting section for setting a target pulse width to be achieved by the first pulse-width adjusting section, and a control section which outputs to the first pulse-width adjusting section a control signal for use in adjusting the pulse width of the main pulse signal in the first pulse-width adjusting section, on the basis of pulse-width information regarding the reference pulse signal measured in the pulse-width measurement section and the target pulse-width information set by the target pulse-width setting section.

Abstract: A switch open-close state-detecting circuit for supplying an interrupt signal to a control terminal of a controller in response to a change of state of a switch to either open or closed state by giving a monitoring voltage to a plurality of switches to supply a change of the monitoring voltage corresponding to opening or closing of the switches to a plurality of input terminals of the controller by detecting the change of the monitoring voltage to supply to the control terminal of the controller for controlling the operation modes of the controller. The switch open-close state-detecting circuit has a control IC including the same number of a plurality of pairs of input terminal and a plurality of output terminals for generating interrupt signals at the output terminals only when supply voltages to pairs of input terminals of the control IC are not equal, and delay circuits connected between the input terminals of the control IC.

Abstract: A circuit for detecting delay of more than a set period of time from a last signal transition for any of a plurality of data signals, comprising a differential comparator, and integrator pairs for each signal, one integrator of the pair being triggered by transition of the signal from low to high and the other triggered by transition of the inverse of the signal from low to high, each integrator having a voltage measured by the differential comparator against a reference voltage, each integrator being reset by the trigger for the other integrator.

Abstract: The alarm circuit uses speed detection so that at a fan slowdown speed below a critical low level, a buzzer alarm starts sounding at a low warning volume and then as the fan slows down further the volume increases; that is, the buzzer volume or the buzzing frequency is inversely proportional to the fan speed. The circuit advantageously can be used for a wide range of fans. A pulse detector of a first stage comparator of this circuit detects the pulses or speed of the fan. More particularly, a power supply isolation resistor with an AC coupling capacitor block the DC voltage levels at the fan so that only the AC or pulse component of the fan is picked up. The isolation resistor prevents the power source from attenuating the pulses. The second stage comparator of the circuit sets the fan speed at which the alarm is to start buzzing and powers the buzzer accordingly. Particularly, the pulses are amplified by the first stage comparator and they periodically discharge a charging capacitor.

Abstract: A power semiconductor device (2) has a first main electrode (S) for coupling to a first supply line (3), a second main electrode (D) coupled to a first terminal (4) for connection via a load (L) to a second voltage supply line (5) and an insulated gate electrode (G) coupled to a control terminal (GT) for supplying a gate control signal to enable conduction of the power semiconductor device (2). An open-circuit detection arrangement is integrated with the power semiconductor device (2) for providing an indication that a load (L) coupled to the power semiconductor device (2) is open-circuited. The detection arrangement has a reference current (Ir) providing arrangement (7, R3, R4, R7, Q1, Q2) and a current deriving arrangement (Q3, Q4) for deriving a current (Id) dependent on the voltage at the second main electrode (D).

Abstract: In an input signal determining method and an apparatus for practicing the method, the level of an input signal is detected at least twice with a predetermined period, if the level of the input signal is significant when detected firstly, then before the second detection is started which is carried out in the predetermined period, whether or not the input signal is a continuous input signal whose level is maintained unchanged for a predetermined time is determined, and if the input signal is not the continuous input signal, the result of the first detection is reset, and if the level of the input signal is maintained for the predetermined time, and the level of the input signal is significant when detected secondly, then the input signal is determined as a correct input signal, whereby the erroneous recognition of the input signal can be avoided, and a noise equal in period to the synchronizing signal can be eliminated.

Abstract: A pulse detection circuit to be used in combination with a generator of a train of synchronizing pulses. The detection circuitry remains in a first, inactive state in the presence of an ongoing sequence of synchronization pulses. In the event of a detected absence of synchronizing pulses for a predetermined period of time, the detection circuitry changes state and generates an electrical output signal indicative of one or more missing synchronizing pulses. The detection circuitry can incorporate either digital or analog timing circuitry.

Abstract: A waveform shaping apparatus includes a comparing device for comparing a sensor output signal with a threshold voltage to convert the sensor output signal into a waveform shaped signal. The comparing device outputs the waveform shaped signal. The waveform shaping apparatus also includes a frequency-to-voltage converting device for generating the threshold voltage in response to a frequency of the output signal from the comparing device. In the frequency-to-voltage converting device, a clock signal is generated in response to the output signal from the comparing device. The clock signal has a period proportional to a period of the output signal from the comparing device. A counting device is operative for counting pulses in the clock signal generated by the clock signal generating device for every given period, and outputting a signal representing a counted pulse number depending on the frequency of the output signal from the comparing device.

Abstract: A transmission line sampling circuit for a T1 line is disclosed. A multi phase oscillator is connected to a plurality of state machines which are connected in parallel to a transmission line. The use of a plurality of state machines to sample the transmission line effectively increases the sample rate of the transmission line beyond that which can ordinarily be supported by a single phase oscillator running at the same frequency of the multi phase oscillator. The outputs of the plurality of state machines are provided to an arbitrator and to a MUX wherein the arbitrator decides which of the four state machines outputs should be switched through the MUX and produced transmitted on an output line.

Abstract: To increase compatibility, a method is used to determine whether a bidirectional or a unidirectional data line circuit is connected to an interface circuit. A first logic level is generated on a non dedicated lead of the interface circuit if a bidirectional data line circuit is connected to the interface circuit. Otherwise, a second logic level is generated on the non dedicated lead of the interface circuit. The logic level on the non dedicated lead after a reset signal determines which type of data line circuit is connected to the interface circuit. Typically the non dedicated lead is a data line lead of the interface circuit and can be used for normal data transfer, if necessary, after detecting which type of data line circuit is connected to the interface circuit.

Abstract: A Doppler velocimeter determines a state of noise generation in a detection signal including a Doppler signal component based on comparison by a preceding/succeeding-signal comparator for comparing the detection signals before and after passing through a band-pass filter for cutting noise adjusted to the frequency of the detection signal, and/or includes a filter circuit for determining passage/interruption of the detection signal after passing through the band-pass filter from a relationship between the count value of a first counter, in which the output of a first frequency multiplier for multiplying the frequency of the detection signal by N is made to be a clock signal and a leading edge in the detection signal is made to be a reset trigger, and a leading edge in the detection signal, and/or includes an error signal generator for generating an error detection signal by detecting a periodic error in the detection signal after passing through the band-pass filter from a relationship between the count value

Abstract: A system for clamping a clock signal line that prevents clock glitching is disclosed. The system is comprised of a plurality of logic gates which generates a signal to clamp the clock signal line only on the occurrence of the clock signal line being low, a clock clamping signal 26 is generated indicating that a peripheral device wants to clamp the clock signal line, and a start condition is detected indicating that the clock signal line may be clamped.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: A pulse detecting system 1 has a high speed A/D converter 10 and a slew controlled pulse detector 110. The A/D converter 10 has large hysteresis for holding the converted digital value of an input signal V.sub.PULSE until the A/D converter 10 is reset. The slew controlled pulse detector 110 limits the slew rate of large amplitude pulse to correct arrival errors and provide an output signal V.sub.AT that more accurately represents the arrival time of the input pulse signal, V.sub.PULSE.

Abstract: A semiconductor apparatus includes a mode setting circuit with reduced power consumption to select one of a plurality of functions produced by the apparatus. The mode setting circuit includes a switching transistor to connect or disconnect a first latch circuit with a mode setting terminal to which a mode setting potential is applied. A reset transistor connected in series with the switching transistor resets the first latch circuit. A control signal such as a clock signal causes either the switching transistor or the reset transistor to conduct alternately. The control signal and the input and output signals of the first latch circuit are fed to the following stage that include another latch circuit to generate a mode setting signal. The mode setting signal is determined based on whether or not the mode setting terminal is connected to the mode setting potential.

Abstract: The present invention relates to an improvement to an address transition detection (ATD) circuit in an IC chip, a method related to the improved ATD circuit is also disclosed. The improved ATD circuit applies a transfer gate and a lot of inverters to construct a new ATD circuit. Not only reduces power dissipation while an address transition is detecting, but less consumption on transistors is achieved. Each time when the logic state of an input pin is switching, the improved ATD circuit generates an inverting phase signal based on the switching; next, a transfer gate generates a driving signal for waking up the chip from idleness; a delaying circuit then generates a regular time interval for the chip to operate the task indicated by the varied address. At the end of the regular time interval, the chip returns to idleness again to wait another job's coming.

Abstract: In an ATD circuit, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means generates a first output signal having a first pulse width in response to a change in external address signal and generates, when the external address signal becomes a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means receives therein the signal generated by the pulse width amplifier circuit and waveform-shapes the output signal so as to provide an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal generated by the first circuit means.

Abstract: A method and apparatus for detection of missing pulses from a repetitive pulse train including signal detection circuits for capturing the rising and/or falling edges of an input signal, time-stamping the captured edges, calculating the maximum and minimum instantaneous frequency over a specified time period, and displaying such frequency values. Instantaneous frequency values between any two adjacent edges are calculated based upon the time-stamps of the edges. The instantaneous frequency values in a specified time period are then sorted to find the minimum and maximum frequency values for that time period. These instantaneous frequency values are displayed in the form of a histogram evidencing the occurrence or lack of occurrence of missing pulses from the input signal.

Abstract: Internal node timing on an integrated circuit which is supplied with a clock signal from a system clock, the cycle time of which can be varied is measured by connecting a sequential element such as a latch to the node to measured and clocking it with a delayed measurement clock while increasing the clock cycle time. The output of the sequential element is an output pin of said integrated circuit. The measurement clock has the same cycle time as the system clock but has a latching edge delayed, the delay being at least 1.5 times the nominal system clock cycle time when it is desired to make measurement over both the high phase and low phase. The output pin is observed and the clock cycle time at which the sequential element fails to latch the current value determined. In a further embodiment, two sequential elements are used to make two measurements of this type and the difference between the two measurements is used to compute the time delay between the two nodes being measured. One node may be a clock node.

Abstract: The invention relates to a method and a circuit system for controlling an appliance used in lighting electronics, especially an electronic ballast or an electronic light controller included in a discharge lamp. An analog or digital type of signal for controlling the operation of an appliance to be controlled is connectable to a common control circuit and. The appliance to be controlled identifies the type of control signal and deciphers the contents of information received thereby on the basis of the signal type.

Abstract: A pulse-width-extension circuit for producing an output pulse signal whose pulse width is extended as compared with a pulse width of an input pulse signal when the pulse width of the input pulse signal is equal to or longer than a given width. The pulse-width-extension circuit produces no output pulse signal when the pulse width of the input pulse signal is shorter than the given width.

Abstract: A clock signal failure detection and recovery circuit for use in a system utilizing multiple, redundant clock signals. Multiple clock source circuits generate a clock signal and a periodic sync pulse, which in turn are manipulated to produce a clock signal present pulse and a periodic clock pulse. The periodic clock pulse associated with one clock signal will clock the circuitry which monitors a clock signal present pulse associated with a different clock signal. In this way, the absence of a clock signal present pulse can still be clocked into the monitoring circuitry when that particular clock signal has failed. Each clock signal present pulse is compared to at least two other clock signal present pulses, and upon recognition of a predetermined number of inconsistencies between the compared clock signal present pulses, a clock signal error signal will be issued.

Abstract: A timer comprised of first and second gated SR (set-reset) latches each including two pair (S1, S2 and R1, R2) of inputs and a pair of outputs (Q, QN), the Q output of the first latch being connected to the R2 input of the second latch, and the QN output of the first latch being connected to the S2 input of the second latch, the Q output of the second latch being connected to the S2 input of the first latch, and the QN output of the second latch being connected to the R2 input of the first latch, apparatus for applying a delayed representation of a first pulse signal to the S1 input of the first latch and apparatus for applying a delayed representation of a second pulse signal to the R1 input of the first latch, apparatus for applying an inverted representation of the pulse signal to the S1 input of the second latch and apparatus for applying an inverted representation of the second pulse signal to the R1 input of the second latch, whereby timed output signals representing a differential between leading edges

Abstract: An address transition signal detecting circuit includes a differentiator for receiving and differentiating an address input signal, and a pulse signal forming portion for receiving the signal differentiated in the differentiator to thereby form an address transition signal.

Abstract: A device which reshapes sinusoidal signals with a singularity to generate square-wave signals and detects the singularity in an unambiguous and reliable manner. The sinusoidal pulses are reshaped into square-wave pulses in such a way that the edges of the square-wave pulses always occur at the same location regardless of the height of the sinusoidal signal. This is achieved in that a change in the edges of the square-wave signals is initiated whenever the sinusoidal signal crosses the zero-axis. The required signal processing and logical comparisons, which also enable a definite detection of reference marks, are carried out in a suitable circuit arrangement.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: In a flag control circuit successively supplied with first and second input flag signals produced in relation to first and second results of calculations in an arithmetic and logic unit to produce a final output flag signal, the first input flag signal is latched by a primary flag signal latching circuit while the second input flag signal is latched by the secondary flag signal latching circuit. The first latched flag signal and the second latched flag signal are ANDed by an AND gate circuit to produce the final output flag signal.

Abstract: A frequency lock indicator (10) comprises a first delay (14), second delay (20), first sampler (24), second sampler (28), third sampler (32), fourth sampler (34), and lock indicator (36). The first delay (14) delays a rising edge of a frequency reference (12) which clocks the first sampler (24) on a rising edge and the third sampler (32) on a falling edge. The second delay (20) delays a rising edge of a feedback signal (18) to produce a delayed feedback signal (22) which clocks the second sampler (28) on a rising edge and the fourth sampler (34) on a falling edge. The first and third samplers sample an up-pump signal (26) and the second and fourth samplers sample a down-pump signal (30). The lock indicator (36) produces a lock indication signal (38) when the sampled up-pump signal substantially equal to the sampled down-pump signal.

Abstract: A method and apparatus is provided for varying the characteristics of an output signal of a current generator based on the impedance of a load to which the output signal is applied. The current generator contains first and second voltage inputs and outputs the output signal based on a voltage difference applied across the first and second voltage inputs. The first voltage input receives an externally applied input voltage, and the second voltage input receives the output of a comparator which has a negative input for inputting the external input voltage and a positive input for inputting the output voltage of the current generator. Based on the above configuration, if the load of the impedance is relatively small, the voltage of the output signal is less than the externally applied input voltage, and the comparator outputs zero volts to the second voltage input. Thus, the current value of the signal output by the current generator is dependent upon the external input voltage.

Abstract: An arbiter circuit for determining priority as between two or more competing request signals and applicable for use in a memory system having a number of memories operating independently without interfering with one another. For each of a number of memories, a receiving circuit 10(i) and an arbitration circuit 12(i) with standardized configurations are allotted. Common memory cycle clock pulse ARB-CLK is sent from memory cycle generator 16 to all of arbiter units 14(1)-14(N) . From the arbiter units 14(1)-14(N) , the commands for the respective memories are output in synchronization to each other based on memory cycle clock pulse ARB-CLK.

Abstract: A device detecting a sync signal is provided, which comprises a sync signal detector having an output selector, an internal clock generator and a combination of three current mirror circuits formed of MOS transistors, and two MOS transistors having resistance characteristics. Irrespective of the high and low state of the input clock signal, the selecting signal for selecting the received sync signal, is made to be high, and the discharge time of the capacitor is minimized so that a capacitor having small capacity can be used and the volume of an integrated circuit element can be minimized and the stable operation is performed, irrespective of the frequency band of the sync signal and the duty thereof.

Abstract: A self-resetting bypass control circuit is disclosed for use with scan testing of integrated circuits. The bypass control circuit includes a shift register and an OR gate. A test-enable signal is input to the shift register and to the OR gate, and the output of the shift register is also input to the OR gate. The output of the OR gate is a bypass signal that goes logic high immediately when the test enable signal goes logic high, that stays logic high while the test enable signal goes logic low momentarily, and that resets to logic low when the test enable signal goes logic low for an extended period of time.

Abstract: A floating detection circuit detects the floating state of an input node which can receive an externally applied DC input signal, and includes a pulse generator, a counter and a floating state discriminator. The pulse generator is coupled to the input node and supplies a pulse signal to the input node when the input node is in a floating state. The counter receives the pulse signal and counts the number of pulses included in the pulse signal during predetermined intervals. The floating state discriminator compares the number of pulses with a predetermined reference number, so as to produce a floating detection signal, wherein the floating detection signal indicates whether or not the input node is in a floating state. A semiconductor circuit includes this floating detection circuit and a DC level detector. The floating detection circuit included in the semiconductor circuit detects the input node state during a first period and produces the floating detection signal during a second period.