Abstract: A memory voltage monitoring circuit generates a low voltage detection signal when a power supply voltage drops below a memory contents holding voltage. A reset circuit generates a reset signal from an external reset signal and outputs the reset signal to the memory voltage monitoring circuit as an operation permission/no-permission signal. The memory voltage monitoring circuit operates while the reset signal shows operation permission.

Abstract: A semiconductor integrated circuit has an active mode and a sleep mode. The semiconductor integrated circuit is constructed by alternately connecting a plurality of combinational logic circuits and a plurality of flip-flops. The flip-flops include a retention flip-flop that is supplied with electric power and retains the data in the sleep mode, and a non-retention flip-flop that is not supplied with electric power during the sleep mode. The non-retention flip-flop includes an initializing circuit that initializes the non-retention flip-flop when the semiconductor integrated circuit is switched from the sleep mode to the active mode.

Abstract: An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

Abstract: A low-voltage detection reset circuit that suppresses a current consumption in a stand-by mode and is reduced in a size is offered. The low-voltage detection reset circuit is provided with a power-on reset circuit that operates only at power-on and outputs a reset pulse and is configured to set a detection level of a detection level setting circuit at a default value using the reset pulse and to activate a programmable low-voltage detection circuit. After the programmable low-voltage detection circuit is activated, a detection level of the programmable low-voltage detection circuit can be modified from the default value by a register.

Abstract: A power detection circuit has a first comparator block, a charge controller block, and a second comparator block. The first comparator block compares a supply voltage with a first threshold value, and the charge controller block controls the charging of a first capacitor according to an output signal of the first comparator block. The second comparator block compares the charge in the first capacitor with a second threshold value so as to produce a power detection signal, and wherein a second capacitor is interposed between the charge controller block and the first capacitor.

Abstract: A semiconductor integrated circuit device operates using a first power supply and a second power supply differing from the first power supply in voltage. The semiconductor integrated circuit device includes a first detecting circuit which detects that the first power supply has exceeded a specific voltage, a second detecting circuit which detects that the second power supply has exceeded a specific voltage, and a check circuit which checks the operating state of an analog circuit carrying out an analog operation using the first power supply and outputs a control signal indicating whether the analog circuit is operating properly. The detecting level of the first detecting circuit is determined on the basis of the control signal. A power-on reset signal is output according to the result of the detection at the first and second detecting circuits.

Abstract: The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.

Abstract: A power-on reset (“POR”) methodology and circuit for an electronic circuit using multiple supply voltage domains asserts a reset signal upon ramp up of the first supply voltage signal, maintains the reset signal until all of the supply voltage signals have ramped up, and de-asserts the reset signal after all of the supply voltage signals have ramped up. Practical embodiments of the POR circuit include a control circuit that reduces static and/or dynamic current leakage associated with the operation of the POR circuit.

Abstract: An initialization signal generating circuit includes a voltage distributor, a first initialization signal generator, a second initialization signal, and a controller. The voltage distributor outputs a voltage signal in response to an external voltage. The first initialization signal generator outputs a first initialization signal in response to the voltage signal output from the voltage distributor. The second initialization signal generator outputs a second initialization signal in response to the voltage signal output from the voltage distributor. The controller blocks the external voltage supplied to the voltage distributor and the first and second initialization signal generators, in response to the first and second initialization signals.

Abstract: A terminal state of a terminal 15 of a vehicle is enabled to be maintained for a minimum period of time even after a drop in the voltage supply. At the same time other loads are to have no effect on the holding time. A control device for controls access to a vehicle and has a voltage source, a voltage supply terminal to which a supply voltage can be applied, and a holding circuit to which the voltage source and the voltage supply terminal are connected in a common circuit point for the purpose of holding an On state for as long as the voltage at the voltage source does not fall below a predetermined value. A switching element that is connected into the circuit between the voltage supply terminal and the common circuit point serves to separate the common circuit point from the supply voltage. The holding time is thus decoupled from the VCC currents drawn by other loads.

Abstract: In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive the state from an output of the low leakage latch and to isolate the state. State restore circuitry is used to restore the state to the circuit when the circuit returns to an active mode. The state restore circuitry is used to receive the isolated state and to restore the state upon receipt of an active pulse.

Abstract: This power detection circuit is comprised of a power-down detection circuit for detecting the first detection level and a power-on detection circuit having the second detection level higher than the first detection level, and the power detection circuit compulsorily initializes a power-on latch circuit by the output signal lowlevelx of the power-down detection circuit and also initializes the power-down detection circuit and the power-on detection circuit by the switch of a starter circuit.

Abstract: A clock input circuit 13 receives power during standby mode and comprises a NAND circuit NAND0 that controls a clock signal CK using a standby mode signal RET. When the standby mode signal RET is at a low level (in standby mode) clock signals C01 and C02 are kept at a high level and low level respectively regardless of the level of the clock signal CK. Further, power continues to be supplied to an FA section in the clock input circuit 13 and to an FB section in a slave latch circuit 12 whereas the power supply to the other circuits is shut off. As a result, the clock signals C01 and C02 remain at the high level and low level respectively and data is held by a loop formed by an on-state transfer gate circuit TG4 and activated inverter circuits INV5 and INV6 in the slave latch circuit 12.

Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Abstract: An inhibit circuit which produces an inhibit signal when a variation in a power supply potential is detected includes a comparator having a negative input connected to a generator producing a reference potential and a positive input connected to an output of a first image circuit producing a first potential that is an image of the power supply potential. The first image circuit includes a diode and a circuit for the production of a reference current parallel-connected between a common point to which the power supply potential is applied and an output of the first image circuit connected to the positive input of the comparator. The circuit has particular utility in portable integrated circuits with very low consumption when idle such as in mobile telephony.

Abstract: There is provided a circuit and a method for generating a power up signal. The circuit for generating a power up signal, includes an external power voltage divider for dividing a magnitude of an external power voltage so as to output the divided voltage, an external power voltage detector for activating a detection signal when the output voltage of the external power voltage divider reaches a preset level, and a power up signal generator for outputting a power up signal according to the detection signal and a first internal power voltage. Herein, the power up signal is generated when the internal power voltage as well as the external power voltage reaches a sufficient level so that a power up signal skew may be reduced to stabilize its operation and enhance reliability of a device.

Abstract: A power-on reset circuit includes a first circuit arranged between a high voltage supply terminal (VDD) and a low voltage supply terminal (VSS), wherein the first circuit is configured to output a low-voltage reset signal at an output node (PORB) when VDD is powered up and to output a high voltage signal at the node PORB after the VDD reaches a predetermined voltage during power up; a second circuit configured to set the node PORB to a low voltage after VDD is powered off; and a third circuit configured to provide a supply voltage at a node DV to the second circuit. The supply voltage is lower than the voltage of VDD by approximately one diode voltage.

Abstract: A reset ramp control structure and method is described. A fast ramp down condition of a monitored voltage is detected and used to force the state of system reset. Delay between fast ramp detection and the forcing of system reset is adjustable. Operation is adaptable to include all DC power systems. The reset ramp control structure provides operational protection during fast ramp down conditions when standard reset circuitry may not be operational.

Abstract: To present a reset control circuit and a reset control method used in a system including clock synchronous circuit, capable of resetting appropriately, especially in case of abnormality, when the clock signal is stopped or its period is longer as compared with the reset response required for detection of abnormal state. A reset control circuit 200 for output control of reset signal RS depending on reset request signal RR comprises a clock transforming unit 210 for transforming and issuing a clock signal CK, while generating a clock output signal RC at delay of clock output waiting period DC depending on the reset request signal RR, and a reset signal generator 220 for generating a reset signal RS at delay of reset output waiting period D depending on the clock output signal RC.

Abstract: A power-on detection circuit is arranged to cooperate with a thermal-voltage generator to determine when predictable circuit operation is achieved. The power-on detection circuit includes a comparator circuit and an inverter circuit. A power-on reset (POR) signal is generated by the inverter circuit, which evaluate an output of the comparator circuit. The comparator circuit includes a differential pair arrangement that is imbalanced with a resistor. The differential pair in the comparator circuit is arranged to determine when the thermal voltage has reached a desired target level by evaluating two points within the thermal-voltage generator circuit. The comparator circuit can have a target level that is below 100% of full operation to improve reliability.

Abstract: Determining voltage level validity for a power-on reset condition is described. A supply voltage is applied to an integrated circuit. An oscillating signal is generated responsive to the supply voltage applied. A counting occurs responsive to oscillations of the oscillating signal. A triggering occurs responsive to reaching a first voltage level of the supply voltage for the power-on reset condition. A first count of the counting occurs responsive to the triggering. A second count is selected responsive to the first count. A second level is accepted as having at least met a threshold for the supply voltage responsive to the counting reaching the second count for the power-on reset condition.

Abstract: A power good signal generating circuit includes an NPN transistor, a first resistor, a second resistor, a third resistor, a first power source, and a second power source. The first resistor is connected between a base of the transistor and the first power source. The second resistor is connected between a collector of the transistor and the second power source. The third resistor is connected between an emitter of the transistor and ground. The collector is connected to an output for sending a PG signal and the emitter is connected to an input for receiving a control signal P.

Abstract: An apparatus comprising a plurality of flip-flops and a compare circuit. The flip-flops may each be configured to (i) receive a clock signal and an input signal and (ii) generate an output signal. The flip-flops may be configured in series such that the output signal of a first of the flip-flops is presented as the input signal to a second of the flip-flops. The compare circuit may be configured to generate a reset signal in response to each of the output signals. The reset signal is generated until each of the output signals matches a set of predetermined values stored in the compare circuit.

Abstract: A voltage providing circuit includes a protective circuit and a power supply circuit. The protective circuit includes a first transistor. A first control signal is input to a collector of the first transistor, a second control signal is input to a base of the first transistor, an emitter of the first transistor is grounded. The collector of the first transistor is connected to the power supply circuit. The second control signal and the first control signal jointly control the power supply circuit to be turned on or turned off. When the second control signal is at a low level, the first transistor is turned off and the power supply circuit is turned off. When the second control signal is at a high level, the first transistor is turned on and the power supply circuit is turned on. Thus, the providing circuit can prevent the electronic component from being damaged when a computer is restarted.

Abstract: A wireless device includes a supply independent bias circuit such as a bandgap current generator or a Proportional-To-Absolute-Temperature (PTAT) current generator. A start-up circuit that includes an amplifier and a Schmidt trigger to provide the desired start-up that avoids regulation to an undesired state.

Abstract: In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on.

Abstract: An apparatus comprising a plurality of flip-flops and a compare circuit. The flip-flops may each be configured to (i) receive a clock signal and an input signal and (ii) generate an output signal. The flip-flops may be configured in series such that the output signal of a first of the flip-flops is presented as the input signal to a second of the flip-flops. The compare circuit may be configured to generate a reset signal in response to each of the output signals. The reset signal is generated until each of the output signals matches a set of predetermined values stored in the compare circuit.

Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.

Abstract: A supply voltage level detection circuit makes use of an additional supply already provided for power. A voltage detection circuit defines a first threshold, and a differencing circuit defines a second threshold. The output state of the differencing circuit is saved in a latch. The latch may be cross coupled gates of cross coupled inverters. When inverters are used, the differencing circuit output contends with the internal latch drive when setting or resetting the latch. The design allows the differencing circuit to overcome the inverter's internal drives to change the logic state of the latch.

Abstract: A power-up reset circuit includes a sensing circuit and an output circuit. The sensing circuit outputs a node voltage in response to an external power supply voltage. The output circuit outputs a voltage sensing signal in response to the node voltage. A signal generation circuit outputs a reset signal in response to the voltage sensing signal. A first resistance adjustment circuit adjusts the level of the node voltage in response to an externally input first control signal. A second resistance adjustment circuit adjusts the level of the voltage sensing signal in response to an externally input second control signal.

Abstract: A reset transistor is prevented from being deteriorated when power-down occurs during a programming operation or an erasing operation. It is made possible to protect the reset transistor as well as other transistors in a circuit to which a high voltage is applied when the power-down occurs during the erasing operation on an EEPROM, because the system is not reset all at once based only on a first reset signal POR of a power-on reset circuit, but is reset based on the first reset signal POR and a low voltage detection signal LD from a low voltage detection circuit so that the reset transistor is not turned on while the high voltage is applied to it.

Abstract: A reference circuit can include a reference section that provides a reference value for other circuits of an integrated circuit and can be enabled and disabled in response to an enable signal. The reference circuit can include at least a first node, draw a reference current in the enabled mode, and draw essentially no current in the disabled mode. A pulse start-up section can provides a low impedance path between the first node and a first potential for a predetermined duration in response to the reference circuit being enabled. A continuous start-up section can provide a low impedance path between the first node and the first potential based on a logic state of an enable signal.

Abstract: In a power-on reset circuit and a method of generating a power-on reset signal tolerant of variation of an ambient temperature, the power-on reset circuit includes a first power-on reset unit, a second power-on reset unit and a logic gate. The first power-on reset unit generates a first power-on reset signal that is activated at a first level of a power supply voltage at a first temperature, and is activated at a second level of the power supply voltage at a second temperature. The second power-on reset unit generates a second power-on reset signal that is activated at the second level at the first temperature, and is activated at the first level at the second temperature. The logic gate executes a logical disjunction operation or a logical conjunction operation of the first power-on reset signal and the second power-on reset signal and generates a third power-on reset signal.

Abstract: A circuit and a method generate a power-on reset signal having a leading part and a trailing part. The circuit includes a startup circuit generating the leading part of the power-on reset signal and a second circuit generating the trailing part of the power-on reset signal. The power-on reset circuit is implemented by a process which does not rely on native devices having zero threshold voltage to control a circuit generating the trailing part of the power-on reset signal.

Abstract: Disclosed is an improved circuit and method for generating a power on reset signal, the circuit being a two-stage circuit comprising a delay-stage circuit and an output-stage circuit. The delay-stage circuit delays a time for a power on reset signal generated in the output-stage circuit changing from low to high, so that a power voltage having a low rising speed may be normally reset. Further, the two stages provide charging paths and discharging paths so that the power on reset signal may be prevented from changing from high to low when it has changed from low to high, when noises are presented on the power voltage.

Abstract: A method and system is disclosed for creating a timing delay for power-on reset. A state machine is formed with three states. It resets a counter value to a predetermined number in an initial state, and increments the counter value for a predetermined number of reset cycles in a reset state until the counter value reaches a predetermined value for creating the time delay, and ends the reset state in a finish state if the counter reaches the predetermined value and if a randomly generated value matches a predetermined signature, wherein if in the reset state the randomly generated value does not match the signature or if in the finish state either the counter value does not reach the predetermined value or the randomly generated value does not match the signature, the initial state starts and subsequently enters the reset state after resetting the counter value.

Abstract: An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is an internal reference voltage pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset and wherein the internal reference voltage pin is normally used by the integrated circuit for internally generating a reference voltage.

Abstract: A processor or a semiconductor integrated circuit has circuit blocks performing signal processing, internal power supply nets, noise detecting circuits corresponding to each circuit block that detect noise on the power supply nets and an interruption handling circuit that prevents a malfunction in processing within a circuit block caused by noise on the power supply nets. When noise is detected, the interruption handling circuit performs an interruption by sending an interruption signal to the circuit block relating to the signal processing for preventing a malfunction to the circuit block. During the operation of a plurality of stages for executing an instruction, noise is monitored at every stage. If no noise is detected through a final stage, the result is outputted. If noise is detected at any one of the stages, then an interruption process is performed.

Abstract: A method and system for providing startup delay is disclosed. The system includes a startup delay circuit. The startup delay circuit includes a signal generating sub-circuit that generates an output signal. The signal generating sub-circuit generates the output signal after a period of time that is related to an input offset of a component of the signal generating sub-circuit.

Abstract: A signal generating apparatus that is capable of accurately measuring a trip point of a power-up signal without installing a separate measuring instrument is described. An apparatus for generating a signal includes a power-up signal generating unit that generates a power-up signal using an external voltage and a measuring unit that outputs, when the power-up signal is enabled, the comparison result between a voltage generated on the basis of the external voltage and a reference voltage as a trip point.

Abstract: A device is provided for resetting an integrated circuit generating a reset signal after a power supply voltage drop to a very low level has been detected. Such a device includes at least one control means, the state of which (conducting or non-conducting) is controlled by a control voltage equal to the difference between the power supply voltage and a predetermined offset voltage, such that if the control voltage is less than or equal to a threshold, the control means authorizes activation of the means for generating a reset signal.

Abstract: An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Abstract: The present invention discloses a reset method for a digital circuit. The method includes: providing a clock signal to the digital circuit; keeping the clock signal at a logic level according to a first indicating signal; generating a reset signal for resetting the digital circuit; and recovering the clock signal to the digital circuit according to a second indicating signal.

Abstract: A start up circuit of power converters is presented. It includes a first transistor, a resistive device, a second transistor, a third transistor and a diode. The first transistor is coupled to a voltage source. The third transistor is connected in serial with the first transistor to output a supply voltage to a control circuit of the power converter in response to the voltage source. The diode is connected from a transformer winding of the power converter to supply a further supply voltage to the control circuit of the power converter. The second transistor is coupled to control the first transistor and the third transistor in response to a control signal. The resistive device provides a bias voltage to turn on the first transistor and the third transistor when the second transistor is turned off. Once the second transistor is turned on, the third transistor is turned off and the first transistor is negative biased.

Abstract: A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to the internal node, and coupling an output of the sensing circuit to a second pad on the integrated circuit when the activation voltage is present on the first pad. A sensing circuit includes first and second pads, a voltage-sensor circuit having an input coupled to an internal node and a power connection coupled to a sensor power node. A circuit is configured to place a supply potential on the sensor power node when a threshold value is on the first pad. A switch coupled between the sensing circuit and the second pad turns on when the supply potential is on the voltage sensor power node.

Abstract: A system and method for power-on reset and under-voltage lockout schemes. The system includes a first transistor, which includes a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage. The system includes a second transistor, which include a second gate, a third terminal, and a fourth terminal, the third terminal being configured to receive an input voltage. The system includes a first resistor that is associated with a first resistance. The first resistor includes a fifth terminal and a sixth terminal, the fifth terminal being configured to receive the input voltage. The system includes a second resistor that is associated with a second resistance. The second resistor includes a seventh terminal and an eighth terminal, the seventh terminal being coupled to the sixth terminal. The system includes a first Zener diode that is associated with a first Zener voltage.

Abstract: A power-up reset circuit with reduced power consumption. The resistance of the power-up reset circuit may be adjusted during a power-up operation. The standby current may thereby be reduced, which may reduce the power consumption in the power-up reset circuit.

Abstract: A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.

Abstract: A power-on control circuit includes a coupling device coupled to a first voltage supply. A first inverter, coupled between the coupling device and a complementary voltage, has an input node coupled to a second voltage supply with a supply voltage level lower than that of the first voltage supply. A level shifter, coupled between the first voltage supply and the complementary voltage, has a first input node connected to an output node of the first inverter and a second input node coupled to the second voltage supply, for generating the power-on control signal when the first voltage supply is powered up and the second voltage supply is turned off and for disabling the power-on control signal when the second voltage supply is subsequently powered up. The coupling device eliminates a leakage current path from the first voltage supply to the complementary voltage through the first inverter.

Abstract: A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be pulled-up to a logic HIGH voltage, for example, by removing the low-impedance path and allowing a voltage source to reach the node through a resistor or transistor. A low voltage pull-down circuit may be provided in a power supervision circuit for systems that operate with, for example, low power conditions. The open-drain node is utilized as a power-on-reset node that provides a LOW logic signal to a system when the power being supplied to the system is below a predetermined voltage threshold.