Abstract: A shift register of a gate driving circuit includes a pull-up unit for pulling up a first output signal and a first gate signal to a high voltage level according to a driving voltage and a high-frequency clock signal, a start-up unit for transmitting a second gate signal, an energy-store unit for providing the driving voltage to the pull-up unit according to the second gate signal, a first discharging unit for pulling down the driving voltage to a first voltage level according to a first control signal, a first leakage-preventing unit for turning off the first discharging unit when the first gate signal reaches the high voltage level, a first pull-down unit for respectively pulling down the first output and first gate signals to the first and a second voltage levels according to the first control signal, and a first control unit for generating the first control signal.

Abstract: An integrated circuit with automatic configuration is disclosed. The integrated circuit comprises a plurality of controllers and a clock detection device. The controllers share a plurality of common pins. The clock detection device coupled to a specified common pin for performing clock detection operations on an external clock signal through the specified common pin according to a plurality of predetermined thresholds and generating a plurality of control signals to the controllers so that only one controller is enabled and performs signal transmission through the common pins.

Abstract: Embodiments of a power-on and brown-out detector are described. In an embodiment, a power-on and brown-out detector for a power supply includes a power-on detection module, a brown-out detection module, and a logic module. The power-on detection module is connected to the power supply and is configured to generate a power-on signal in response to a voltage increase of the power supply. The brown-out detection module is connected to the power supply and is configured to generate a brown-out signal in response to a voltage charge by the power supply and a subsequent voltage decrease of the power supply. The logic module is configured to generate a control signal in response to the power-on signal and the brown-out signal. The power-on detection module is further configured to be activated or deactivated by the control signal. Other embodiments are also described.

Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

Abstract: A programmable power-on reset circuit in accordance with one embodiment of the invention can include a programmable voltage divider. The programmable power-on reset circuit can also include a comparator that is coupled to the programmable voltage divider and that is coupled to receive a reference voltage. Additionally, the programmable power-on reset circuit can include a non-volatile memory that is coupled to the programmable voltage divider, wherein the non-volatile memory can be coupled to receive programming for controlling an output of the programmable voltage divider.

Abstract: Some of the embodiments of the present disclosure provide a D-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed.

Abstract: A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.

Abstract: Signal synchronizers synchronize input signals with a clock signal. The input of each synchronizer is connected to a first input and the output of each synchronizer is connected to a second input of a respective first gate arrangement. The first gate arrangements provide an output signal only if there is an input signal on the first input and none on the second input or vice versa. The outputs of each of the first gate arrangements is connected to respective inputs of a second gate arrangement, which provides an output signal if there is a signal on any of its inputs. The output of the second gate arrangement is connected to a third gate arrangement which operates such that the clock signal to the synchronizers is only enabled when there is a change to the state of a signal received at the input of at least one of the synchronizers.

Abstract: The present invention discloses a reset circuit that has a reset IC 12 having a terminal 2 connected to a reset terminal of the microcomputer 30 that is driven by a constant voltage (3.3V) generated by regulating a rectified voltage (V+) by a regulator 24, and a terminal 4 that inputs the constant voltage (3.3V) thorough a register R1, and outputs a reset signal to the microcomputer 30 when an input voltage input to the terminal 4 is lower than a first threshold value; and a transistor Q1 in which a collector is connected to the terminal 4 through a resistor 2 and an emitter is connected to the ground and the transistor is turned on when an output voltage of the switching transformer 21 is lower than a predetermined level, wherein the voltage lower than the first threshold value is input to the terminal 4 when the transistor Q1 is turned on.

Abstract: A voltage change detection device is provided, which can reduce a deviation of a detection potential and can detect a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node.

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract: There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level.

Abstract: An integrated circuit includes first and second transistors, a switch, and a power-on reset (POR) circuit. The first transistor has a first current electrode, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode. The switch is for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal. The POR circuit has a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch. The latch-up detection circuit is for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.

Abstract: A brown out detector (BOD), configured to provide a BOD reset in the event of a brown out event, is provided. The BOD includes means for tracking a reference voltage that is updated through duty cycling schemes so as to reduce power consumption, as well as means for detecting a falling flank of a supply voltage so as to optimize response times. More specifically, the BOD includes at least one track module, at least one sample module, at least one detector module and at least one comparator. The comparator is configured to compare a duty cycled tracked reference voltage with a duty cycled sampled reference voltage and to output a BOD reset if the tracked reference voltage is less than the sampled reference voltage. The comparator is further capable of exhibiting improved response times when a boost current is received. The boost current is provided by the detector module when the supply voltage falls beyond a predetermined threshold.

Abstract: A reset circuit comprising: a first depletion mode device having a first terminal coupled to a node at a reset voltage and a second terminal for providing a reset signal to at least one device; and a control circuit arranged to switch the first depletion mode device into a high impedance state after a first predetermined period.

Abstract: Power gating control and related circuitry for integrated circuits is described herein. A centralized power gating control circuit uses trigger circuits to control the on/off switching of power gating circuits distributed at different points in a chip, integrated circuit, module or block (collectively “IC”). The power gating circuits may include power gates partitioned for sleep and shutdown modes. The shutdown mode power gates may employ multi-level power gate architecture to minimize inrush current during power-up of the IC. Each level may be associated with or tied to a trigger circuit and activated based on a voltage level reaching the voltage threshold of the trigger circuit. The power gating control and related circuitry may be embedded in the IC.

Abstract: A power reset circuit with zero standby current consumption includes a power storage unit, first, second, and third voltage detection units, a switching unit, and a power reset unit. The power storage unit stores electric power by a supply voltage source. The first, second, and third voltage detection units are connected to the supply voltage source to start a switching circuit of the first, second, and third voltage detection units in accordance with a change in a normal supply stage, a shutdown stage, and a voltage ramp-up stage of the supply voltage source, control a voltage level of the power reset unit, and thereby generate the power reset signal. Accordingly, the power reset circuit does not consume current in a standby state (the normal supply stage of the supply voltage source) and thus is characterized by zero current consumption.

Abstract: A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

Abstract: A novel semiconductor device and a method of driving the semiconductor device. A (volatile) node in which data that is rewritten as appropriate by arithmetic processing is held and a node in which the data is stored are electrically connected to each other via a source and a drain of a transistor in which a channel is formed in an oxide semiconductor layer. Then, data and data obtained by inverting the data (inverted data) are stored before supply of power source voltage is stopped, and the two inputs (data) are compared after restart of supply of the power source voltage, so that data obtained by arithmetic processing just before the supply of the power source voltage is stopped is restored.

Abstract: A system reset circuit and a method for resetting a system automatically according to an operation state of the system are provided. The system reset circuit includes a system, which is triggered by a first logic state during an operation of a program and a second logic state at termination of the program, for generating a trigger signal for maintaining the first logic state in a lockup state and a counter for receiving the trigger signal as an enable signal, for counting a period of the first logic state of the trigger signal, and for clearing the counting for a period of the second logic state, and of which an output node is connected to a reset node of the system, wherein, when the first logic state period of the trigger signal is maintained before the counter expires, the system generates a reset signal automatically.

Abstract: An integrated circuit is provided that includes a plurality of modules, comprising at least one clock-gated module; and a controller unit, which is arranged to enable and disable provision of a clock signal to the at least one clock-gated module. The at least one clock-gated module includes one or more electronic circuits arranged to be, in a first state of an electrical stress condition during a first portion of a period of time and in a second state of less electrical stress than in the first state during a second portion of the period of time. The at least one clock-gated module is further arranged to, switch the one or more electronic circuits between the first state and the second state such that a change of a characteristic of at least one of the one or more electronic circuits caused by the electrical stress condition is at least partially reduced.

Abstract: A flip-flop circuit includes an input stage circuit, a middle stage circuit, an output stage circuit and a set/reset circuit. The input stage circuit is arranged for receiving a first signal from a first node, and selectively outputting a second signal at a second node according to at least one control signal. The middle stage circuit is coupled to the input stage circuit, and arranged for receiving the second signal, and selectively outputting a third signal at a third node according to the at least one control signal. The output stage circuit is coupled to the middle stage circuit, and arranged for receiving the third signal to output an output signal. The set/reset circuit is coupled to the second node and the third node, and arranged to receiving a set signal and a reset signal, and selectively determining a voltage level of the third signal at the third node.

Abstract: A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.

Abstract: Systems, apparatus, and methods are provided for initializing a voltage bus. An exemplary system includes an input interface, a voltage bus, discharge circuitry coupled to the voltage bus, connection circuitry coupled between the voltage bus and the input interface, and a control module coupled to the connection circuitry and the discharge circuitry. The control module activates the discharge circuitry prior to activating the connection circuitry.

Abstract: An apparatus for controlling retention of data includes a logic circuit, a retention control cell circuit, and an I/O cell circuit. The logic circuit generates at least one retention enable signal before a chip enters a reduced power mode. The retention control cell circuit latches the retention enable signal and outputs a retention enable control signal based on a first power signal of the logic circuit and a detection result of a second power signal for input/output (I/O). And, the I/O cell circuit latches data based on the retention control signal.

Abstract: A power-up signal generation circuit includes a discharge driving unit configured to discharge a voltage of a power-up detection node in response to a voltage of an external power supply voltage, a charge driving unit configured to charge the voltage of the power-up detection node in response to a voltage of an internal power supply voltage, a power reset discharging unit configured to discharge a voltage of the power-up detection node while the semiconductor integrated circuit is reset, and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node.

Abstract: An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

Abstract: An exemplary resetting circuit adapted for regulating a voltage on an output terminal of a shift register is disclosed. The resetting circuit includes a reset driving module and a reset module. The reset driving module is received with an enable signal to output a control voltage signal to an output terminal of the reset driving module. The reset module is electrically coupled to the output terminal of the shift register and the output terminal of the reset circuit driving module, and is controlled by the control voltage signal on the output terminal of the reset driving module to determine whether switching on an electrical path between the output terminal of the shift register and a gate-off voltage level.

Abstract: A method for generating a reset signal in a system on a chip (SoC) is disclosed. A sense signal is generated responsive to a supply voltage provided to the SoC. A reset signal is asserted while the sense signal is below a threshold voltage level. The sense signal may be forced below the threshold value for a period of time determined by a first capacitive time constant circuit. Operation of the first capacitive time constant circuit is inhibited after the sense signal has been above the threshold value level for a second period of time as determined by a second capacitive time constant circuit responsive to the supply voltage. In some embodiments, the first capacitive time constant circuit and the second capacitive time constant circuit may be discharged when the supply voltage falls below a second threshold voltage level, such that the reset signal is again asserted.

Abstract: A glitch circuit includes an SR flip-flop where a received input clock is operatively coupled to set and reset inputs of the flip-flop, respectively. A configurable delay circuit receives an input signal, and an output of the delay circuit provides a delayed signal. The configurable delay circuit includes a plurality of switchable taps, each providing an increment of delay to the input signal. The delay circuit input is operatively coupled to an output of the flip flop, and an output of the delay circuit is operatively coupled to the inputs of the flip-flop. The glitch circuit captures a first signal transition of the input clock and blocks all other transitions from propagating through the flip-flop during a selected delay period so as to provide on an output of the flip-flop, the glitch-free output clock.

Abstract: A semiconductor integrated circuit includes a first retention flip-flop configured in a first type in which a retention flip-flop is able to retain data based on one of a low-level clock signal and a high-level clock signal, and unable to retain data based on another one of the low-level clock signal and high-level clock signal, and a second retention flip-flop configured in a second type in which a retention flip-flop is able to retain data based on the low-level clock signal and also able to retain data based on the high-level clock signal.

Abstract: A data acquisition system includes an analog-to-digital converter (ADC) having a MUX control outputs, a controller coupled to the ADC, a multiplexer coupled to the MUX control outputs of the ADC, and an operational amplifier coupling an analog data output of the multiplexer to an input of the ADC. An ADC having integrated multiplexer control includes control logic circuitry, ADC circuitry, MUX logic and an oscillator coupled to the control logic circuitry, the ADC circuitry, and the MUX logic.

Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.

Abstract: Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: A circuit including an input configured to receive a clock signal. Detection circuitry may be configured to detect if the clock signal is present on the input. An output is configured to provide a control signal having a first level if the clock signal is present on the input and a second level if the clock signal is absent from the input.

Abstract: A clock signal generation circuit includes a first oscillation circuit for generating a first oscillation clock signal having a first frequency; a second oscillation circuit for generating a second oscillation clock signal having a second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as a high speed clock signal. The clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.

Abstract: An integrated circuit includes circuitry organized into sub-blocks, and power supply selection circuitry operative to selectively adjust the connectivity of power supply terminals of the sub-blocks. When the integrated circuit is operating in an active mode, the power supply selection circuitry couples the sub-blocks in parallel between upper and lower active-mode power supplies; when the integrated circuit is operating in a standby mode, the power supply selection circuitry couples two or more sub-blocks in series between upper and lower standby-mode power supplies. Additionally, in standby mode, isolation circuitry within a sub-block is activated to isolate circuitry within the sub-block from input or output terminals of the sub-block.

Abstract: A semiconductor device including a power-on-reset (POR) circuit. The semiconductor device includes a driving voltage generator configured to generate a first voltage that rises at a first slope and subsequently rises at a second slope greater than the first slope and a first POR signal generator configured to receive the first voltage and generate a first POR signal having a first ramp-up time.

Abstract: In one embodiment, a circuit is provided. The circuit includes a load configured to receive power through a power path. The circuit also includes a current monitor configured to sense a current draw on the power path. A switch on the power path is coupled in series between the load and a power rail, and a control circuit is coupled to the current monitor. The control circuit is configured to set the switch to a non-conducting state and to send a reset signal to the load if the current monitor senses an overcurrent on the power path.

Abstract: Apparatus and methods for a power-on-reset (POR) circuit are provided. In an example, a (POR) circuit can include a self-bias module configured to provide a reference voltage, a feedback module configured to provide a feedback voltage, a comparison module configured to compare the feedback voltage to the reference voltage and to provide an output signal, an inverter configured to couple the output of the comparison module to an enable input of the self-bias module, and a switch module coupled to the inverter, wherein the switch module and the inverter are configured to disabled the self bias module when the feedback voltage exceeds the reference voltage.

Abstract: An electronic device and a method for operating an electronic device, wherein the electronic device comprises a reset stage which is configured to have a power down threshold and a power cycle threshold. The voltage level of the power cycle threshold is lower than the voltage level of the power down threshold. The two threshold levels define a first and second interval for a supply voltage of the electronic device. A first interval is between the power cycle threshold and the power down threshold. A second interval is above the power down threshold. The reset stage is further configured to provide the control signal having a defined first state in the first interval and a defined second state in the second interval. The electronic device is set to a low power reset mode if the control signal is in the first state and the electronic device is enabled to enter an active mode if the control signal is in the second state.

Abstract: A power on reset signal generating apparatus is provided. The power on reset signal generating apparatus includes a trigger capacitor, a reference current supplying circuit, and a current regulator. One end of the trigger capacitor is coupled to a ground voltage, and the other end of the trigger capacitor generates a power on reset signal. The reference current supplying circuit is coupled to a signal generating end. The current regulator is coupled to the signal generating end, and the signal generating end draws a splitting current to adjust the value of the current received by the trigger capacitor.

Abstract: A circuit includes first to fifth resistors and first to third electronic switches. The circuit allows a signal from a first terminal of the second electronic switch to change from a low level to a high level gradually, and to change from a high level to a low level abruptly.

Abstract: A hold pulse latch is located in a data path between an output of a launch pulse latch and an input of a capture pulse latch. The hold pulse latch is configured to latch, and hold for the input of the capture patch, the output of the launch pulse latch in response to a hold pulse on its enable input. Optionally, at higher voltages, and frequency is high the launch pulse latch is changed to a transparent buffer mode. Optionally, the hold pulse latch is placed midway through the logic path between the launch pulse latch and the capture pulse latch.

Abstract: When the value of a power supply voltage (VDD) becomes a first threshold value or higher, a first start-up circuit (20) causes a band gap reference circuit (10) to start a stable operation and a first voltage value (VA) is output from the band gap reference circuit (10). When the value of the power supply voltage becomes a second threshold value or higher which is greater than the first threshold, a second start-up circuit (40) turns on a PMOS transistor (MP3) of a voltage dividing circuit (30), and a second voltage value (VB) output from the voltage dividing circuit (30) becomes a value, which is derived by dividing the value of the power supply voltage according to the resistance ratio of resistors (R31, R32). From a voltage comparison circuit (50), a reset level voltage value is output when the second voltage value (VB) is smaller than the first voltage value (VA), and a power-supply voltage level voltage value is output if the second voltage value (VB) becomes the first voltage value (VA) or higher.

Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

Abstract: A power on reset (POR) circuit is provided. For the POR circuit, a PMOS transistor is coupled to a first voltage rail at its source. A drive circuit is coupled to the drain of the PMOS transistor and is configured to output a POR signal. A voltage divider is coupled between the drain of the PMOS transistor and the second voltage rail. A switch network is provided as well, which has first and second switches. The first switch is coupled between the gate of the PMOS transistor and the voltage divider, and the second switch is coupled between the gate of the PMOS transistor and the voltage divider. A controller is also coupled to control the first and second switches, wherein the first and second switches are complementary driven.

Abstract: A device includes a first internal voltage generation circuit generating a first internal voltage in response to an external power supply voltage, a second internal voltage generation circuit generating a second internal voltage in response to the external power supply voltage, the second internal voltage being different in voltage level from the first internal voltage, and a preset signal generation circuit responding to a power-on of the external power supply voltage to the device and generating, independently of the first internal voltage, first and second preset signals that bring the first and the second internal voltage generation circuits into respective initial states, the preset signal generating circuit stopping generation of the first preset signal when the external power supply voltage reaches a first voltage level and stopping generation of the second preset signal when the external power supply voltage reaches a second voltage level different from the first voltage level.