Abstract: An input priority determination circuit is configured such that: (i) when a set signal S is asserted and a reset signal R is negated, an intermediate set signal S? is asserted and an intermediate reset signal R? is negated; (ii) when the set signal S is negated and the reset signal R is asserted, the intermediate set signal S? is negated, and the intermediate reset signal R? is asserted; (iii) when a control signal P indicates a set priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is asserted and the intermediate reset signal R? is negated; and (iv) when the control signal P indicates a reset priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is negated and the intermediate reset signal R? is asserted.

Abstract: A system and method to control a power on reset signal is disclosed. In a particular embodiment, a power on reset circuit includes a first linear feedback shift register and a second linear feedback shift register. The first linear feedback shift register is configured to operate at least partially in parallel with the second linear feedback shift register.

Abstract: An exemplary reset circuit includes a first connection jack connected to a first power supply, a second connection jack connected to a second power supply, a reset IC, a voltage response module, and a control module. The voltage response module outputs a first response signal when the voltage provided by the second power supply is abnormal, and then the control module outputs a first voltage which is less than the voltage provided by the first power supply. The voltage response module outputs a second response signal when the voltage provided by the second power supply is normal, and then the control module outputs a second voltage which is equal to the voltage provided by the first power supply. When the voltage received by the reset IC is changed from the first voltage to the second voltage, the reset IC outputs a reset signal to reset the processing IC.

Abstract: Externally configurable power-on-reset systems and methods for integrated circuits are disclosed that utilize internal power-on-reset circuitry and reset control circuitry to provide operational configurations determined by external connections. In one configuration where no dedicated external reset signal is desired, the reset control circuitry relies upon the internal power-one-reset circuitry to generate the internal reset control signal. In another configuration where an external reset signal is utilized, the reset control circuitry relies upon the external reset signal, which overrides the internal power-on-reset circuitry, to generate the internal reset control signal. In further configurations, the reset control circuitry utilizes logic circuitry controlled through a digital interface to determine when the internal reset control signal can be de-asserted.

Abstract: A system can include at least one power supervisor coupled to a power supply voltage and including a processing element configured by instructions stored in a memory to assert at least one output signal in response to at least one comparator output, at least one comparator having a first input coupled to the power supply voltage and a second input coupled to a reference voltage, and configured to provide one comparator output, and at least one programmable voltage divider coupled to one input of the comparator and configured to vary a voltage divided output in response to the processing element.

Abstract: A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.

Abstract: A voltage operation system includes: a power on reset circuit, a voltage detecting circuit, an operating signal generating circuit, and an electronic fuse circuit. The power on reset circuit is used for generating a power on reset signal. The voltage detecting circuit detects an operating voltage to output a voltage detecting signal. The operating signal generating circuit, coupled to the power on reset circuit and the voltage detecting circuit-outputs an operating signal. The electronic fuse circuit can be fused according to a lock signal, a fuse signal, and the operating signal.

Abstract: An initialization circuit comprises a section signal generator generating a section signal, of which a prescribed section is enabled in response to a power-up signal, a first oscillator generating a first period signal in response to the section signal, a first period multiplier generating a first multiplied signal by multiplying a period of the first period signal, and a signal selector transferring the first multiplied signal or a second multiplied signal selectively as a self-refresh enable signal in response to the section signal.

Abstract: A power-on reset (POR) circuit is provided. The POR circuit includes a first current source, a second current source, and a current comparator. The first current source is arranged to provide a relatively supply-independent circuit. The second current source is arranged to provide a supply-dependent current. The current comparator is arranged to compare the relatively supply-independent circuit with the relatively supply-dependent current to provide a POR signal.

Abstract: A first switch is switched to short a multi-functional pin of an integrated circuit to a ground terminal or let a current supplied to the multi-functional pin to flow to a second switch connected to the multi-functional pin. Before the integrated circuit is ready, the second switch is closed circuit and is detected its current to determine a first signal to enable or disable the integrated circuit. After the integrated circuit is ready, the second switch is open circuit, the voltage at the multi-functional pin is detected to determine a second signal to enable or disable the integrated circuit, and when the voltage at the multi-functional pin is higher than a threshold, a power good signal is triggered.

Abstract: A method and apparatus of resetting a mobile device including a Power Management Integrated Circuit (PMIC) with no manual reset function are provided. The apparatus includes an input unit for creating a specific input signal for a reset according to a user's input. The apparatus includes a reset unit for creating a manual reset input signal in response to the specific input signal, and for blocking battery power supplied to the PMIC by using the manual reset input signal and a signal created during operations of the mobile device. The reset apparatus includes a power unit for supplying the battery power.

Abstract: An electronic device and a method for operating an electronic device, wherein the electronic device comprises a reset stage which is configured to have a power down threshold and a power cycle threshold. The voltage level of the power cycle threshold is lower than the voltage level of the power down threshold. The two threshold levels define a first and second interval for a supply voltage of the electronic device. A first interval is between the power cycle threshold and the power down threshold. A second interval is above the power down threshold. The reset stage is further configured to provide the control signal having a defined first state in the first interval and a defined second state in the second interval. The electronic device is set to a low power reset mode if the control signal is in the first state and the electronic device is enabled to enter an active mode if the control signal is in the second state.

Abstract: An integrated circuit includes first and second transistors, a switch, and a power-on reset (POR) circuit. The first transistor has a first current electrode, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode. The switch is for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal. The POR circuit has a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch. The latch-up detection circuit is for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.

Abstract: A microcomputer includes a first comparator which compares a voltage to be monitored, with a first reference voltage, a second comparator which compares the voltage to be compared, with a second reference voltage, and an interrupt control circuit which monitors the voltage to be monitored by the first and second comparators in parallel and, when a preset condition is satisfied, generates an interrupt signal.

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract: The present invention is applicable to the field of electrics and provides an integrated circuit (IC) and a standby controlling method thereof. The IC comprises a reset device, a standby control device, a functional device and a power supply control device. The functional device at least comprises a functional unit that does not operate in a standby mode. The power supply control device is configured to supply power to the functional device, the standby control device and the reset device.

Abstract: A no-load detecting circuit and the method thereof are disclosed. The no-load detecting circuit may be applied in switching mode power supplies or other circuits. The no-load detecting circuit comprises: a variable resistance circuit coupled in series to a load of the switching mode power supply; and a first comparison circuit coupled to the variable resistance circuit to receive the voltage across the variable resistance circuit, wherein based on the comparison of the voltage across the variable resistance circuit and a first threshold, the first comparison circuit generates a no-load detecting signal indicative of the load status; wherein the equivalent resistance of the variable resistance circuit varies based on the varying of the load of the switching mode power supply.

Abstract: A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.

Abstract: Disclosed are apparatus and methodology subject matters for providing improved functionality of a meter in a 2-way communications arrangement, such as an Advanced Metering System (AMS) or Infrastructure (AMI). More particularly, the present technology relates to methodologies and apparatus for providing load sensing for utility meters which preferably are operable with remote disconnect features in an Advanced Metering Infrastructure (AMI) open operational framework. Meters per the present subject matter utilize a detection circuit, and separately utilize certain remote disconnect functionality. In particular, disconnect functionality is coupled with consideration of electric load information, such as load current as determined by the metering functionality.

Abstract: A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed.

Abstract: A power-up signal generation circuit includes a main driving unit configured to drive a power-up detection node according to power supply voltage level information; an auxiliary driving unit configured to additionally drive the power-up detection node according to temperature information; and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node in accordance with the operations of the main driving unit and the auxiliary driving unit.

Abstract: A data processing system includes a brown-out detection circuit with a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor has a first current electrode coupled to the second terminal of the first resistive element, a control electrode, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal. The comparator has a first input terminal coupled to the first terminal of the first resistive element, a second input terminal coupled to the second terminal of the first resistive element, and an output terminal for providing a brown-out detection signal.

Abstract: A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.

Abstract: An electronic integrated device may include a signal generation stage arranged to generate a first signal representative of an under voltage lockout logic signal. The signal generation stage may include a voltage divider block arranged to provide an internal reference voltage signal to a bandgap core group based upon a reference signal. The bandgap core group may generate the first signal based upon the internal reference voltage signal. The bandgap core group may further include a first generation module arranged to generate a output regulated reference voltage signal based upon the internal reference voltage signal, and a second generation module arranged to generate the first signal based upon the internal reference voltage signal and a driving signal obtained by a preliminary processing of the internal reference voltage signal by a bandgap core module included within the band gap core group.

Abstract: A start circuit including a load unit, a first switch, a second switch and a reset control circuit is provided. The load unit receives a power voltage. The first switch is electrically connected between a first end of the load unit and a ground, and receives a node voltage from a reference circuit. The second switch has a first end electrically connected to the reference circuit, a second end electrically connected to the ground, and a control end electrically connected to the second end of the load unit. The second switch determines whether to provide a start voltage to the reference circuit according to a conducting state thereof. The reset control circuit provides a discharge path between a control end of the first switch and the ground, and conducts the discharge path according to the power voltage during a period when the power voltage is smaller than a threshold voltage.

Abstract: Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.

Abstract: A constant switching current flip-flop includes a latch circuit that provides latch outputs of the flip-flop, whereby the latch outputs are reset to zero at the beginning of each clock cycle to eliminate pattern dependent switching currents. The latch circuit is reset responsive to control signals provided without significant delay.

Abstract: A reset transistor is prevented from being deteriorated when power-down occurs during a programming operation or an erasing operation. It is made possible to protect the reset transistor as well as other transistors in a circuit to which a high voltage is applied when the power-down occurs during the erasing operation on an EEPROM, because the system is not reset all at once based only on a first reset signal POR of a power-on reset circuit, but is reset based on the first reset signal POR and a low voltage detection signal LD from a low voltage detection circuit so that the reset transistor is not turned on while the high voltage is applied to it.

Abstract: A system includes power saving circuitry to revive a system controller from a sleep mode for performance of operations in an active mode. The system also includes a regulator including a floating gate reference device to generate output voltage and current capable of powering the power saving circuitry during the sleep mode. A method includes generating a reference voltage and current with a float gate device, and powering wake-up circuitry with the reference voltage and current while in a power saving mode. The wake-up circuitry is configured to activate a main system controller from the power saving mode.

Abstract: A threshold voltage detection circuit comprises a first inverter, a first transistor, a second transistor, a third transistor and a fourth transistor. The first inverter comprises a first terminal and a second terminal, a first electrode of the first transistor is electrically connected with the second terminal of the first inverter, a fourth electrode of the second transistor is electrically connected with the first terminal of the first inverter, a seventh electrode of the third transistor is electrically connected with the second terminal of the first inverter and the first electrode of the first transistor, a tenth electrode of the fourth transistor is electrically connected with a third electrode of the first transistor and a fifth electrode of the second transistor, and an eleventh electrode of the fourth transistor is electrically connected with a ninth electrode of the third transistor.

Abstract: A start circuit adapted to start a reference circuit including a plurality of bias nodes is provided. The start circuit includes a current source, a current mirror, a load device, and a control device. The current source determines whether or not to generate an internal current according to a plurality of bias voltages on a part of the bias nodes. The current mirror duplicates the internal current to produce a mirrored current. The load device adjusts a control voltage according to the mirrored current. The control device determines whether or not to generate a start voltage according to the control voltage, and transmits the start voltage to one of the part of the bias nodes, so as to break the reference circuit away from a zero-current state.

Abstract: The present invention discloses a reset circuit that has a reset IC 12 having a terminal 2 connected to a reset terminal of the microcomputer 30 that is driven by a constant voltage (3.3V) generated by regulating a rectified voltage (V+) by a regulator 24, and a terminal 4 that inputs the constant voltage (3.3V) thorough a register R1, and outputs a reset signal to the microcomputer 30 when an input voltage input to the terminal 4 is lower than a first threshold value; and a transistor Q1 in which a collector is connected to the terminal 4 through a resistor 2 and an emitter is connected to the ground and the transistor is turned on when an output voltage of the switching transformer 21 is lower than a predetermined level, wherein the voltage lower than the first threshold value is input to the terminal 4 when the transistor Q1 is turned on.

Abstract: There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.

Abstract: A method and apparatus for fail-safe start-up circuit for subthreshold current sources have been disclosed.

Abstract: A driver circuit drives a pulse width modulation (PWM) controller. The driver circuit includes an enabling circuit, a power supply input control circuit, a stabilizing circuit, and a discharge circuit. The stabilizing circuit is electrically connected to the PWM controller. The power supply input control circuit is electrically connected between the enabling circuit and the stabilizing circuit. The discharge circuit is electrically connected between the stabilizing circuit and the ground. In response to the driver circuit working in normal operation, the enabling circuit enables the power supply input control circuit to output a working voltage to the stabilizing circuit, and in response to the process of the driver circuit restarting, the enabling circuit enables the power supply input to stop outputting power supply to the stabilizing circuit. The discharge circuit leads a residual voltage of the stabilizing circuit to the ground, during the process of the driver circuit being restarted.

Abstract: A method of generating a reset signal for an integrated circuit without a dedicated reset pin includes calibrating a first clock pulse from a clock signal, measuring a second clock pulse from the clock signal, measuring a third clock pulse from the clock signal, and generating an internal reset signal if the first clock pulse width is longer than a predetermined minimum clock pulse width, if the second clock pulse is within an expected first value range, and if the third clock pulse is within an expected second value range.

Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. One or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Abstract: An aging detection circuit is disclosed. An aging detection circuit may include at least an inverter and a half-latch. During a power-up sequence, if an input voltage of the first inverter changes sufficiently to cause the output of the inverter to change states, the output of the half-latch may be set to a state indicating aging of the circuit. This indication may be used in determining whether or not a supply voltage should be changed to compensate for the aging. A first transistor of the inverter may be arranged such that it remains active subsequent to power-up of the circuit. When active, the first transistor may be subject to degradation mechanisms associated with aging and which change its threshold voltage. The threshold voltage may change such that on a successive power-ups of the circuit, the first transistor is at least momentarily deactivated, leading to the setting of the state indicating aging by the half-latch circuit.

Abstract: Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.

Abstract: An apparatus includes a first sensing circuit operative to drive a node with a first sample of an input signal during a first phase of a clock signal. The apparatus includes a second sensing circuit operative to drive the node with a second sample of the input signal during a second phase of the clock signal. An output signal on the node includes the first and second samples and has a bit rate that is N times the rate of the clock signal. N is an integer greater than one. In at least one embodiment of the apparatus, during the second phase of the clock signal, the first sensing circuit provides a high impedance to the node, and during the first phase of the clock signal, the second sensing circuit provides a high impedance to the node.

Abstract: A circuit in accordance with one embodiment of the invention can include a variable voltage generator that is coupled to receive an input voltage. Furthermore, the circuit can include a non-volatile memory that is coupled to the variable voltage generator. The non-volatile memory can be coupled to receive programming for controlling an output voltage of the variable voltage generator.

Abstract: A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation.

Abstract: A driving device of a light emitting unit is provided. The driving device includes a driving circuit, a switch, a capacitor, and a compensation circuit. The driving circuit has a control terminal and a driving terminal connected to the light emitting unit. The driving circuit determines a driving current according to the voltage on the control terminal. The switch has a first end for receiving a data voltage, a second end connected to the light emitting unit, and a control end for receiving a scan voltage. The capacitor has a first end connected to the control terminal of the driving circuit and a second end connected to the second end of the switch. The compensation circuit has an output terminal connected to the first end of the capacitor. The compensation circuit supplies a reset voltage to the first end of the capacitor when the switch is turned on.

Abstract: A system can include at least one power supervisor coupled between two supply voltage terminals and including a comparator circuit configured to assert at least one output signal in response to a voltage between the terminals varying from at least one trip voltage, and a memory coupled to a programming interface for storing values that establish the at least one trip voltage; and circuitry coupled between the terminals that receives the at least one output signal, and configured to hold at least a portion of the circuitry in one mode of operation in response to the assertion of at least one output signal.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: A master-slave flip-flop may be operable to sense a signal, received by a slave circuit from a master circuit, at a pair of serially coupled NMOS transistors and/or at a pair of serially coupled PMOS transistors in the slave circuit. The flip-flop may generate a corresponding output signal at an output terminal based on the sensing of the signal received by the slave circuit. The flip-flop may receive, in a feedback path of the slave circuit, a SET signal. An inverted version of the SET signal may be received via a gate terminal of a PMOS transistor in the master circuit. The flip-flop may receive, in a feedback path of the master circuit, a RESET signal. The RESET signal may also be received via a gate of a NMOS transistor in the master circuit. The flip-flop may disable an input terminal utilizing the SET signal and/or the RESET signal.

Abstract: In general, this disclosure describes techniques for implementing a system-wide reset of multiple devices. The techniques ensure that when any one of the devices of the system is reset, all the devices are reset. For example, a system includes a master reset device and a plurality of slave reset devices that are interconnected by a single reset line to provide improved robustness against electrostatic discharge (ESD) and electromagnetic pulse events. The master reset device detects a reset signal on the reset line and retransmits a true reset signal on the reset line in response to detecting the reset signal. Additionally, the master reset device may enter a blocking state after retransmitting the true reset signal to prevent detecting the reset signal that it transmitted on the reset line to avoid reset lockup.

Abstract: A data processing system (100), such as a System-on-Chip, includes a processor (120), a memory (140) that has an expected minimum data retention voltage, and a brown-out detector (160), which includes a brown-out detection circuit (201) that has an analog output, and an output circuit (248 and 252) that converts the analog output of the brown-out detection circuit to a digital brown-out flag. The brown-out detection circuit includes a self-biased current reference, current mirrors, and a current comparator. The brown-out detector monitors voltage of a power supply of the memory, and the brown-out detector asserts the digital brown-out flag to the processor when the voltage of the power supply is at, or slightly above, a highest expected minimum data retention voltage.

Abstract: A signal transmission circuit is provided, which includes a level shifting circuit performing level shifting on an input signal and then outputting the input signal, but which can inhibit the output of an erroneous signal caused by the voltage change of the power source. The level shifting circuit, for individually performing level shifting on a first input signal and a second input signal, and outputting the first input signal and the second input signal as a first shifted signal and a second shifted signal respectively, comprises a first series circuit having a switching element switched according to the first input signal and a resistor, a second series circuit having a switching element switched according to the second input signal and a resistor, and a counter-current preventing portion for preventing a reverse current from flowing from the ground terminal toward the first series circuit and the second series circuit.

Abstract: A semiconductor device includes an internal circuit to perform a predetermined function at a plurality of different supply power voltages, a power supply voltage region detector to detect a supply power voltage to output a detection signal, a latch to store the signal output from the power supply voltage region detector and output the stored signal as a power supply voltage region signal, and a reset circuit to generate a reset signal to perform a predetermined reset operation on the internal circuit. The latch stores the output signal from the power supply voltage region detector just after the reset operation for the internal circuit is released, and the internal circuit changes an internal setting according to the power supply voltage region signal output from the latch.