Abstract: Disclosed herein are a delay latch circuit and a delay flip-flop circuit arranged to inhibit the increase in power consumption while preventing malfunction under low voltage conditions. An internal signal output circuit outputs as an internal signal an inverted signal of a data signal starting from an internal transparency start timing until an internal transparency end timing. From the internal transparency end timing until the internal transparency start timing, the internal signal output circuit outputs a fixed value signal as the internal signal. A transistor delays the output internal signal over a time period which ranges from a hold instruction delay timing to the issuance of a data transparency instruction and which includes the internal transparency end timing therebetween.

Abstract: A brown-out detection circuit includes a first resistive element, a first transistor, a second transistor, and a comparator. The first resistive element has a first terminal coupled to a first power supply voltage terminal, and a second terminal. The first transistor is of a first conductivity type and has a first current electrode coupled to the second terminal of the first resistive element, a control electrode, and a second current electrode. The second transistor is of a second conductivity type and has a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode coupled to a second power supply voltage terminal. The comparator has a first input terminal coupled to the first terminal of the first resistive element, a second input terminal coupled to the second terminal of the first resistive element, and an output terminal for providing a brown-out detection signal.

Abstract: A system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.

Abstract: A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.

Abstract: An initialization circuit comprises a section signal generator generating a section signal, of which a prescribed section is enabled in response to a power-up signal, a first oscillator generating a first period signal in response to the section signal, a first period multiplier generating a first multiplied signal by multiplying a period of the first period signal, and a signal selector transferring the first multiplied signal or a second multiplied signal selectively as a self-refresh enable signal in response to the section signal.

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract: Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus is implemented with a digital electronic component that produces a clock signal. The apparatus also includes a first counter that outputs a first count signal based on the clock signal and a second counter that outputs a second count signal based on the clock signal. The apparatus also includes a power on reset logic that selectively provides a power on reset signal based on the first count signal and the second count signal. The power on reset logic can also selectively disable the apparatus upon providing the power on reset signal.

Abstract: One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.

Abstract: A semiconductor device includes: an input node supplied with an input signal; an output node provided correspondingly to the input node; first and second input circuits coupled in parallel to each other between the input and output nodes; and a control circuit configured to control the first and second input circuits such that one of the first and second input circuits is switched over from an active state to an inactive state and the other of the first and second input circuits is switched over from an inactive state to an active state during the one of the first and second input circuits being still in the active state.

Abstract: A voltage regulator includes a programming interface via which programming instructions may be applied to a processor of the voltage regulator. The voltage regulator operates the processor according to the programming instructions to select one of multiple active internally-generated analog voltage levels to determine an output voltage level of the voltage regulator.

Abstract: Provided is a semiconductor integrated device that selects one or more of a plurality of functional blocks and resets the selected functional block, and a control method of the semiconductor integrated device. The semiconductor integrated circuit includes a functional block that is reset when a clock signal and a reset signal are supplied, a reset signal output unit that outputs the reset signal for resetting the functional block, a clock mask circuit that stops the clock signal to be supplied to the functional block, and a clock mask control circuit that controls the clock mask circuit.

Abstract: A key press detecting circuit for detecting the status of the key is provided. The key press detecting circuit comprises a discharging circuit which discharges when the key (K1) is pressed; and a voltage detecting circuit, which comprises a combination of a PNP transistor (T2) and a NPN transistor (T3), wherein when the discharging circuit discharges for a predefined period, the PNP transistor (T2) will be turn on, which causes the NPN transistor (T3) to be turned on and to output a second signal for a second function.

Abstract: Scan-based reset utilizes already existing design-for-test scan chains to reset control and logic circuitry upon reset conditions, such as power-up reset. Such utilization eliminates the need for expensive, high fan-out reset trees and per scan cell reset control logic, thus reducing chip area and power consumption. Additional power savings is achieved by controlling clock frequency during reset conditions. Limiting scan cell chain length and providing multiple chains reduces reset latency.

Abstract: A clock management unit includes a delay unit; and an output unit, wherein the delay unit receives a clock signal and a reset signal for resetting an external circuit, and supplies a delayed reset signal to the output unit, wherein the output unit supplies to the external circuit an external clock signal obtained by processing the clock signal and the delayed reset signal, and wherein the external clock signal does not experience any edge transitions during at least two periods of the clock signal after the reset signal transitions to an active state for resetting the external circuit.

Abstract: A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

Abstract: A frequency divider section generates a frequency-divided clock RSELO by dividing the frequency of an internal clock LCLK, which lags behind an external clock in phase, and generates a delayed frequency-divided clock RSELI by delaying the frequency-divided clock RSELO. A signal input from the outside in synchronization with an internal clock PCLK which lags behind the external clock in phase is held in a latch circuit in synchronization with the delayed frequency-divided clock RSELI. Then, an output signal of the latch circuit is read into a latch circuit in synchronization with the frequency-divided clock RSELO and is output as a signal which is synchronized with the internal clock LCLK. In addition, a frequency divider section includes a variable divider which divides the frequency of the internal clock LCLK by a predetermined divide ratio which can be changed.

Abstract: A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transisto

Abstract: A power-up signal generating circuit of a semiconductor memory apparatus includes a current source unit configured to supply a current to a first node; a current sink unit configured to be turned on when the level of a divided voltage dividing an external voltage is equal to or higher than a predetermined level to allow the current to flow from a first node to a second node; a control unit configured to control the turn-on timing of the current sink unit by controlling a voltage level of the second node; and a signal generating unit configured to enable a power-up signal depending on a voltage level of the first node.

Abstract: An intelligent voltage regulator circuit in accordance with one embodiment of the invention can include a variable voltage generator that is coupled to receive an input voltage. Additionally, the intelligent voltage regulator circuit can include a processing element that is coupled to the variable voltage generator. The processing element can be coupled to receive programming for controlling a characteristic of the intelligent voltage regulator circuit. The processing element can be for dynamically changing the characteristic during operation of the intelligent voltage regulator circuit.

Abstract: A power supply voltage reset circuit, provided in an apparatus having an internal circuit capable of adjusting an internal power supply voltage, for resetting the internal circuit when a power supply voltage of the apparatus rises, and includes: a unit that generates an internal power supply voltage reference signal and changes a signal level thereof; a unit that generates an internal reference voltage to be a reference level in generating a reset signal for the internal circuit at a time of rising of the power supply voltage; a unit that generates a power-on adjustment voltage which rises later than the internal reference voltage at the time of rising of the power supply voltage and becomes greater than the internal reference voltage after a predetermined time passes; and a unit that generates the reset signal by comparing the internal reference voltage with the power-on adjustment voltage.

Abstract: A starting apparatus includes: a storage unit storing an identifier; a rectifying unit rectifying a reception signal; a generating unit comparing the reception signal rectified in the rectifying unit to a reference signal and generating a digital signal from the reception signal; a judging unit judging whether or not the digital signal contains information of the identifier; a reference changing unit changing the reference signal when the judging unit judges that the reception signal does not contain information of the identifier; and a start instructing unit instructing start of an electric appliance when the judging unit judges that the reception signal contains information of the identifier.

Abstract: A system reset circuit and a method for resetting a system automatically according to an operation state of the system are provided. The system reset circuit includes a system, which is triggered by a first logic state during an operation of a program and a second logic state at termination of the program, for generating a trigger signal for maintaining the first logic state in a lockup state and a counter for receiving the trigger signal as an enable signal, for counting a period of the first logic state of the trigger signal, and for clearing the counting for a period of the second logic state, and of which an output node is connected to a reset node of the system, wherein, when the first logic state period of the trigger signal is maintained before the counter expires, the system generates a reset signal automatically.

Abstract: A circuit in accordance with one embodiment of the invention can include a variable voltage generator that is coupled to receive an input voltage. Furthermore, the circuit can include a non-volatile memory that is coupled to the variable voltage generator. The non-volatile memory can be coupled to receive programming for controlling an output voltage of the variable voltage generator.

Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Abstract: Provided is a delay circuit that has a delay time period independent of a power supply voltage and has the equal delay time period between a case of a change in input signal from Low to High and a case of a change in input signal from High to Low. The delay time period is determined as a time period necessary for a voltage of a capacitor (17) (internal voltage (Va)) to increase from a ground voltage (VSS) to a voltage equal to or higher than an inverting threshold voltage of a constant current inverter (19) (threshold voltage (Vtn) of an NMOS transistor (16)). Therefore, the delay time period is determined with reference to the ground voltage (VSS). Note that the same holds true for an internal delay circuit (20). If the input signal (Vin) becomes High, the delay circuit utilizes the delay time period caused by an internal delay circuit (10). On the other hand, if the input signal (Vin) becomes Low, the delay circuit utilizes the delay time period caused by the internal delay circuit (20).

Abstract: Methods, devices, modules, and systems for a band-gap reference voltage detection circuit are provided. One embodiment for a band-gap reference voltage detection circuit includes a Brokaw cell having a band-gap reference voltage, and a circuit portion for indicating the magnitude of an input voltage signal with respect to the band-gap reference voltage. The input voltage is applied to transistor bases of the Brokaw cell.

Abstract: An intelligent power-on reset circuit in accordance with one embodiment of the invention can include a programmable voltage divider. The intelligent power-on reset circuit can also include a comparator that is coupled to the programmable voltage divider and that is coupled to receive a reference voltage. Furthermore, the intelligent power-on reset circuit can include a processing element that is coupled to the programmable voltage divider. The processing element can be coupled to receive programming for controlling a characteristic of the intelligent power-on reset circuit. The processing element can be for dynamically changing the programming during operation of the intelligent power-on reset circuit.

Abstract: An electronic device includes a signal generator and a processing module. The signal generator generates reset signals to reset the processing module. The signal generator includes a first capacitor, a second capacitor, and a switching unit. The first capacitor receives an input voltage and charges accordingly when the electronic device is powered on. The second capacitor generates the reset signals based on the input voltage. The switching unit transmits the input voltage to the second capacitor to charge the second capacitor when the electronic device is powered on, and grounds the second capacitor after the electronic device is powered off. The reset signals are generated during the charging and discharging process of the second capacitor.

Abstract: A programmable power-on reset circuit in accordance with one embodiment of the invention can include a programmable voltage divider. The programmable power-on reset circuit can also include a comparator that is coupled to the programmable voltage divider and that is coupled to receive a reference voltage. Additionally, the programmable power-on reset circuit can include a non-volatile memory that is coupled to the programmable voltage divider, wherein the non-volatile memory can be coupled to receive programming for controlling an output of the programmable voltage divider.

Abstract: A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal.

Abstract: An integrated circuit, comprises a wakeup terminal; a supply voltage terminal configured to receive a supply voltage; and a power control circuit. The power control circuit comprises an enable circuit coupled to the wakeup terminal and configured to generate a voltage monitoring enable signal as a response to a wakeup signal received at the wakeup terminal, and a voltage monitoring circuit for generating a supply voltage level indication signal. The voltage monitoring circuit is coupled to the supply voltage terminal and comprises an operation switch controlled by the voltage monitoring enable signal. The voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and set the supply voltage level indication signal accordingly. The integrated circuit further comprises processing circuitry, with the supply voltage level indication signal controlling the switching between a normal operation state and a standby state of the processing circuitry.

Abstract: A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is detected. In an illustrative embodiment, the scrubber corrects for upsets in a circuit comprised of a plurality of redundant circuits, each redundant circuit including a data port for receiving data and a load enable port for controlling when the redundant circuit should load new data. The fault detection logic processes the outputs from each of the redundant circuits and outputs a fault detect signal indicating whether an upset has been detected in one or more of the redundant circuits. The fault detect signal is coupled to the load enable ports, forcing the redundant circuits to immediately reload with corrected data from a voter or with new incoming data when an upset is detected.

Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.

Abstract: The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.

Abstract: A power-up circuit for a semiconductor memory device includes a voltage division unit configured to divide a power supply voltage, a first power-up generation unit configured to detect a voltage level of a first divided voltage of the voltage division unit during an initial stage of applying a power supply to generate a first power-up signal and a second power-up generation unit configured to detect a voltage level of a second divided voltage of the voltage division unit, after the first power-up signal is generated from the first power-up generation unit, to generate a second power-up signal.

Abstract: Methods for controlling a Power On Reset (POR) circuit in an Integrated Circuit (IC) are presented. In one embodiment, a method includes an operation for gating a test POR signal configured to selectively disable an output of a POR circuit, and an operation for programming a fuse. The programming of the fuse includes operations for disabling the signal path of the test POR signal, and for enabling the output of the POR circuit. In another embodiment, the signal path of the test POR signal includes a pass gate, where permanently disabling the signal path is performed by disconnecting the pass gate.

Abstract: A reset signal generating circuit for a processor includes a charging circuit, a discharging circuit, and a triggering circuit. The charging circuit receives timing pulse signals from the processor to supply charging current according to the timing pulse signals when the processor operates normally, and stops supplying the charging current when the processor is at fault. The discharging circuit buffers the charging current supplied by the charging circuit when the processor operates normally, and discharges a low voltage to the triggering circuit when the processor is at fault. The triggering circuit outputs a trigger signal to the processor when the triggering circuit detects the low voltage to reset the processor.

Abstract: An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

Abstract: A delay circuit is used for receiving an input signal from a signal source. The delay circuit includes a delay unit, a switch unit, and a generator. The switch unit is used for receiving a voltage from a power supply and selectively transmitting the voltage to the delay unit according to the input signal. The generator is coupled to the power supply for generating an output signal. The output signal is equivalent to the input signal that is delayed for a predetermined time period. Wherein the delay unit is used for generating an electrical signal according to the voltage and transmitting the electrical signal to the generator. The delay unit includes an adjustable capacitor coupled between ground and an interconnection of the switch unit and the generator. An electronic device including the delay circuit is also provided.

Abstract: An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.

Abstract: A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit.

Abstract: Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.

Abstract: A communication system comprises a twisted pair communication link operably coupled to at least two driver stages for providing at least two independent input signals on the twisted pair communication link. The at least two independent input signals on the twisted pair communication link are summed and input to a comparator arranged to compare the summed signal to a reference value. The output of the comparator is input to the at least two driver stages. The outputs from the at least two driver stages are summed and fed back and summed with one or more of the independent input signals. In this manner, adverse effects due to non-ideal symmetry between components in a twisted pair communication link, such as a Controller Area Network system, are reduced.

Abstract: A controller which has functions of remote control, multiple protection and PWM inside. The controller can shut down and latch the converter, when a failure happens (such as under voltage and over voltage of output, and over power protection). But, under-voltage and over-power protection will also happen when Vin is decreased by AC interruption or Vin source is removed. This invention is to provide a method to reset the latch protection by detecting Vin and Vo voltage.

Abstract: A power-up signal generating circuit includes a detecting unit configured to output a bias signal having a voltage level corresponding to an external power voltage in response to an internal voltage and a deep power down (DPD) signal; and a signal generating unit configured to generate a power-up signal having a logic level corresponding to the voltage level of the external power voltage in response to the DPD signal and the bias signal, wherein the internal voltage increases during an activation time of the power-up signal to reach a predetermined voltage level after a predetermined time, and maintains a ground voltage level during an inactivation period of the power-up signal.

Abstract: An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.

Abstract: There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.

Abstract: A level shifter receives an input signal of either a first lower voltage or a first upper voltage which form a voltage pair, and level-shifts the input signal to output an output signal of either a second lower voltage or a second upper voltage. An SR flip-flop generates an output signal which is switched to the second upper voltage upon receiving a positive edge via its set terminal, and is switched to the second lower voltage upon receiving a positive edge via its reset terminal. An AND gate generates the logical AND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, which is output to the set terminal of the SR flip-flop. A NOR gate generates the logical NOR of the feedback signal and the input signal, which is output to the reset terminal of the SR flip-flop.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.