Abstract: Implementations of the present disclosure involve a semi-dynamic flip-flop circuit incorporating a partially floating evaluation window that provides a faster data to output delay, a PMOS keeper device may be placed in series with an existing keeper circuit of the semi-dynamic flip-flop circuit. The gate of the PMOS series keeper device may be connected to a shut-off signal of the semi-dynamic flip-flop circuit that provides a three gate delay, self-timed positive pulse to control the keeper circuit. The PMOS series keeper device effectively turns off the keeper circuit when the clock signal rises but turns in back on after a three gate delay to sustain the precharge state of the dynamic node. The effective turning on and off of the keeper circuit portion may decrease the data to output delay of the flip-flop, resulting in higher performing microprocessors.

Abstract: A latch device is provided with a relay and a shadow latch. The relay has an input to accept a binary relay input signal, an input to accept a clock signal, an input to accept a shadow-Q signal, and an output to supply a binary Q signal value equal to the relay input signal value. The relay output is supplied in response to the relay input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the relay input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal with a value equal to an inverted Q signal value. The shadow latch output is supplied in response to the relay input signal and clock signal.

Abstract: A counter circuit is provided that can switch delay times by use of a simple circuit configuration. A counter circuit includes plural stages of flip flops connected in cascade, in which a flip flop in a first stage receives a clock from an oscillator as an input signal, and a flip flop in a given stage after the first stage receives a Q output of a preceding stage as an input signal, wherein all or part of the plural stages of flip flops receive a mode signal, and wherein each of the plural stages of flip flops divides by 2 a frequency of the received input signal for output as a Q output when the mode signal indicates a normal delay mode, and each stage of the flip flops that receives the mode signal allows through passage of the received input signal for output as a Q output when the mode signal indicates a delay shortened mode.

Abstract: A scannable latch circuit is disclosed. In one embodiment, the scannable latch circuit includes a master latch, a slave latch, and a gating circuit coupled between the master latch and the slave latch. The slave latch may be implemented to support scan-shifting for test operations. Scan data received by the master latch may be provided to the slave latch through the gating circuit. The gating circuit may enable data to be transferred from the master latch to the slave latch when a scan enable signal is asserted. When the scan enable signal is deasserted, the gating circuit may cause the slave latch to output a constant (i.e. unchanging) state, regardless of the state of data stored in the master latch. This may result in power savings by inhibiting the slave latch from making state changes when scan-shifting operations are not in progress.

Abstract: A device (300, 1000) provides a dual-edge triggered flip-flop (DETFF) that is reconfigurable to a master-slave flip-flop (MSFF). The device includes a reconfigurable MUX-D flip-flop including two distinct circuit configurations. In a first configuration, two latches or storage elements (340, 360, 1040, 1060) are operating in series to provide a MUX-D flip-flop. In a second configuration, the storage elements (340, 360, 1040, 1060) are operating in parallel to provide a dual-edge triggered flip-flop (DETFF).

Abstract: Storage circuitry is provided with increased resilience to single event upsets, along with a method of operation of such circuitry. The storage circuitry has a first storage block configured in at least one mode of operation to perform a first storage function, and a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function. Configuration circuitry is responsive to a predetermined mode of operation where the second storage function is unused, to configure the second storage block to operate in parallel with the first storage block. By arranging the two storage blocks in parallel when one of the storage blocks is otherwise performing no useful function, this in effect increases the size of the storage block that is still performing the useful storage function, and as a result increases its resilience to single event upsets.

Abstract: A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: A low-hysteresis high-speed latch circuit is disclosed which isolates a sample stage and hold stage from one another during a latch clock phase and simultaneously shorts the output nodes together during the latch clock phase to reduce hysteresis of the latch.

Abstract: A master-slave flip-flop circuit is provided with a retention capability to support operation in both a normal mode and a retention mode. During the retention mode the retention circuitry drives the output signal via either a first path 16 or a second path 22, 24, 4, 10 in dependence upon the phase of the clock signal. During both phases of the clock signal the output signal is driven in a well defined state to reflect the signal stored within the retention circuitry. There is thus provided a clock independent retention master-slave flip-flop circuit. Both high density and high speed variants of the flip-flop circuit may use the technique.

Abstract: A scannable storage circuit includes a scan enable input, a storage element having a Node coupled to a data output buffer for driving a data output terminal. The data output buffer includes an inverter; a transmission gate having a first MOS transistor and a second MOS transistor with sources and drains coupled to each other, drains coupled to an output of the inverter and sources coupled to the data output terminal and gates coupled to the scan enable input and an inverted scan enable input. A third MOS transistor and a fourth MOS transistor is coupled to the sources of the first and second MOS transistors, the third MOS transistor and fourth MOS transistor are configured to pull up or pull down the data output terminal in response to a first control signal and a second control signal respectively. A scan output is generated from the output of the inverter.

Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

Abstract: A flip-flop circuit includes a master latch, a master/slave gate, a slave latch, a slave gate, a feedback latch, and a master gate. The master latch has an input and an output. The master/slave gate has an input coupled to the output of the master latch and an output. The slave latch has input coupled to the output of the master/slave gate and an output. The slave gate has input coupled to the output of the slave latch and an output. The has an input coupled to the output of the slave gate and an output. The master gate has an input coupled to the output of the feedback latch and an output coupled to the input of the master latch.

Abstract: A level shifting flip-flop for generating a level-shifted output signal based on an input signal includes a master stage and a slave stage. The slave stage has an integrated level shifting circuit. The slave stage level shifts a signal as it passes through the flip-flop, which eliminates the need of level shifting the signal after it is output from the flip-flop.

Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a low-clock-energy latch circuit that is fully static. The clock is only coupled to a first clock-activated pull-up or pull-down transistor and a second clock-activated pull-down or pull-up transistor. The level of the input signal is captured by a storage sub-circuit on one of the rising or the falling clock edge and stored to generate an output signal until the clock transitions. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled and disabled by the first clock-activated transistor and a propagation sub-circuit is activated and deactivated by the second clock-activated transistor.

Abstract: A method and circuit for operating a bistable latch are provided. The state of input data is latched on a first edge of a clock signal. In response to every first edge of the clock signal, a control circuit causes power boost circuit to couple first and second complementary output nodes of the bistable latch to a power source. In response to detecting stable operation of the bistable circuit, the control circuit causes power boost circuit to decouple the first and second complementary output nodes from the power source.

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract: According to one embodiment, a semiconductor integrated circuit is provided, which has mounted thereto a flip-flop circuit including a latch portion that takes and holds input data based upon a clock signal, and a clock portion that inputs the clock signal to the latch portion, wherein an active region of the flip-flop circuit is divided in such a manner that the width of the active region is secured, and each of the active regions has uniform width.

Abstract: A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal.

Abstract: A semiconductor device includes a flip-flop circuit formed in a CMOS semiconductor integrated circuit. The flip-flop circuit includes at least a first clock generating inverter that generates a first clock signal and a second clock generating inverter that generates a second clock signal obtained by inverting the first clock signal, the first clock generating inverter and the second clock generating inverter are arranged so as to sandwich a latch unit, the latch unit including a master latch unit and a slave latch unit in the flip-flop circuit, the first clock generating inverter and a first other circuit in the flip-flop circuit are configured to share a source region, the first other circuit being adjacent to the first clock generating inverter, and the second clock generating inverter and a second other circuit in the flip-flop circuit are configured to share a source region, the second other circuit being adjacent to the second clock generating inverter.

Abstract: A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series.

Abstract: A master-slave flip-flop may be operable to sense a signal, received by a slave circuit from a master circuit, at a pair of serially coupled NMOS transistors and/or at a pair of serially coupled PMOS transistors in the slave circuit. The flip-flop may generate a corresponding output signal at an output terminal based on the sensing of the signal received by the slave circuit. The flip-flop may receive, in a feedback path of the slave circuit, a SET signal. An inverted version of the SET signal may be received via a gate terminal of a PMOS transistor in the master circuit. The flip-flop may receive, in a feedback path of the master circuit, a RESET signal. The RESET signal may also be received via a gate of a NMOS transistor in the master circuit. The flip-flop may disable an input terminal utilizing the SET signal and/or the RESET signal.

Abstract: A multi-threshold complementary metal-oxide semiconductor technology (MTCMOS technology) master slave flip-flop with a single clock signal includes a master storage element configured to store an input data in response to a clock signal transition and a slave storage element configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition. The master storage element includes low threshold voltage transistors, the slave storage element includes high threshold voltage transistors, and the master and the slave storage elements are provided with a single clock signal.

Abstract: A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.

Abstract: A semiconductor device includes: a first master-slave flip-flop having a first master latch which receives and latches first data signal in synchronism with first clock and a first slave latch which receives and latches the first data signal from the first master latch in synchronism with second clock; and a second master-slave flip-flop disposed side by side with the first master-slave flip-flop and having a second master latch which receives and latches second data signal in synchronism with third clock and a second slave latch which receives and latches the second data signal from the second master latch in synchronism with fourth clock, and wherein the second slave latch of the second master-slave flip-flop is disposed adjacent to the first master latch of the first master-slave flip-flop and the second master latch of the second master-slave flip-flop is disposed adjacent to the first slave latch of the first master-slave flip-flop.

Abstract: A digital logic circuit includes a logic element for providing a data signal, a clock for providing a clock signal and a master-slave flip-flop. The master-slave flip-flop includes a master latch for storing data on a master latch input at a first active edge of the clock signal and a slave latch for storing data on an output of the master latch at a second active edge of the clock signal following the first active edge. A timing error detector asserts an error signal in response to a change in the data signal during a detection period following the first active edge of the clock signal. A timing correction module selectively increases a propagation delay of the data signal from the logic element to the master latch input in response to the error signal.

Abstract: A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals.

Abstract: Disclosed is a low power latch that includes a low threshold voltage (LThV) inverter inverting an input data value to provide an output data value and including a LThV pull-up transistor and LThV pull-down transistor that operate at a threshold voltage less than a reference threshold voltage. The low power latch also includes a high threshold voltage (HThV) transistor isolating unit configured to isolate a power supply voltage provided to the LThV inverter during a sleep mode indicated by a sleep mode signal, and including a first HThV transistor and a second HThV transistor that operate at a threshold voltage less than the reference threshold voltage.

Abstract: A power-gated retention flop circuit is disclosed. In one embodiment, a retention flop includes a first latch coupled to a first global voltage node and a virtual voltage node and configured to receive a data input signal, and a second latch coupled to receive the data input signal from the first latch, wherein the second latch is coupled to the first global voltage node and a second global voltage node. The second latch is configured to provide a data output signal based on the data input signal. A power-gating circuit is coupled between the virtual voltage node and the second global voltage node, wherein the power-gating circuit is configured to, when active, couple the virtual voltage node to the second global voltage node. Thus, the first latch may be powered down while the second latch remains powered on.

Abstract: A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch includes a tracking cell and a locking cell. In a first embodiment, the locking cell includes two complementary logic inverters and two transmission gates. When the locking cell is locked, the two gates are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates. Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second and third embodiment, the tracking cell involves a pair of inverters. The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.

Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Abstract: A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops.

Abstract: A prescaler circuit according to an exemplary aspect of the present invention includes a first flip-flop circuit that detects second output data and outputs the detected data as first output data, and a second flip-flop circuit that detects the first output data and outputs the data as the second output data. The first flip-flop circuit includes a master-side latch circuit that generates intermediate data, a slave-side latch circuit that detects the intermediate data and outputs the data as the first output data, and a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4. The master-side latch circuit generates the intermediate data based on the second output data and the control signal.

Abstract: A D flip-flop (DFF), a method of operating a DFF, a latch and a library of standard logic elements including standard logic elements corresponding to a DFF and a latch. In one embodiment, the DFF has a data input and a data output and includes: (1) a master stage passgate coupled to the data input, (2) a master stage coupled to the master stage passgate and having a hysteresis inverter with feedback transistors of opposite conductivity, (3) a slave stage passgate coupled to the master stage and (4) a slave stage coupled between the slave stage passgate and the data output and having a hysteresis inverter with feedback transistors of opposite conductivity.

Abstract: A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master circuit, where the always-on balloon circuit includes a common sub-circuit shared with the master circuit. The master circuit writes into the always-on balloon circuit when the single sleep mode signal is activated, and the master circuit reads from the always-on balloon circuit when the single sleep mode signal is deactivated. The always-on balloon circuits comprises high threshold voltage transistors, while the slave circuit comprises low threshold voltage transistors. The master and slave circuits have no leakage current, or substantially no leakage current, after the single sleep mode signal is activated.

Abstract: A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current.

Abstract: A multi-threshold complementary metal-oxide semiconductor technology (MTCMOS technology) master slave flip-flop with a single clock signal includes a master storage element configured to store an input data in response to a clock signal transition and a slave storage element configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition. The master storage element includes low threshold voltage transistors, the slave storage element includes high threshold voltage transistors, and the master and the slave storage elements are provided with a single clock signal.

Abstract: A semiconductor integrated circuit having a flip-flop with improve soft error resistance, including a controller which controls a clock signal generating circuit to output a first clock signal and a second clock signal with a timing so that logic of data retained in a first data retaining terminal becomes identical to logic of data retained in a third data retaining terminal, and then turns on a first switching circuit to connect between the first data retaining terminal and the first data retaining terminal.

Abstract: A prescaling stage includes bistable circuit in turn including respective master and slave portions inserted between a first and a second voltage reference and feedback connected to each other. Each portion is provided with at least one differential stage supplied by the first voltage reference and connected, by a transistor stage, to the second voltage reference, as well as a differential pair of cross-coupled transistors, supplied by output terminals of the differential stage and connected, by the transistor stage, to the second voltage reference. Advantageously, each master and slave portion includes a degeneration capacitance inserted in correspondence with respective terminals of the transistors of the differential pair.

Abstract: A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node.

Abstract: A flip-flop circuit operates by a first clock signal whose amplitude is smaller than that of input data D. A pair of transistors receive the input data D and the reversed input data *D, respectively, to latch the input data D. An activation circuit activates the pair of transistors in a conduction state. A control circuit receives the first clock signal and sets the activation circuit to a conduction state for a predetermined time period starting from an edge timing of the received first clock signal. The control circuit increases the amplitude of the first clock signal and sets the activation circuit in a conduction state by using a second clock signal which is the first clock signal with the increased amplitude.

Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Abstract: A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops.

Abstract: A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and standby mode operation. The system further comprises a standby mode control circuit to control the state of the master and slave flip flops during active and standby mode operation based on at least two control signals. A first transfer gate determines the current flow to and from the master flip flop based on the output of the standby mode control circuit. Similarly, a second transfer gate determines current flow to and from the slave flip flop based on the output of the standby mode control circuit. A first power supply powers the master flip flop during active mode operation.

Abstract: A flip-flop circuit has a function of respectively switching ON/OFF state of operation of a first data retaining circuit in a master side element and a second data retaining circuit in a slave side element, i.e., constituent elements of the flip-flop circuit, wherein the flip-flop circuit performs timing control, so as to reduce unnecessary current, eliminate the affect caused by parasitic capacitance. The flip-flop circuit operates with a low power consumption but has a high maximum operating frequency.

Abstract: A master stage 101 comprises a differential circuit composed of transistors 1 and 2, a differential circuit composed of transistors 3 and 4, a differential circuit composed of transistors 5 and 6, a load circuit 7 (a first load circuit), a load circuit 8 (a second load circuit), and a current source transistor 9. The load circuit 7 (the first load circuit) is composed of an inductor 7A (a first inductor), an inductor 7B (a fifth inductor), and a capacity 7C (a first capacity). The inductor 7B and capacity 7C cooperates together in forming a parallel resonance circuit (a first LC parallel resonance circuit), while the parallel resonance circuit is connected in series to the inductor 7A.

Abstract: Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle.

Abstract: The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Abstract: A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path.