Abstract: A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series.

Abstract: A semiconductor device has a first latch circuit, a second latch circuit configured to receive an output of the first latch circuit, a first switching element provided between the first latch circuit and the second latch circuit, a feedback line for feeding data held by the second latch circuit to the first latch circuit, and a second switching element provided on the feedback line.

Abstract: A low power flip-flop circuit and its operation are described. In one example, the circuit includes a clocked gate for producing an output in response to an input when a clock is received, and a clock control circuit to receive the clock and the input, to determine whether the output will be changed by the input and to provide the clock to the clocked gate if the output will be changed by the input.

Abstract: A shift register including a plurality of stage circuits is provided. Each of the stage circuits has a shift circuit for receiving an input signal and providing an output signal. The output signal is obtained through the logic calculation and delaying of the input signal. Each of the stage circuits, except the first one, further includes a logic circuit used to produce at least one control signal according to the internal signals of the containing stage circuit, so as to replace at least one of the required clock signals during the operation of the corresponding shift circuit.

Abstract: A latch circuit (1) comprising a first input device (10a) in a first branch (4a) and a second input device (10b) in a second branch (4b). The latch circuit comprises a first estimator unit (40a) adapted to generate a first estimate of a current generated by the first input device (10a) and a second estimator unit (40b) adapted to generate a second estimate of a current generated by the second input device (10b). The latch circuit further comprises a control-voltage unit (50) operatively connected to the first and the second estimator unit (40a, 40b). The control-voltage unit is adapted to generate a control voltage based on a sum of the first estimate and the second estimate. Further, the latch circuit (1) comprises a first and a second voltage-controlled current unit (30a, 30b) adapted to generate currents at least based on the control voltage. The first voltage-controlled current unit (30a) is operatively connected to the first branch (4a).

Abstract: A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D?). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q?). One of the outputs (Q?) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.

Abstract: A master-slave circuit that includes a master circuit having input data stored therein, a storage unit for receiving the input data in response to receiving a sleep mode setting signal that sets a sleep mode, and for storing the input data, and a first control unit for interrupting the supply of a power supply voltage to the master circuit after the input data is stored in the storage unit.

Abstract: A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch.

Abstract: The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

Abstract: A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.

Abstract: To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a master latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.

Abstract: In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and the second NMOS transistor are connected to input data. A gate of the third NMOS transistor is connected to a clock pulse signal. A logic level of a first intermediate node between the first PMOS transistor and the second NMOS transistor is latched by a first latch. The flip-flop further includes a fourth PMOS transistor and fifth and sixth NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the fourth PMOS transistor and the fifth NMOS transistor are connected to the first intermediate node. A gate of the sixth NMOS transistor is connected to the clock pulse signal.

Abstract: A logic processing circuit including a plurality of flip-flop including a front stage flip-flop and a rear stage flip-flop, a logic gate circuit network adapted to process data stored in the front stage flip-flop, a result of the process being stored in the rear stage flip-flop, and switching means for switching between a power-on period and a power-off period, the power-on period being a period in which power is being provided to the logic gate circuit network, the power-on period corresponding to either a low-level state period of a clock signal or a high-level state period thereof, the power-off period being a period in which the power is being turned off, the power-off period corresponding to the state period other than the state period corresponding to the power-on period.

Abstract: A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level inverted from that of the digital data signal within a period within which the clock has a second level; a second control stage configured to output a signal of a first level within the period within which the clock has the second level and a signal of a level within another period within which the clock has the first level; a third control stage configured to output an output signal of the first level within a period within which the signal outputted from the second control stage has the second level; and a phase adjustment circuit configured to adjust the phase to produce a second clock and supply the second clock to the third control stage.

Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes an L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Abstract: An edge triggered system is provided having a data and scan input includes a latch device having a clock input and an AND gate, coupled to the latch device, structured and arranged to receive a first clock signal and an inverted clock signal to generate a clock to the clock input. A process for operating an edge triggered system having a data and scan input includes forwarding a first clock signal to an input of an AND gate. The method includes inverting a second clock signal forwarded to another input of the AND gate and generating a clock input for a latch device from the AND gate.

Abstract: A master-slave type flip-flop circuit consisting of a master latch and a slave latch, wherein the master latch comprises: a first clocked inverter to which data are input and a first latch circuit configuring a closed circuit with a first inverter and a second clocked inverter so that an output of the first clocked inverter is input to the first inverter and; the slave latch comprises: a transmission gate to which an output from the first latch circuit is input and a second latch circuit configuring a closed circuit with a second inverter and a third clocked inverter so that an output of the transmission gate is input to the second inverter, respective components configuring the master latch and the slave latch are configured with Sea Of Gate (hereinafter to be referred to as SOG) configuring a gate array, a basic cell of the SOG consists of triplely arrayed N-type transistors and corresponding triplely arrayed P-type transistors, the triplely arrayed N-type transistors consist of double-arrayed normally size

Abstract: A multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) flip-flop, a circuit including the MTCMOS flip-flop, and a method of forming the MTCMOS flip-flop are disclosed. The MTCMOS flip-flop breaks a leakage current path during a sleep mode to retain an output data signal. The MTCMOS flip-flop typically further uses a data feedback unit to retain the output data signal.

Abstract: A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-slave flip-flop can be reduced. Since the master latch is formed from a static circuit, data can be held stably during the standby time by setting the master latch in a data holding state.

Abstract: The present invention is a scan flip-flop circuit with extra hold time margin. The scan flip-flop circuit includes a multiplexer, a sense amplifier and a latch. The latch includes a generation unit for generating an output signal in response to a first signal and a second signal outputted from the sense amplifier, and a storage unit receives the second signal and the output signal and maintains the output signal of the latch when the first signal and the second signal are non-activated.

Abstract: Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or not the bypass signal is activated. A latch circuit latches input data based on the first and second output signals. A latch controller logically operates the bypass signal and input data to generate a third output signal having a different state depending on whether or not the bypass signal is activated. An output controller is switched in response to the states of the first and second output signals for logically combining an output signal selected from the latch circuit and the third output signal to provide the output signal.

Abstract: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Abstract: A flip-flop has a master stage and two slave stages coupled to receive complementary outputs from the master stage. Each stage includes transfer gates and a bistable element in the form of cross-coupled inverters. The master stage bistable element switches states on a first edge of a clock signal in response to the state of a digital data input signal. The slave stage bistable elements switch states on a second dege of the clock signal in response to respective complemenary outputs from the master stage.

Abstract: A latch or flip flop circuit with an increased operating frequency is disclosed. In particular, the operating frequency of the latch is increased by reducing the set up time of the latch circuit. A regenerative circuit is provided between the transmission gate of the latch circuit and the data output. The regenerative circuit comprises a pull up circuit and a pull down circuit. The circuit arrangement of the present invention may be applied to flip flop or latch circuits in combination with other flip flop or latch circuits such as a Master-Slave configuration.

Abstract: The invention provides a design method for reducing phase noise of an electronic circuit comprising a master section and a slave section, said sections including SOI type transistors, characterised in that, first, the floating body transistors which are involved in the degradation of said phase noise are located, then their floating body is set to a potential by means of an appropriate connection, in order to locally reduce their contribution to the overall phase noise of said circuit. It also provides a reduced phase noise master-slave circuit. This circuit includes floating body SOI type transistors, characterised in that the potential of said floating body of the transistors that (60, 61) contribute to said phase noise is set by means of an appropriate connection (64, 65).

Abstract: Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, master-slave flip-flops, digital logic circuits, memory devices and other circuits. In one aspect of the invention, a master-slave flip-flop is constructed using one or more nanotube switching element-based storage devices. The master storage element or the slave storage element or both may be constructed using nanotube switching elements, for example, using two nanotube switching element-based inverters. The storage elements may be volatile or non-volatile. An equilibration device is provided for protecting the stored data from fluctuations on the inputs. Input buffers and output buffers for data storage circuits of the invention may also be constructed using nanotube switching elements.

Abstract: A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.

Abstract: Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

Abstract: For retaining an output data signal of a data retention cell in a power-saving mode, a slave latch unit of the data retention cell is powered with a real power for preserving the output data signal. The output data signal is furnished backward to an input control circuit of the data retention cell. The data signal furnished to a master latch unit of the data retention cell is controlled to switch between an input data signal and the output data signal by the input control circuit in response to a retention signal. The switching of the data signal for refreshing the master latch unit is delayed by a delay unit of the input control circuit, which functions to make sure that the data-preserving process is properly operated on any transition from the power-saving mode to a power-active mode.

Abstract: A latch circuit includes a voltage driven type data reading unit and a voltage driven type data holding unit, and operates based on a clock signal that is supplied from an outside source. The data reading unit reads both a first input data and a second input data, and outputs both a first output data and a second output data based on both the first input data and the second input data, while the data holding unit holds both the first output data and the second output data. Both the first input data and the second input data are differential signals, and both the first output data and the second output data are differential signals that have phases that are inverted.

Abstract: A lookup table (LUT) is programmable to function as a flip-flop. The LUT includes a plurality of memory cells, a plurality of transmission gates, and first and second logic gates. The transmission gates are coupled between the memory cells and an output terminal of the LUT to form a multiplexer circuit selecting one of a plurality of values stored in the memory cells and providing the selected value to the output terminal. First and second logic gates are included in two of the paths through the multiplexer, also providing first and second feedback paths within the LUT. These feedback paths enable the programmable implementation of first and second latches that form the flip-flop. Another subset of the memory cells can be optionally used to implement a function that drives the data input of the flip-flop.

Abstract: Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.

Abstract: A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two repeater clock signals. The flop repeater circuit including a plurality of transistors and inverters coupled together to function as a flip-flop circuit that passes data without any full transmission gates.

Abstract: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to electrical ground. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to electrical ground. When a clock signal is in a first state, the first single transistor is activated to preset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to preset the digital storage element.

Abstract: A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. Therefore, a radiation hardened programmable phase frequency divider that is immune to SEU's is achieved.

Abstract: A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.

Abstract: A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.

Abstract: Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.

Abstract: Provided is a multi-threshold CMOS (MTCMOS) flip-flop for latching a data input signal in response to a clock signal and converting the latched signal to a data output signal.

Abstract: A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series.

Abstract: A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-slave flip-flop can be reduced. Since the master latch is formed from a static circuit, data can be held stably during the standby time by setting the master latch in a data holding state.

Abstract: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to a voltage source. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to the voltage source or a different voltage source. When a clock signal is in a first state, the first single transistor is activated to reset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to reset the digital storage element.

Abstract: A data latch contains a supply connection, a reference ground potential connection and a data input. The input side of an inverter is connected to the data input, and it is coupled via a first switching device to the supply connection, and via a second switching device to the reference ground potential connection. Furthermore, a first multivibrator circuit having transistors of a first conductance type is provided, and is coupled to the supply connection. A second multivibrator circuit having transistors of a second conductance type is coupled to the reference ground potential connection. The transistors in the first and second multivibrator circuits in the data latch are connected to one another on the output side at a first node and at a second node, with the first node being connected to one output of the inverter, and the second node forming an output tap.

Abstract: A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate.

Abstract: A register circuit includes a passage control circuit and a holding circuit. The passage control circuit includes a first transistor having a gate to which a clock signal is input, a second transistor having a gate to which a data signal is input, and a third transistor having a gate to which a control signal is input, with source-drain paths of the first, second, and third transistors being connected in series. The passage control circuit enables passage of the data signal to the holding circuit according to a state of the clock signal when the control signal is in one of an active state and an inactive state, and disables passage of the data signal to the holding circuit when the control signal is in the other one of the active state and the inactive state. The holding circuit latches the data signal passed from the passage control circuit.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.

Abstract: A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.

Abstract: Disclosed are methods and systems for implementing various circuitry within a high speed, high frequency signal environment such as an integrated circuit. In one embodiment, an improved clock tree mechanism utilizes multiple low power drivers to distribute a clock signal to various load cells. In another embodiment, a single circuitry in current mode logic is used to implement a combined multiplexer, buffer and level shifter. In other embodiments, improved static and partially static flip-flop circuitry is disclosed which uses fewer devices and less power than conventional circuitry while achieving the same functionality.

Abstract: A multi-threshold flip-flop includes a master latch, a slave latch, and at least one control switch. The master latch is composed of an input buffer formed with low threshold (LVT) transistors and a first latch circuit formed with LVT transistors. The slave latch is composed of a second latch circuit formed with high threshold (HVT) transistors and an output driver formed with LVT transistors. The at least one control switch enables or disables the LVT transistors and is implemented with at least one HVT transistor. The LVT and HVT transistors may be N-FETs and/or P-FETs. The multi-threshold flip-flop can operate at high speed, has low leakage current, and can save the logic state when disabled.