Abstract: Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.

Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.

Abstract: A clock circuit includes a phase-lock loop and a holdover circuit. The phase-lock loop generates an output clock signal having a constant frequency based on a loop filter voltage of a loop filter in the phase-lock loop. The holdover circuit generates and stores a digital value indicating the loop filter voltage and generates an analog voltage signal having the loop filter voltage indicated by the digital value. Further, the holdover circuit maintains the output clock signal at the constant frequency during a holdover of the phase-lock loop by regenerating the loop filter voltage based on the analog voltage signal. Because the analog voltage signal is based on the digital value, the voltage of the loop filter does not decay over time during the holdover of the phase-lock loop. As a result, the output clock signal remains at the constant frequency during the holdover of the phase-lock loop.

Abstract: An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

Abstract: An electronic device with an amplifier output stage (OS) and an over-current detection means (OCDM) for detecting an output over-current (IHS, ILS) of the output stage (OS) is provided. The over-current detection means (OCDM) comprises a level detection means (LDM) for detecting a level of the output current (IO) exceeding a first level of the output current (IDET), and a timing detection means (TDM) for detecting a duration during which the output current (IO) exceeds the first current level (IDET) being a maximum current level.

Abstract: A clock failure detection circuit comprises clock failure detection logic having a clock input providing an input clock signal, a counter and a reference clock input providing a reference clock signal to the counter for counting a number of reference clock cycles. The counter comprises a reset input arranged to receive successive reset pulses generated by at least one clock edge of the input clock signal to reset a counter value of the counter. The counter value before reset is used to identify a clock frequency error. A method of detecting a clock failure is also described. By using a counter value based on the reference clock cycles, and a reset trigger based on a clock edge of the input signal, it is possible to identify a clock frequency error in a much shorter time.

Abstract: To provide a signal judgement circuit that makes a judgement on signals received via at least four or more signal lines and enhances robustness and redundancy. A signal judgement circuit 1 making a judgement on a signal includes: an error signal generation circuit 10 receiving signals via at least four signal lines 100 and outputting an error signal when, of all the received signals, the number of signals taking on a same value does not exceed half of the number of the received signals; and an output selection circuit 30 selecting any one of the received signals and outputting the selected signal.

Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

Abstract: An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2?. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

Abstract: A phase comparator includes an edge detecting unit to which a reference signal is input and to which a referred signal based on the reference signal is input as a feedback signal. The edge detecting unit detects an edge of the reference signal and an edge of the referred signal. The phase comparator also includes a phase-difference detecting unit that detects a phase difference between the edge of the reference signal and the edge of the referred signal. The phase comparator also includes a phase-difference-signal output unit that outputs a phase-difference signal for current control based on the phase difference. The phase comparator also includes an input-break detecting unit that detects an input break of the reference signal when an edge of the referred signal is again detected after an edge of the referred signal is detected and before an edge of the reference signal is detected.

Abstract: Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor.

Abstract: The present invention relates to a clock supervision unit (100) and an electronic system clocked by at least one clock (c*) and using the clock supervision unit (100). The clock supervision unit (100) analyzes the at least one clock (c*) based on a monitor clock (m*) provided together with the at least one clock (c*) or separately to the clock supervision unit (100). The clock supervision unit (100) at least comprises an activity unit (210), a deviation unit (220) and an auxiliary clock generator (240). The auxiliary clock generator (240) outputs an auxiliary clock (a*). The activity unit (210) detects the presence of the monitor clock (m*) based on the auxiliary clock (a*) and the presence of the auxiliary clock (a*) based on the monitor clock (m*). The deviation unit (220) detects clock faults in the monitor clock (m*) based on the auxiliary clock (a*).

Abstract: A method and a circuit for detecting a disturbance of a state of at least one first flip-flop from a group of several first flip-flops of an electronic circuit, wherein: the respective outputs of the first flip-flops in the group are, independently from their functional purpose, combined to provide a signal and its inverse, triggering two second flip-flops having data inputs forced to a same state, the respective outputs of the second flip-flops being combined to provide the result of the detection; and a pulse signal comprising a pulse at least for each triggering edge of one of the first flip-flops in the group initializes the second flip-flops.

Abstract: A clock failure detection circuit comprises clock failure detection logic having a clock input providing an input clock signal, a counter and a reference clock input providing a reference clock signal to the counter for counting a number of reference clock cycles. The counter comprises a reset input arranged to receive successive reset pulses generated by at least one clock edge of the input clock signal to reset a counter value of the counter. The counter value before reset is used to identify a clock frequency error. A method of detecting a clock failure is also described. By using a counter value based on the reference clock cycles, and a reset trigger based on a clock edge of the input signal, it is possible to identify a clock frequency error in a much shorter time.

Abstract: A method and system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.

Abstract: A signal presence detection device has a first reference voltage generation device in the form of a first voltage divider, a second reference voltage generation device in the form of a second voltage divider and a third reference voltage generation device in the form of a third voltage divider. The detection device also has a signal conditioning device such as a hysteretic amplifier with an output that is coupled to the first and second voltage dividers. A comparison device is coupled to all three voltage dividers to compare a voltage of the first voltage divider to a voltage of the third voltage divider and to compare a voltage of the second voltage divider to the voltage of the third voltage divider. The comparison device is coupled at two outputs thereof to two respective inputs of an XOR device. The XOR device receives respective signals from the first and second outputs of the comparison device and produces a signal presence output that serves to indicate whether an incoming signal is present or absent.

Abstract: In order to provide a high frequency clock detection circuit capable to detect a high frequency clock using any period as a threshold, the high frequency clock detection circuit of the present invention includes a delay circuit having a delay time set to be longer than a clock period corresponding to the irregular high frequency state, a first flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the first flip-flop circuit, a second flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the second flip-flop circuit through the delay circuit, and a detection-result output circuit for detecting a difference between the output signal from the first flip-flop circuit and the output signal from the second flip-flop circuit and for providing the function circuit with the high frequency clock detection signal indicating the irregular

Abstract: A digital circuit is disclosed for detecting clock activity in an integrated circuit (IC) device. In one implementation, a clock detection circuit can include two flip flops. A first flip flop detects activity on the clock being tested (e.g., the flip flop is set when a positive clock edge is detected). A second flip flop is coupled to the output of first flip flop and is operable by an enable signal to sample the output of the first flip flop. The output of the second flip flop is asserted as active, when a positive clock edge occurs between the release of the reset signal on the first flip flop and the assertion of the enable signal on the second flip flop. In some implementations, one or more additional flips can be interposed between the first and second flips to control metastability.

Abstract: A circuit for monitoring a PWM signal and providing an output indicating a condition of the PWM signal. The circuit also uses condition based hysteresis to maintain an output value at a previous state until the condition of the PWM signal has remained unchanged for a given duration. In addition, the circuitry may be used in conjunction with a switching regulator to reduce switching noise during high duty cycle operation.

Abstract: One of a first signal, a second signal, and a third signal is received respectively from each of three inputs. A pattern formed by the first signal, the second signal, and the third signal is compared to a set of predetermined patterns. Based on the comparing, it is determined whether an error exists. If an error condition exists, a specific one of the inputs is identified as a cause of the error.

Abstract: A method to detect a missing a clock pulse is provided. The method begins by providing a clock signal and a delayed clock signal. The delayed clock signal is then sampled to generate a sample of the delayed clock signal. A missing clock pulse may be detected if the sample of the delayed clock signal does not equal an expected value of the delayed clock signal.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: A system and method is disclosed for providing communication of an over-current protection signal and current mode control signals between a controller chip and a power chip in an integrated circuit device that comprises a plurality of integrated circuit chips. The controller chip sends pulse width modulation signals and a reference current signal to the power chip. Current flow status detection circuitry in the power chip detects a current flow status in the power chip and provides a current flow status signal to the controller chip. The current flow status signal may comprise an over-current protection signal or current mode control signals. One advantageous embodiment of the invention comprises a switch mode power supply integrated circuit.

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract: A frequency sensor includes at least one a resistor element and a capacitor. A frequency is detected according to a charging/discharging time to/from the capacitor, thereby realizing a frequency sensor with reduced power consumption and reduced circuit scale. Further, plural resistors and plural capacitors can be provided, along with switches connected to the respective resistors and capacitors. Additionally, a time constant can be adjusted after production, whereby variations in production can be reduced. Furthermore, a self-diagnosis circuit can be included for determining whether the frequency sensor itself operates normally or not. Thus, a highly-reliable frequency sensor can be realized.

Abstract: A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.

Abstract: A hysteresis receiver containing two inverters and a logic controller. The inverters are implemented with threshold voltages equaling Vil and Vih, which together define the hysteresis window. The inverters receive the input signal and generate a respective inverted value. The logic controller propagates as output one of the two inverted values if the two inverted values are equal, and a prior value (corresponding to a previous sample) if the two inverted values are not equal. A receiver circuit with a hysteresis window defined by Vil and Vih, is obtained as a result.

Abstract: A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.

Abstract: A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.

Abstract: A tone detector is disclosed that is realizable in digital embodiment on a single integrated circuit die and does not require external components, such as a discrete capacitor. An input connects to a comparator, which in turn connects to one or more edge detectors and a flip flop. The edge detector outputs a pulse responsive to a detected edge. A counter is reset by the pulses from the edge detectors thereby preventing the counter from reaching a maximum value, which would otherwise be output from the counter and provided to a flip flop to clock in the comparator output at the D input to the flip flop. In operation, the comparator generates a rail to rail signal responsive to a received tone, which in turn is clocked through the flip flop as a logic high output indicating presence of a tone.

Abstract: A system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.

Abstract: A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock terminal responsive to the inverse of the feedback clock. The one-shot block generates a pulse in response to a rising edge of the reference clock that is used to generate the feedback clock. The one-shot block generates an output signal applied to a reset terminal of the first flip-flop.

Abstract: Methods and apparatus for power monitoring with sequencing and supervision are disclosed. An example method disclosed herein comprises supervising a first power rail and a second power rail, sequencing a first enable signal associated with the first power rail and a second enable signal associated with the second power rail, and determining whether the first power rail is enabled based on regulation information determined while supervising the first power rail.

Abstract: The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail indicator signal as a function of the reset pulse stream and a difference between an input signal and a reference voltage. The correlation module correlates an event (e.g., overvoltage or undervoltage) of the pass/fail indicator signal with a period of the clock signal at which the event occurred.

Abstract: A clock anomaly detection circuit includes: a dividing unit configured to output a divided target clock by dividing frequency of a target clock; a first time width measurement unit configured to obtain values of the divided target clock using rising edges of a monitoring clock that is synchronized with the target clock, and to measure an H level time with and an L level time width; a second time width measurement unit configured to obtain values of the divided target clock using falling edges of the monitoring clock, and to measure an H level time with and an L level time width; and an anomaly determination unit configured to determine that the target clock is abnormal when an anomaly is detected in the H level time width or the L level time width measured in the first time width measurement unit and when an anomaly is detected in the H level time width or the L level time width measured in the second time width measurement unit.

Abstract: A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.

Abstract: The number of electrical devices implemented in motor vehicles and supplied with electricity by the motor vehicle battery rises with each generation. The manufacturers of motor vehicles make great demands on electrical device to be built-in their motor vehicles, especially to the stand-by power consumption of the built-in devices in order to protect the motor vehicle battery from a fast and undesired unloading during the stop of the motor vehicle. The present invention relates to an electrical circuit provided to be implemented in motor vehicle built-in devices for limiting the power consumption during the stand-by thereof, i.e. to reduce the power consumption to almost no consumption. Further, the present invention relates to an electrical motor vehicle built-in device having the aforementioned electrical circuit for limiting the power consumption of the electrical motor vehicle built-in device.

Abstract: A malfunction detection circuit realized by a simple circuit structure is incorporated into a semiconductor integrated circuit without increasing the scale thereof, in order to prevent loss etc. of data due to a malfunction of the semiconductor integrated circuit. Malfunctions can be prevented without relying on measuring temperature or power supply voltage which are analog values, thereby improving the reliability of the semiconductor integrated circuit. A detection-target flip-flop in a function block is synchronized to a clock, and another flip-flop is synchronized to a clock whose phase has been delayed behind or advanced ahead of the former clock. A logic operation is performed using output from both flip-flops to determine whether a latch operation has been performed at an appropriate clock pulse edge in a clock pulse train. The malfunction countermeasure is performed if the latch operation is determined to have been performed at an inappropriate clock pulse edge.

Abstract: An apparatus for optical receiver circuit protection includes a bias source, a bias monitor, and a comparator. The bias source is to provide a bias voltage to an optical receiver. The bias monitor is coupled to measure a current through the optical receiver, where the current changes responsive to received optical energy. A comparator is coupled to the bias monitor, where the comparator has a first state if the current is less than a threshold current level and where the comparator has a second state if the current is greater than the threshold current level. The bias source is coupled to be enabled responsive to the comparator switching to the first state and disabled responsive to the comparator switching to the second state.

Abstract: A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast internal precision oscillator, and finally switches to the fast internal precision oscillator. A failure detection circuit within the clock controller detects a failure of the external precision oscillator and sends an associated interrupt signal to the processor. The clock controller decouples the external oscillator from the processor and couples the backup oscillator to the processor. The microcontroller integrated circuit then enables the fast internal precision oscillator, decouples the backup oscillator, and couples the fast internal precision oscillator to the processor.

Abstract: A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.

Abstract: A semiconductor apparatus for flexibly and effectively configuring a delay monitor circuit without an increase in circuit scale includes a delay signal generation circuit for switching the configuration of delay element arrays based on first configuration information and second configuration information and propagating a delay element array wherein a pulse is switched, a register group having a first register for the first configuration information and a second register for second configuration information, a selector for outputting to the delay signal generation circuit the first configuration information and second configuration information in accordance with an instruction of a selection signal in a time sharing way, and a control circuit for controlling a power source voltage based on delay information of a delay element array and outputting to the selector a selection signal to select from the first configuration information and second configuration information in a time sharing way.

Abstract: This invention offers a signal-off detection circuit allowing arbitrary setting of an issuing time (response time) of a signal disconnection alarm without being affected by a time constant of a direct current feedback circuit giving an offset voltage to an amplifier for amplifying a data signal. Input data signals per a fixed time determined by a timer is counted by a counter, and a count value is compared with a predetermined set value in a comparator. A configuration is made such that a signal disconnection alarm may be issued by detecting a disconnection state of the data signal according to a comparison result. Thereby, an issuing time of a signal disconnection alarm can be set without being affected by a time constant of a direct current feedback circuit giving an offset voltage to an amplifier for amplifying a data signal of a preceding stage.

Abstract: A clock signal outputting method in which either a clock signal based on a signal from the outside or an alternative clock signal from a fixed oscillator is selected and outputted, wherein, when the clock signal is selected to be outputted, the fixed oscillator is put into non-operating state, and when any error occurs in the clock signal, the fixed oscillator is operated to output the alternative clock signal.

Abstract: Methods and apparatus are disclosed for using in-band signal(s) over a differential serial data link to reduce power usage of a transmitter and receiver coupled by the link.

Abstract: A clock switching circuit suitably adapted to stable switching operation of high-frequency multiphase clock signals. The clock switching circuit receives two clock signals and selectively outputs one of the two clock signals in accordance with a selection signal. The clock switching circuit includes a switching controller that transfers the selection signal at the beginning of a period in which both of the two clock signals are active, and an internal selector that selectively outputs one of the two clock signals in response to the selection signal transferred from the switching controller.

Abstract: A redundant-source clock generator has only two oscillators, rather than three oscillators. A secondary oscillator is phase-locked to a primary clock from a primary oscillator using a phase detector, charge pump, and filter that generate a control voltage to the secondary oscillator that determine the frequency of a secondary clock. The primary clock is compared to the secondary clock to detect primary clock failure. When clock failure is detected, a mux is switched to select a delayed secondary clock rather than a delayed primary clock to output as a system clock. Since the mux receives delayed clock signals, clock-failure detection has additional time to detect the clock failure before the clock failure is propagated through the mux. When the primary oscillator fails and the clock failure is detected, the phase detector stops comparing a feedback secondary clock to the primary clock and instead holds the control voltage steady.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Abstract: According to some embodiments, a presence indication associated with an attachment is provided.

Abstract: A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitored clock by delaying the to-be-monitored clock by a predetermined time, a latch circuit which detects based on the to-be-monitored clock and the delayed synchronous to-be-monitored clock that a value of a decrease in a pulse width to be determined by a pulse duty of the to-be-monitored clock becomes smaller than the predetermined time, and a flip-flop circuit which samples an output signal of the latch circuit based on the to-be-monitored clock.