Abstract: An improved signal detector system implementable in a high-speed SerDes receiver core that is able to detect valid signals from noise signals with a much tighter tolerance. The signal detector system improves upon the prior art designs by implementing modifications including: (1) the use of two peaking amplifiers for both (differential) input signals and reference to track and cancel gain variation; and, (2) the reduction of current mirroring stages to cut down current mapping error.

Abstract: A passive coupling structure constructed using printed circuit board traces is used to separate the low and high frequency components of an incoming digital signal. The low and high frequency components of the signal are sent to separate receivers on an integrated circuit. The low frequency receiver may be a conventional level based receiver. The high frequency receiver is a Schmitt-trigger with hysteresis around a DC level or two comparators with separate reference voltages. The outputs of these receivers are combined to produce a receiver output that has increased reliability and noise immunity.

Abstract: An integrated circuit comprises a microprocessor for generating data signals along a data bus by way of an inverter to a plurality of input/output switching buffers. The buffers pass the data signals to a transmission bus for onward transmission to a receiving integrated circuit. A respective drain and source supply power to the buffers. A transition checking circuit monitors the number of data signals on the data bus simultaneously switching from a first to a second logic state and a control circuit counts the number of the simultaneous switching data signals and generates a flag signal when the count exceeds half the number of buffers. The flag signal is applied to the inverter to invert all of the data signals on the bus.

Abstract: A circuit for detecting asynchronous events includes a first event detection latch; and a second event detection latch coupled to the first event detection latch, wherein the first event detection latch is ready to detect an event when the second event detection latch is being reset and wherein the second event detection latch is ready to detect a next event when the first event detection latch is being reset.

Abstract: A clock signal detection circuit is provided that can reliably detect whether or not a clock signal is supplied with a reduced circuit scale and reduced power consumption.

Abstract: The invention is directed to an apparatus and a method for generating a fault detection signal when a differential signal is in a fault condition. The fault condition arises when the data transmission path in a differential signaling device is either open, shorted, or terminated by an abnormal means, and is such that the inputs are within the valid common-mode range and a valid differential signal cannot be obtained. The invention is buffered from the differential signal source, and an intermediate signal is produced in response to the differential signal. Portions of the intermediate signal are compared to a reference signal, and based on the comparisons, fault condition control signals are produced. A fault detection signal is produced when two fault condition control signals indicate the presence of a fault. The fault detection signal is made available for invocation of a failsafe state.

Abstract: A system and method for transmitting data includes one or more transmitters connected to each of at least one bus data line via open-driver bus data line drivers, and one or more receivers. In a preferred embodiment, the devices are interconnected by a parallel interface using a bus architecture having the bus data and carrier-sense (CRS) lines each driven by open-collector or open-drain drivers in a wired-and configuration. Pullup resistors and a common clock signal are also provided. Each device is provided with an interfacing unit which connects the device to the bus, and detects collisions by comparing data transmitted by the device with data received from the bus. The invention is particularly applicable to implementation as a backplane connecting intercommunicating printed wiring boards having interfaces such as the IEEE 802.3 (Ethernet) Media Independent Interface (MII), the interfacing unit serving to emulate the Ethernet PHY.

Abstract: A clock down sensor mainly comprises a converter and a low-pass filter. The converter is used to convert an input signal from a PECL (Positive Emitter Coupling Logic) signal to a TTL (Transistor Transistor Logic) signal, the low pass filter is used to obtain a DC (Direct Current) level of the TTL signal. Thereby, the sensor can judge whether the clock signal is terminated according to the potential of the output signal in order to emit a warning so that a breakdown elimination inquiry can be done or automatic breakdown elimination can be processed earlier.

Abstract: An apparatus and method is provided for detecting loss of differential signal carried by a pair of differential signal lines. According to the method, a common mode level is detected from voltages on the pair of differential signal lines. A threshold level is generated, referenced to the detected common mode level. A signal level is generated from the voltages on the pair of differential signal lines, the signal level being averaged over a first period of time. From the threshold level and the detected common mode level a reference level is generated, the reference level being averaged over a second period of time longer than then the first period of time. The signal level is compared to the reference level to determine if a signal is present on the pair of differential signal lines.

Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

Abstract: Fault detection circuitry is provided for a PWM driver responsive to a PWM input signal to produce a PWM output signal, and includes a first circuit producing a scaled switching signal as a scaled representation of the PWM input signal. A second circuit is configured to produce a combined switching signal as a combination of the PWM output signal and the scaled switching signal, and a third circuit is configured to convert the combined switching signal to an analog output signal indicative of one or more fault conditions associated with the PWM driver. A number of comparators may be included with each responsive to the analog output signal and to a different one of a corresponding number of different references voltages, to produce a fault signal indicative of a particular one of the one or more fault conditions.

Abstract: A circuit for sensing the presence of an inductive load that is particularly applicable to sensing when a solenoid is being driven by a pulse width modulation (PWM) signal. The circuit includes a high side connected transistor having an output driving a load, with the transistor driven by a PWM signal. A circulating diode is coupled to the driving output of the transistor. The circuit further comprises an operational amplifier (op amp) circuit that is coupled to the circulating diode and operates as an inverting operational amplifier (op amp). The op amp circuit charges a first capacitor when the transistor releases driving an inductive load.

Abstract: The present invention comprises a low side reverse recovery sense circuit (401) and a high side reverse recovery sense circuit (601), of a low side over-current circuit of a power output stage (400) and a high side over-current of a power output stage (600), respectively, operable to sense current through said low side and high side primary circuit and accurately control said current when an over-current threshold is detected while disabling such circuit when a reverse recovery spike is detected.

Abstract: An integrated circuit has a loss of signal (LOS) system for detecting a loss of signal condition for an input data stream according to a LOS threshold. The LOS threshold specifies a minimum signal magnitude indicating the loss of signal condition. The integrated circuit includes a sampling circuit to sample a LOS signal, which receives a sampling threshold specifying a signal magnitude for a sampled signal above which the sampling circuit samples the sampled signal as a first digital value and below which the sampling circuit samples the sampled signal as a second digital value. A digital control circuit coupled to an output of the sampling circuit generates a calibrated digital representation of the sampling threshold according to a plurality of samples of the LOS signal. The calibrated sampling threshold is then used during loss of signal evaluation.

Abstract: An electronic device such as a processor receives a master clock signal from a system clock generator. The clock signal may be single-ended or differential. The disclosure presents methods and devices for automatically producing a clock signal that follows the master clock signal, regardless of whether the master clock signal is single-ended or differential.

Abstract: A microcomputer is provided, which eliminates the need of input of a selection signal to select whether an external oscillator element is connected to generate an internal clock signal or an external clock signal is inputted to generate an internal clock signal. In this microcomputer, a delay circuit generates a delayed reset signal from an external reset signal to have a specific delay period. An external clock signal detection circuit detects an external clock signal at a second terminal, outputting a detection signal. An oscillation control signal generation circuit generates an oscillation control signal for an amplifier circuit, where the oscillation control signal is generated corresponding to a detection signal outputted from an external clock signal detection circuit. The oscillation control signal is used to activate the amplifier when the external clock signal does not exist at the second terminal and to inactivate the amplifier when the external clock signal exists at the second terminal.

Abstract: An on-chip watchdog circuit (100) is provided that generates an output signal (175) when an error signal (112) generated by a circuit under test (110) is detected. The on-chip watchdog circuit (100) comprises a logic gate (125) that is connected to a clock signal and receives a signal in response to the error signal 112 generated by the circuit under test (110). A gate output circuit (140) is connected to an output of the logic gate (125). An RC circuit (150) is connected to the gate output circuit (140). A comparator (170) is connected to the RC circuit (150). The comparator (170) is also connected to a voltage divider (160) and provides the output signal (175) in response to the error signal (112) generated by the circuit under test (110), and the on-chip watchdog circuit (100) and the circuit under test (110) are integrated on a same semiconductor microchip.

Abstract: One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. The system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Next, the system uses the voltage-controlled variable resistor to control a first current. A current mirror is then employed to create a second current from the first current. This second current passes through a resistor to produce a control voltage, which is amplified to produce a validity signal indicating whether or not the clock signal is valid. In one embodiment of the present invention, the system additionally uses at least one capacitor to filter out periodic fluctuations in the validity signal.

Abstract: A clock monitoring apparatus according to the invention including a main clock monitoring portion including a first counter for counting a main clock, issuing a normal operation confirming flag indicating that a normal operation is being carried out when the first counter is overflowed or reaches a previously determined set value, monitoring the normal operation confirming flag by a sub clock, issuing a first main clock stop flag having an output in correspondence with H (high level)/L (low level) of the normal operation confirming flag and a main clock initializing signal for initializing the main clock when the main clock is determined to stop and resetting the first main clock stop flag when the main clock is recovered by receiving the main clock initializing signal, and a sub clock switching control portion including a second counter for counting a signal output produced by calculating a logical sum of the sub clock and the first main clock stop flag at fall of the sub clock at a time point of generating

Abstract: A clock detect indicator capable of determining the presence of high and low frequency clock signals is provided. The clock detect indicator, which operates independent of a reference clock, has detection circuitry that determines whether a particular clock signal has alternating high-to-low and low-to-high transitions. Based on the determination, the clock detect indicator outputs a transition on a clock detect indication signal. Further, a method for detecting a clock signal in an integrated circuit is provided.

Abstract: A clock monitoring apparatus according to the invention including a main clock monitoring portion including a first counter for counting a main clock, issuing a normal operation confirming flag indicating that a normal operation is being carried out when the first counter is overflowed or reaches a previously determined set value, monitoring the normal operation confirming flag by a sub clock, issuing a first main clock stop flag having an output in correspondence with H (high level)/L (low level) of the normal operation confirming flag and a main clock initializing signal for initializing the main clock when the main clock is determined to stop and resetting the first main clock stop flag when the main clock is recovered by receiving the main clock initializing signal, and a sub clock switching control portion including a second counter for counting a signal output produced by calculating a logical sum of the sub clock and the first main clock stop flag at fall of the sub clock at a time point of generating

Abstract: A loss-of-clock (LOC) detector circuit detects a clock failure substantially within a specified number of clock periods and generates a loss-of-clock signal. The LOC detector includes a frequency-to-current converter which generates a charging current substantially proportional to a frequency of an input clock. A capacitor accepts the charging current and provides a terminal voltage that changes in response to the charging current. An edge detector receives the input clock signal as an input and produces an output pulse on an edge of the input clock signal. A switch is coupled to the capacitor such that the capacitor is discharged to a reference potential when the switch is closed. The switch is controlled by the edge detector to close when the edge detector output pulse is asserted. A comparator generates a loss-of-clock signal when the voltage on the capacitor passes a trip voltage of the comparator.

Abstract: In general, a built-in self test circuit and method is provided that measures error in any periodic signal and, particularly, a Phase Lock Loop (PLL) output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal having the same frequency as the phase lock loop output clock signal. Accordingly, a delay chain, including a plurality of delay elements, generates N delayed pulses from the short-pulse signal. A hit-pulse generator receives the N delayed pulses and compares each delayed pulse with the phase lock loop output clock signal 2K times, such that the hit-pulse generator also generates a hit-pulse when both signals are high. It also generates a hit count which represents the number of hit-pulses. After each of the N delayed pulses are compared with the clock signal 2k times, a comparator compares a predetermined set of threshold values corresponding to the cumulative distribution of jitter for a PLL clock signal with the hit count.

Abstract: While generating a correction pulse (E) based on a clock signal (Xck1) input into one input terminal (6), a frequency and a phase of a differentiated pulse train (Data_Dif) input into the other input terminal (5) are compared with a frequency and a phase of the clock signal input into the one input terminal, then a leading phase instructing pulse (U4) and an incomplete lagging phase instructing pulse (D4a) are generated based on this compared result, then false pulses contained in the incomplete lagging phase instructing pulse (d4a) are removed by using the correction pulse (E) when the differentiated pulse train (Data_Dif) input into the other input terminal is in the tooth missing state, and then the precise leading phase instructing pulse (U4) and the precise lagging phase instructing pulse (D4) are output from two output terminals (7, 8).

Abstract: A clock interruption detection circuit comprises a frequency divider circuit for outputting a plurality of frequency divided clocks by dividing an input clock with different division values, an AND circuit for ANDing the input clock and the plurality of frequency divided clocks, an inverter for inverting one of the frequency divided clocks with the largest division value, another AND circuit for ANDing the input clock, the rest of the frequency divided clocks and the output of the inverter, a first and a second switch with a control terminal supplied with the output of each of the AND circuits for controlling the on/off of a discharge path of a first and a second capacitor, a first and a second waveform-shaping buffer circuit supplied with a terminal voltage of the first and the second capacitor, and a selection circuit for selecting one of the outputs of the first and second waveform-shaping buffer circuits in accordance with a selection control signal obtained by delaying the output of the inverter by a pre

Abstract: A loss of signal detection circuit using Gilbert mixers. A differential input signal is provided to an input Gilbert mixer. Reference signals are provided to a reference Gilbert mixer. The two Gilbert mixers pull reference lines in opposing directions such that a one line is higher than another line when the differential input signal provides valid data.

Abstract: A clock monitoring circuit is disclosed for detecting that the period of a clock signal has become shorter than a predetermined time interval. The clock monitoring monitoring circuit comprises a first and second flip-flop circuits that are D-type flip-flops, a delay circuit, and a gate circuit. The second flip-flop circuit receives as an input signal the output signal of the first flip-flop circuit. The output signal of the second flip-flop circuit is delayed a fixed time interval by the delay circuit and then supplied as an input signal to the first flip-flop circuit. The delay time of the delay circuit is set to be equal to the previously described predetermined period. The gate circuit receives the output signals of the first and second flip-flop circuits, and provides a signal whose logic level when the period of the received clock signal is the predetermined period differs from that when it is shorter than the predetermined period.

Abstract: An application specific integrated circuit includes a clock recovery circuit which recovers from an input signal a repetitive sequence of data values wherein no two consecutive values are the same and a recovered clock. An address generator responds to the recovered clock to cause storage of the data values in said memory in a set of locations having addresses generated by the address generator, so that the address generated by the generator increments in response to a repetitive transition in the recovered clock. The existence of a clock glitch is found by reading the data values from the set of locations to determine whether any two consecutive locations contain the same data value.

Abstract: The lock detector circuit determines and indicates whether the PLL is in an in-lock mode or in an out-of-lock mode without using an external capacitor for controlling phase error. Moreover, the lock detector circuit indicates the operating mode of the PLL on a period-by-period basis relative to the period of the reference and feedback signals. Thus, the lock detector circuit provides real-time indication of the operating mode of the PLL.

Abstract: A circuit for detecting abnormality of a subject clock signal, includes a frequency dividing circuit for frequency-dividing a monitoring clock signal to provide a frequency-divided monitoring clock signal; a shift register which stores the frequency-divided monitoring clock signal in synchronization with the subject clock signal; and a plurality of abnormality evaluation circuits. The abnormality evaluation circuits operate complementarily each other in accordance with an output signal of the shift register and detect abnormality of the subject clock signal for a period of time corresponding to the cycle of the monitoring clock signal.

Abstract: A circuit for detecting a state of at least one electrical actuating element is described. The circuit has a signal input for receiving an input signal representing the state of the actuating element, a signal output for emitting an output signal representing the state of the actuating element, a control output for emitting an activation signal for an evaluation unit, to change over the evaluation unit from an inactive operating state to an active operating state, and a control unit. The control unit is connected to the signal input on the input side and to the control output on the output side and serves for generating the activation signal in a manner dependent on the input signal. The input signal at the signal input is an analog signal, the control unit generating the activation signal for the evaluation unit if the input signal lies within a predetermined range.

Abstract: A sensor device includes a sensor circuit for measuring a physical amount such as pressure, a voltage detector for detecting a voltage actually supplied to the sensor circuit, and an oscillator for generating an oscillating signal when the voltage detector finds the voltage supplied to the sensor circuit is abnormally low. The sensor signal and the oscillating signal are selectively supplied to a controller. The controller controls various devices connected thereto based on the sensor signal, while it detects a malfunction of the sensor device based on either a high level signal or a low level signal in the oscillating signal. Thus, the malfunction of the sensor device is automatically detected without fail.

Abstract: Method and device for reducing the time constant of a system having a conductor connected thereto by connecting an impedance between the conductor and a potential as the voltage on said conductor exceeds a preselected value.

Abstract: A data decoder for decoding digital data in a high frequency signal in an optical storage device. A carrier signal derived from the high frequency passed through a zonal bandpass filter and a limiter is multiplied by the high frequency signal passed through a high pass filter. The resulting product is filtered and passed through a comparator forming a digital data stream.

Abstract: A circuit for detecting a state of at least one electrical actuating element is described. The circuit has a signal input for receiving an input signal representing the state of the actuating element, a signal output for emitting an output signal representing the state of the actuating element, a control output for emitting an activation signal for an evaluation unit, to change over the evaluation unit from an inactive operating state to an active operating state, and a control unit. The control unit is connected to the signal input on the input side and to the control output on the output side and serves for generating the activation signal in a manner dependent on the input signal. The input signal at the signal input is an analog signal, the control unit generating the activation signal for the evaluation unit if the input signal lies within a predetermined range.

Abstract: A loss-of-signal (LOS) detector, for example, for a clock/data recovery (CDR) circuit for an optical fiber communication system, has (1) a transition detector for detecting stuck-on-one and stuck-on-zero LOS conditions and (2) an inconsistency detector for detecting other types of LOS conditions. In one embodiment, the inconsistency detector has two decision circuits having different operating conditions (e.g., different decision thresholds and/or different sampling times). The two decision circuits are configured to generate like output signals (i.e., both high or both low), when a valid input data signal is applied. However, at certain times during certain LOS conditions, the outputs of the two decision circuits will be mutually inconsistent (i.e., one high and one low). If the number of such inconsistencies over a specified time period exceeds a specified threshold level, then an LOS condition is determined.

Abstract: A method for performing an “AND” operation on two independent inputs in a fail-safe manner includes cascading two charge pumps to output a condition signal representing the “AND'ed” state of the inputs. Each independent input has an active state asserted by a waveform of predetermined frequency and duty cycle, and an inactive fail-safe state asserted by a zero voltage. The method includes supplying power to a first charge pump, supplying power from the first charge pump to a second charge pump, and supplying each of the independent inputs to one of the respective charge pumps. A condition signal is output using an output from the second charge pump. Additionally, the method verifies the correctness of the frequency and duty cycle of each independent input using a cross connection scheme. This method provides a high-power, low-loss, and low-cost electrical circuit for operating devices responding to specific voltages, for example, vital relays.

Abstract: A data communication network is provided having a first communication device that includes a plurality of ports, and a control coupled to the ports and having a plurality of outputs extending from the control, with each of the outputs indicative of the status of one of the ports. The network further includes a power shut-off and recovery circuit coupled to the first communication device, and having a first signal detection circuit coupled to the ports for detecting activity on each port and for generating a first signal indicative of the activity, and a second signal detection circuit coupled to the outputs for detecting activity on each port and for generating a second signal indicative of the activity. The power shut-off and recovery circuit further includes a power control circuit that is coupled to the first and second signal detection circuits for receiving the first and second signals, respectively, and for selectively asserting an ENABLE signal based on either the first signal or the second signal.

Abstract: An oscillation stop detection circuit comprises delay means for delaying an oscillation signal having a predetermined cycle by a predetermined time to thereby output a delayed signal therefrom, detecting means for exclusive-ORing the oscillation signal and the delayed signal to thereby detect the presence of the oscillation signal and outputting a pulse signal in the predetermined cycle when the oscillation signal exists, and charge and discharge means having a capacitor electrically connected between an output node for outputting a detection signal indicative of whether the oscillation signal is at a stop and a source potential or a ground potential, and for discharging the capacitor when the pulse signal is supplied and charging the capacitor according to a predetermined time constant while the pulse signal is unsupplied.

Abstract: An apparatus and method are disclosed for initiating automatic recovery from a signal loss. A frequency division circuit receives a system clock signal, and generates an output signal having a lower frequency than the clock signal. An input detection circuit receives an asynchronous input signal from an external source and outputs a third output signal that indicates whether or not the asynchronous input signal is present or absent within a prescribed detection interval. A recovery circuit receives the system clock signal and the third output signal, and outputs a recovery signal that indicates a loss of the asynchronous input signal over a predetermined length of time. The recovery signal is used as a trigger to initiate a recovery process by the system.

Abstract: Current sense amplifiers with hysteresis are provided which conserve scarce chip surface area yet still provide fast response times in a low power CMOS environment. A first embodiment includes a first amplifier and a second amplifier which are electrically coupled. Each amplifier includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, where the first and second transistors are coupled at a drain region. A signal input node is coupled to a source region of the first transistor in each amplifier. A signal output node is coupled to the drain region of the first and the second transistors in the second amplifier. The signal output node is further coupled to a gate of a third transistor in order to introduce hysteresis into the current sense amplifier. Integrated circuits, electrical systems, methods of operation and methods of forming the novel current sense amplifier are similarly included.

Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected. Also, an inverter receives the sensing signal and outputs a first signal.

Abstract: A counting apparatus having excellent fail-safe characteristics can be used in a rotation-stopped detection apparatus. As a first feature, timing of a high-frequency signal P2 is carried out by a counter 1 after completion of a counting of pulse signals P1. When the frequency of the timing output for the high-frequency signal is a predetermined value, a judgment signal, indicating that the counting is normal, is generated by a frequency discriminating circuit 30. As a second feature, a counter 100 is preset using a preset signal. Then, after verifying by an output from a self hold circuit 102 that the counter 100 has been reset, a counting output is generated from a self hold circuit 104. As a third feature, the counting apparatus is used as timer circuits 203, 300, 400, and the generation frequency of a rotation detection pulse signal IP based on a sensor signal, is obtained to thereby detect a rotation-stopped condition of a rotating body.

Abstract: A pulse detection circuit, a method of operation and a fan assembly test circuit employing the same. In one embodiment, the pulse detection circuit includes a charge pump that receives an input signal and varies a charge in a charge storage device based on the input signal. The pulse detection circuit further includes a level detector, coupled to the charge pump, that compares a voltage across the charge storage device with first and second reference voltages, and a signaling circuit, coupled to the level detector, that generates an output signal based on the comparison and indicating an existence of the pulse. The pulse detection circuit may be a part of a fan assembly test circuit adapted to receive an input signal from a cooling fan under test.

Abstract: An apparatus detects the loss of an asynchronous input signal and generates a reset signal that is synchronous to a system clock signal. The apparatus detects the loss of the input signal and generates a first output signal. The first output signal is delayed by a predetermined number of clock cycles, and a second output signal is generated to indicate a sustained loss of the input signal. A signal monitoring circuit is provided to confirm the loss of the input signal and generate a third output signal. The reset signal is generated only if the signal loss is both sustained and confirmed. Accordingly, the apparatus will not be unnecessarily reset as a result of noise that delays or accelerates the arrival of an edge of the asynchronous input signal.

Abstract: An integrated circuit having an apparatus for automatically adjusting noise immunity is disclosed. The integrated circuit includes multiple functional logic circuits, a clock generator, a group of noise monitor circuits, and a control logic circuit. The clock generator generates a clock signal to all these circuits. The noise monitor circuits are utilized to detect noise occurring in the integrated circuit. In response to any noise detected by the noise monitor circuits, the control logic circuit decreases the speed of the clock signal sent to all the circuits, especially the functional logic circuits, via a slow down signal to the clock generator. Alternatively, the control logic circuit can inform the functional logic circuits via a noise alert signal to increase the noise immunity of certain noise sensitive circuits within the functional logic circuits.

Abstract: A circuit arrangement for monitoring a load operated with a clock signal is provided. The circuit arrangement may be applied to the field of automotive engineering. The circuit arrangement includes a comparator having at least two inputs and one output. The circuit arrangement further includes a D-flip-flop having one clock input, one signal input, and one output. At least a first input of the comparator is coupled to the load signal. The output of the comparator is coupled to the signal input of the D-flip-flop. The clock input of the D-flip-flop is coupled to the clock signal. The output of the D-flip-flop delivers a monitoring signal.

Abstract: A device is provided for neutralizing an electronic circuit whose rate is set by a clock signal in the event of an anomaly in the clock signal. The device includes an inhibition circuit for selectively inhibiting operation of the electronic circuit, and an anomaly detector for activating the inhibition circuit to inhibit operation of the electronic circuit as soon as an anomaly is detected in the clock signal. In one preferred embodiment, the anomaly detector includes two monostable circuits and a logic circuit. The first monostable circuit receives the clock signal and outputs a first pulse at each trailing edge of the clock signal, and the second monostable circuit receives the clock signal and outputs a second pulse at each leading edge of the clock signal. The logic circuit receives the first and second pulses and outputs an activation signal to the inhibition circuit whenever the clock signal shows an anomaly.

Abstract: In the microcomputer with a PLL (1007), a frequency lock signal generation circuit (101) inputs a XINFAST signal (1025) and a PLLFAST signal (1026) of a L level transferred from the PLL (1007) while frequency oscillation of the PLL (1007) is in unstable state, and then outputs a lock signal (110) to indicate refreshing of counting down to a stable detection timer (107).

Abstract: A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current" power consumption when docks to the logic circuit are stopped, and allows the circuit to be powered down when idle. The system includes a circuit for forcing clock phases to an active state, a circuit for breaking feedback paths within the logic circuit, and an optional clock loss detector for detecting clock inactivity and automatically initiating the static mode.