Abstract: An apparatus for monitoring a reference clock signal having a clock pulse train comprises a detecting block for counting pluses of a count clock signal to produce a count value and generate a count failure signal when the count value reaches a predetermined value, wherein the frequency of the count clock signal is larger than that of the reference clock signal; and a controlling block for generating a clear signal at every clock pulse of the reference clock signal to cleat the detecting block when the clear signal is inputted thereto.

Abstract: A system clock signal switching device capable of switching outputs from a plurality of clock signal generation systems i order to ensure the continuous supply of a stable system clock signal. An oscillation circuit A generates a clock signal CK1 as an ordinary system clock signal while an oscillation circuit B generates a clock signal CK2 as another separate clock signal, such as the time-count clock signal. The output lines of these circuits are connected with the input terminals of a multiplexer. An output clock signal monitor circuit checks the clock signal CK1 from the oscillation circuit A, wherein input terminals of the monitor are connected with the output lines to attain the operational clock signals for its monitoring operation. A monitor flag from the monitor circuit is supplied to a switching signal input terminal of the multiplexer via a line.

Abstract: An edge signal restoration circuit and method to enhance an edge of a signal decreases a rise and fall time of a propagating signal during transitions between logic states. The edge signal restoration circuit includes a first circuit to detect an edge of an input signal and to output a detection signal, and a second circuit to drive a next state of the input signal in response to the detection signal at approximately the same time as the first circuit detects the edge of the input signal. The edge signal restoration method detects a transition of the signal between a current state and a next state, and drives the next state onto the signal during its transition to that next state.

Abstract: A power shut-off and recovery circuit for data communication devices is provided. The power shut-off and recovery circuit has a power control circuit for polling a plurality of ports. The power control circuit determines how many of the ports are in an operational mode and compares the number of active ports to a predetermined number of ports. If the number of active ports is less than the predetermined number of ports, the power control circuit de-asserts an ENABLE signal. If the number of active ports is greater than or equal to the predetermined number of ports, the power control circuit asserts the ENABLE signal. A source transfer circuit is provided for selectively disengaging the data communication device from a power source in response to the ENABLE signal. The power control circuit re-polls all the ports and updates the ENABLE signal accordingly.

Abstract: The oscillation-stop detecting device accurately detects the stopping of a clock signal due to various causes. The voltage detecting circuit detects when a clock signal output from the clock signal oscillator remains at a high, a low or an intermediate level, and outputs a clock voltage detection signal. The oscillation-stop detecting circuit outputs a detection signal in response to the voltage detection signal.

Abstract: A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.

Abstract: There is disclosed a pulse-width controller which includes a first pulse-width adjusting section which adjusts the pulse width of a main pulse signal, a second pulse-width adjusting section which adjusts the pulse width of a reference pulse signal, a pulse-width measurement section which measures the pulse width of the reference pulse signal adjusted by the second pulse-width adjusting section, a target pulse-width setting section for setting a target pulse width to be achieved by the first pulse-width adjusting section, and a control section which outputs to the first pulse-width adjusting section a control signal for use in adjusting the pulse width of the main pulse signal in the first pulse-width adjusting section, on the basis of pulse-width information regarding the reference pulse signal measured in the pulse-width measurement section and the target pulse-width information set by the target pulse-width setting section.

Abstract: The disclosure is an operation control circuit of a power supply unit in a memory device which outputs a given operation control signal used for supplying a power supply voltage when a main control signal of the memory device is operating and additionally outputs the operation control signal in response to a sub control signal driven when the main control signal does not operate.

Abstract: A switch open-close state-detecting circuit for supplying an interrupt signal to a control terminal of a controller in response to a change of state of a switch to either open or closed state by giving a monitoring voltage to a plurality of switches to supply a change of the monitoring voltage corresponding to opening or closing of the switches to a plurality of input terminals of the controller by detecting the change of the monitoring voltage to supply to the control terminal of the controller for controlling the operation modes of the controller. The switch open-close state-detecting circuit has a control IC including the same number of a plurality of pairs of input terminal and a plurality of output terminals for generating interrupt signals at the output terminals only when supply voltages to pairs of input terminals of the control IC are not equal, and delay circuits connected between the input terminals of the control IC.

Abstract: A power semiconductor device (2) has a first main electrode (S) for coupling to a first supply line (3), a second main electrode (D) coupled to a first terminal (4) for connection via a load (L) to a second voltage supply line (5) and an insulated gate electrode (G) coupled to a control terminal (GT) for supplying a gate control signal to enable conduction of the power semiconductor device (2). An open-circuit detection arrangement is integrated with the power semiconductor device (2) for providing an indication that a load (L) coupled to the power semiconductor device (2) is open-circuited. The detection arrangement has a reference current (Ir) providing arrangement (7, R3, R4, R7, Q1, Q2) and a current deriving arrangement (Q3, Q4) for deriving a current (Id) dependent on the voltage at the second main electrode (D).

Abstract: An apparatus for use in a synchronous transmission system (STS) efficiently tests N clock signals provided from a device incorporated in the STS, wherein N is a positive integer larger than 1 and the N clock signals are represented by a first predetermined clock frequency. The N clock signals are first received by a counting device in response to a reset signal issued by a system controller in the STS to produce an error reference signal for each of the N received clock signals. And then, at a clock generator, a reference clock signal represented by a second predetermined clock frequency is provided. A first set of error detection signals for the N clock signals is derived based on the N clock signals, the reference clock signal and the error reference signals at a first error detection device. Thereafter, at a second error detection device, a second set of error detection signals for the N clock signals is obtained based on the reference clock signal and the error reference signals.

Abstract: In an input signal determining method and an apparatus for practicing the method, the level of an input signal is detected at least twice with a predetermined period, if the level of the input signal is significant when detected firstly, then before the second detection is started which is carried out in the predetermined period, whether or not the input signal is a continuous input signal whose level is maintained unchanged for a predetermined time is determined, and if the input signal is not the continuous input signal, the result of the first detection is reset, and if the level of the input signal is maintained for the predetermined time, and the level of the input signal is significant when detected secondly, then the input signal is determined as a correct input signal, whereby the erroneous recognition of the input signal can be avoided, and a noise equal in period to the synchronizing signal can be eliminated.

Abstract: A timing error detecting circuit detects a timing error of a measurement objective circuit by reading an input data in synchronism with rising or falling of a timing signal and outputting a first output data as a result of the process. The timing error detecting circuit includes a specification insertion circuit for providing an allowable specification value of a delay period relative to the timing signal, a signal processing detecting portion reading the first output data of the measurement objective circuit in synchronism with rising or falling of output of the specification insertion circuit and performing similar process to the measurement objective circuit for outputting a second output data, and a judgement circuit inputting the first and second output data of the measurement objective circuit and the signal processing detecting portion and making judgement of the timing error of the measurement objective circuit in synchronism with rising or falling of the specification insertion circuit.

Abstract: A clock failure detection circuit which monitors a clock by comparing the clock to at least one delayed version of itself is provided. The original clock and the delayed version will be offset, such that an edge of one of them can clock a logic circuit to determine if the clock is at the proper level. By setting up the delay so that a clock edge is generated when the clock signal should be low, for instance, a bad output signal will be provided whenever the clock is high instead. This could be caused by the clock being stuck high, or by an irregular pulse width.

Abstract: There is provided a time counting circuit which measures a pulse spacing of a pulse signal with a high accuracy and exhibits high resistance to variations in power-source voltage.A delay circuit ring consists of a plurality of delay circuits connected in a ring configuration and signal transition is caused to circulate around the delay circuit ring by oscillation. A switch-signal generating circuit outputs first and second switch signals based on the time at which a pulse signal to be measured rises. A row of sampling circuits consists of a plurality of sampling circuits connected to the output terminals of the respective delay circuits and samples the output signals from the delay circuits in response to a direction indicated by the first switch signal.

Abstract: A system for clamping a clock signal line that prevents clock glitching is disclosed. The system is comprised of a plurality of logic gates which generates a signal to clamp the clock signal line only on the occurrence of the clock signal line being low, a clock clamping signal 26 is generated indicating that a peripheral device wants to clamp the clock signal line, and a start condition is detected indicating that the clock signal line may be clamped.

Abstract: A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).

Abstract: A method and apparatus for detection of missing pulses from a repetitive pulse train including signal detection circuits for capturing the rising and/or falling edges of an input signal, time-stamping the captured edges, calculating the maximum and minimum instantaneous frequency over a specified time period, and displaying such frequency values. Instantaneous frequency values between any two adjacent edges are calculated based upon the time-stamps of the edges. The instantaneous frequency values in a specified time period are then sorted to find the minimum and maximum frequency values for that time period. These instantaneous frequency values are displayed in the form of a histogram evidencing the occurrence or lack of occurrence of missing pulses from the input signal.

Abstract: A pulse generator has an input and two outputs at which to respectively generate pulses in relation to different types of signal edges received at the input of the generator. The generator provides two distinct logic circuit blocks of the sequential type, the blocks being mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks, it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

Abstract: An electronic interface custom integrated circuit which provides interfacing between micro-controller devices and field effect transistors in truck or car anti-lock braking systems for controlling solenoid valves to modulate the pressure in the brake chambers or brake cylinders. The interface circuit includes built-in diagnostic and safety features including fault protection interlock, safety interlocks, status indication outputs and a special purpose analog output for enhancing the performance of anti-lock braking system electronic control units.

Abstract: A digital loss of lock detection (LLD) device for a phase looked loop (PLL) generates a locked frequency signal synchronized with a reference frequency signal. The LLD comprises first to fifth latching means for detecting when the reference clock failed high/low, when the locked clock failed high/low and when the reference clock is outside the tracking range of the PLL. The first to fifth latching means provide respectively a first to fifth error signals for each type of the above faults.

Abstract: A detector circuit operating in parallel with a bandwidth limited measurement channel in a measurement instrument generates a warning signal when an input signal exceeds a predetermined repetition rate or has a pulse width less than a predetermined value. To provide a warning signal to the measurement instrument that the input signal contains high frequency components that are likely to be missed by the measurement channel, the detector circuit operates in parallel with the measurement channel. A pulse width in the input signal that is sufficiently narrow or a repetition rate that is too high causes the detector to generate the warning signal that is provided to the measurement instrument.

Abstract: A clock system includes internal monitor circuitry such that the clock system is testable in a secure environment. In particular, the clock system includes a plurality of separately enableable clock generator circuit modules. Each of the clock generator circuit modules generates a separate clock signal when enabled. Combining circuitry receives the separate clock signals from those clock generator circuit modules which are enabled and derives a derived clock signal therefrom. Monitor circuitry receives the derived clock signal, detects whether there are transitions in the derived clock signal, and provides a monitor indication of a result of the detection. Thus, the clock system can be tested without providing the separate clock signals outside the clock system. Preferably, the clock system also includes a programmable clock control register that holds clock control data, the clock control data determining which of the clock generator circuit modules are enabled.

Abstract: A digital input is disclosed for supplying a digital signal representing the occurrence of a special event, such as a malfunction, to a recording device. The present invention can be advantageously used in a distribution network for electrical energy, in which the special event triggers the actuation of a switch in a switchgear. The digital input has two first current terminals, to which direct current is applied from an external voltage source. Two second current terminals are connected to a sensor element, for example an auxiliary contact of the switchgear, which outputs the digital signal when the special event occurs. An electrical circuit is also connected to the two second current terminals and carries the digital signal to an optocoupler which provides electrical isolation. The digital input furthermore has a device for converting the direct current supplied from outside the device into a direct current which is electrically isolated therefrom.

Abstract: A clock signal generation circuit is disclosed which receives a reference clock and detects, in response thereto, the loss of the reference clock. A phase comparator 13, detects the phase difference between the reference clock signal and an stabilized clock from a PLL synthesizer, a signal DOWNB state of the phase comparator 13 is fixed to "0" level at the time of loss of the reference clock signal where the reference clock can be fixed to "0" or "1" level. The signal DOWNB is monitored using a reference clock loss detection circuit 12. If the signal DOWNB stays at the "0" level for a prescribed length of time, the reference clock loss detection circuit 12 judges that the reference clock is lost and brings an XTALFAIL signal to the active state.

Abstract: A diagnostic device for testing a false warp stop in an industrial loom caused by a failing or offending drop wire. The device provides a connector that is operably engaged with the warp bars of an industrial loom. When a drop wire becomes worn or pliable and bridges the warp bar to stop the loom, the connector assists to create a circuit that includes the affected warp bar, a power source, a rectifier and an indicator device. The indicator device is activated by completion of the circuit and remains actuated even after the loom is restarted. The apparatus is thus effective to help locate a failing drop wire as opposed to a drop wire that has fallen due to a slack or broken warp thread.

Abstract: In a flag control circuit successively supplied with first and second input flag signals produced in relation to first and second results of calculations in an arithmetic and logic unit to produce a final output flag signal, the first input flag signal is latched by a primary flag signal latching circuit while the second input flag signal is latched by the secondary flag signal latching circuit. The first latched flag signal and the second latched flag signal are ANDed by an AND gate circuit to produce the final output flag signal.

Abstract: A frequency lock indicator (10) comprises a first delay (14), second delay (20), first sampler (24), second sampler (28), third sampler (32), fourth sampler (34), and lock indicator (36). The first delay (14) delays a rising edge of a frequency reference (12) which clocks the first sampler (24) on a rising edge and the third sampler (32) on a falling edge. The second delay (20) delays a rising edge of a feedback signal (18) to produce a delayed feedback signal (22) which clocks the second sampler (28) on a rising edge and the fourth sampler (34) on a falling edge. The first and third samplers sample an up-pump signal (26) and the second and fourth samplers sample a down-pump signal (30). The lock indicator (36) produces a lock indication signal (38) when the sampled up-pump signal substantially equal to the sampled down-pump signal.

Abstract: A method of monitoring abnormality of a clock driver in an electronic apparatus having a clock supply unit that supplies a clock signal and a plurality of function executing units to which the clock signal is inputted for executing prescribed functions at an identical clock, wherein each function executing unit is provided with a clock driver which, on the basis of the clock signal, oscillates internally to reproduce a clock signal, includes monitoring cut-off of an input clock signal and cut-off of an output clock signal of the clock driver, and outputting an alarm upon judging that the clock driver is abnormal in a case where the output clock signal has been cut off but the input clock signal has not.

Abstract: A sensor circuit is disclosed for use with a clock circuit providing a periodic timing signal to a clock output, wherein a timing reference for the periodic timing signal is provided by a crystal connected between a crystal input and a crystal output of the clock circuit, or alternatively provided by an external periodic logic signal coupled to the crystal input. The sensor circuit provides a sensor output in a first state, thereby indicating the presence of an external periodic logic signal timing reference, in response to at least a given number of large-signal voltage transitions on the crystal input within a certain period of time, and otherwise provides a second state on the sensor output, typically to indicate the presence of a crystal timing reference. Also disclosed is a clock circuit including a sensor circuit, and further including means for disabling a feedback resistor necessary for crystal operation when the timing reference is determined to be provided by an external periodic logic signal.

Abstract: A circuit monitors electronic devices which require continuous clocking for non-destructive operation. The circuit samples a repetitive signal, such as a clock, from a device of interest (DOI). If, for whatever reason, the clock signal becomes absent, the circuit responds by deactivating the DOI. If the clock revives or becomes intermittent the circuit will not reactivate the DOI. The circuit will reactivate the DOI only upon application of an explicit reset signal. The circuit is all digital and therefore technology independent, and provides for precise control of the deactivation response time.