Clock timing recovery methods and circuits

Abstract

A clock timing recovery circuit for recovering the clock timing from a baseband signal obtained by detection of a received signal. The clock timing is rapidly established using a clock signal which has been phase-shifted from the desired clock timing to sample the baseband signal, and by obtaining the optimum phase from the sampled signal obtained as a result. A clock-timing recovery circuit according to this invention does not require oversampling and provides easy optimization of circuit constants.

Claims

1. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling a baseband signal obtained by detection of a received signal, the baseband signal containing a recovery signal for clock timing recovery; and

control means for controlling the amount of phase shift of the phase shift means, wherein

said control means includes:

first means for causing the phase shift means to output the first clock signal for sampling the recovery signal, whereof a phase of the first clock signal n-th leading edge point or trailing edge point (n=1, 2, 3,... ) is phase shifted by n.times..DELTA.t from an origin defined by a chosen leading edge point or trailing edge point of the system clock signal, where.DELTA.t is a predefined amount of phase shift;

second means for estimating, from a sampled signal obtained by sampling the recovery signal, a phase difference between a phase of the system clock signal and a minimum bit error clock timing at which a bit error rate becomes a minimum, and which, on the basis of the estimated phase difference, said second means causes the phase shift means to output a corresponding clock timing for sampling the baseband signal that follows the recovery signal; and

a control switch for selectively switching control of the phase shift means from between the first means and the second means.

2. A clock timing recovery circuit according to claim 1, further comprising:

sampling clock generating means for generating a second clock signal having leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and for generating a third clock signal having leading or trailing edge points which lag behind the leading or trailing edge points of the first clock by the same timing difference.delta.t; and

means for selecting either the first clock signal, which is output from the phase shift means, as a sampling clock signal for sampling the recovery signal, or for selecting an output of the sampling clock signal generating means as the sampling clock for sampling the baseband signal that follows the recovery signal,

wherein said second means includes arithmetic means for calculating an amount of phase shift of the phase shift means by comparing decision errors obtained from the sampled signal at leading or trailing edge points that lead by.delta.t, with decision errors obtained from a sampled signal at leading or trailing edge points that lag by.delta.t.

3. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase shifted with respect to the system clock signal, as a clock timing for sampling a baseband signal obtained by detection of a received signal; and

control means for controlling an amount of phase shift of the phase shift means; and

sampling clock generating means for generating a second clock signal having leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and for generating a third clock signal having leading or trailing edge points which lag behind leading or trailing edge points of the first clock by the same timing difference.delta.t,

wherein the control means includes means for calculating an amount of phase shift of the phase shift means by using information relating to a phase error of the clock timing, the information being obtained respectively from sampled signals obtained by sampling the baseband signal using the second and the third clock signals as respective sampling clock signals.

4. A clock timing recovery circuit according to claim 3, wherein the information relating to the phase error is a decision error of a phase component of the sampled signals obtained by the sampling.

5. A clock timing recovery circuit according to claim 3, wherein the baseband signal is a signal obtained by coherent detection, and the information relating to the phase error comprises decision errors of signal points of the sampled signals obtained by the sampling.

6. A clock timing recovery circuit according to claim 3, wherein the baseband signal contains a clock timing recovery signal, and the information relating to the phase error comprises amplitudes of the sampled signals obtained by sampling the clock timing recovery signal.

7. A clock timing recovery circuit according to claim 6, further comprising:

means for shifting a timing of the first clock signal by a half period when a timing of the system clock signal and a clock timing of the baseband signal deviate by a half period.

8. A clock timing recovery circuit according to claim 3, wherein:

the sampling clock generating means includes means for alternately selecting the second clock signal or the third-clock signal and for outputting these as one clock signal; and

the control means compares the information relating to a phase error obtained alternately with respect to the second clock signal and the third clock signal.

9. A clock timing recovery circuit according to claim 3 wherein:

the sampling clock generating means outputs the second clock signal and the third clock signal separately; and

the control means compares the phase error related information obtained separately with respect to the second clock signal and the third clock signal.

10. A clock timing recovery circuit according to claim 9, wherein:

the baseband signal includes an in-phase channel signal and a quadrature channel signal;

the second clock signal is output as a sampling clock signal for one of the in-phase channel signal and the quadrature channel signal, and the third clock signal is output as a sampling clock signal for the other channel; and

the calculating means includes means for comparing the phase error related information obtained respectively from the in-phase channel and the quadrature channel.

11. A clock timing recovery circuit according to claim 3, wherein the second and the third clock signals generated by the sampling clock generating means are output to main signal lines as sampling clock signals for decoding digital data from the baseband signal.

12. A clock timing recovery circuit according to claim 3, wherein

the first clock signal is output to main signal lines as a sampling clock signal for decoding a transmitted signal from the baseband signal, the clock timing recovery circuit further comprising;

sampling means for using the second clock signal and the third clock signal to sample the baseband signal in separate lines from main signal lines; and

means for obtaining phase error related information from the output of this sampling means.

13. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling a baseband signal obtained by detection of a received signal;

control means for controlling an amount of phase shift of the phase shift means, the baseband signal containing a recovery signal for clock timing recovery;

sampling clock generating means for generating a second clock with leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and a third clock signal with leading or trailing edge points which lag behind the leading or trailing edge points of the first clock signal by the same timing difference.delta.t, wherein said control means includes:

first means for calculating an amount of phase shift of the phase shift means by comparing amplitudes of sampled signals respectively obtained by sampling the recovery signal using the second and the third clock signals respectively as sampling clock signals; and

second means for calculating the amount of phase shift of the phase shift means by comparing decision errors obtained from the sampled signals responsive to the baseband signal following the recovery signal being sampled using the second and the third clock signals respectively as sampling clock signals.

14. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling a baseband signal obtained by detection of a received signal;

control means for controlling an amount of phase shift of the phase shift means on the basis of decision errors obtained from sampled signals obtained by sampling the baseband signal and

sampling clock generating means for generating and outputting as a sampling clock signal for main signal lines a second clock signal which alternately has a leading edge or trailing edge point which leads a leading edge or trailing edge point of the first clock signal by a predefined timing difference.delta.t, and a leading edge or trailing edge point which lags behind a leading edge or trailing edge point of the first clock signal by the same timing difference.delta.t, wherein

the control means includes arithmetic means for comparing decision errors obtained from sampled signals at the leading edge or trailing edge point that leads by.delta.t, with decision errors obtained from sampled signals at the leading edge or trailing edge point that lags by.delta.t, and on this basis the arithmetic means calculates the amount of phase shift of the phase shift means.

15. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling, in main signal lines, a baseband signal obtained by detection of a received signal;

control means for controlling an amount of phase shift of the phase shift means on the basis of decision errors obtained from sampled signals obtained by sampling the baseband signal;

sampling clock generating means for generating a second clock signal which alternately has a leading edge or trailing edge point which leads a leading edge or trailing edge point of the first clock signal by a predefined timing difference.delta.t, and a leading edge or trailing edge point which lags behind a leading edge or trailing edge point of the first clock signal by the same timing difference.delta.t; and

sampling means for using the second clock signal to sample the baseband signal in separate lines from the main signal lines,

wherein the control means includes arithmetic means for comparing decision errors obtained from sampled signals at the leading edge or trailing edge point that leads by.delta.t, with decision errors obtained from sampled signals at the leading edge or trailing edge point that lags by.delta.t, and on this basis the arithmetic means calculates the amount of phase shift of the phase shift means.

16. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling a baseband signal obtained by detection of a received signal;

control means for controlling an amount of phase shift of the phase shift means on the basis of one of decision errors of phase components of sampled signals obtained by sampling the baseband signal, and decision errors of signal points of the sampled signals obtained by sampling the baseband signal; and

sampling clock generating means for generating and for outputting, as a sampling clock signal for main signal lines, a second clock signal which alternately has a leading edge or trailing edge point which leads a leading edge or trailing edge point of the first clock signal by a predefined timing difference.delta.t, and a leading edge or trailing edge point which lags behind a leading edge or trailing edge point of the first clock signal by the same timing difference.delta.t, wherein

the control means includes arithmetic means for comparing decision errors of phase components obtained from sampled signals at a leading edge or trailing edge point that leads by.delta.t, with decision errors of the phase components obtained from sampled signals at the leading edge or trailing edge point that lags by.delta.t, and on this basis calculates the amount of phase shift of the phase shift means.

17. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling a baseband signal obtained by coherent detection; and

control means for controlling an amount of phase shift of the phase shift means on the basis of decision errors of signal points of sampled signals obtained by sampling the baseband signal; and

sampling clock generating means for generating a second clock signal with leading or trailing edge points which lead the leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and a third clock signal with leading or trailing edge points which lag behind the leading or trailing points of the first clock signal by the same timing difference.delta.t, and which outputs the second clock signal as the sampling clock signal for one of an in-phase channel and a quadrature channel in main signal lines, and outputs the third clock signal as the sampling clock signal for the other channel, wherein

the control means includes arithmetic means for comparing decision errors respectively obtained from the sampled signals in the in-phase and quadrature channels, and on this basis calculates the amount of phase shift of the phase shift means.

18. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling, in main signal lines, a baseband signal obtained by quasi-coherent or coherent detection;

control means for controlling an amount of phase shift of the phase shift means on the basis of one of decision errors of phase components of sampled signals obtained by sampling the baseband signal and decision errors of signal points of the sampled signals;

sampling clock generating means for generating a second clock signal which alternately has a leading edge or trailing edge point which leads a leading edge or trailing edge point of the first clock signal by a predefined timing difference.delta.t, and a leading edge or trailing edge point which lags behind a leading edge or trailing edge point of the first clock signal by the same timing difference.delta.t; and

sampling means for using the second clock signal to sample the baseband signal in separate lines from the main signal lines,

wherein the control means includes arithmetic means for comparing decision errors obtained from the sampled signals at a leading edge or trailing edge point that leads by.delta.t, with decision errors obtained from the sampled signals at the leading edge or trailing edge point that lags by.delta.t, and on this basis the arithmetic means calculates the amount of phase shift of the phase shift means.

19. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling, in main signal lines, a baseband signal obtained by coherent detection;

control means for controlling an amount of phase shift of the phase shift means on the basis of decision errors of signal points of sampled signals obtained by sampling the baseband signal;

sampling clock generating means for generating a second clock signal with leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and a third clock signal with leading or hailing edge points which lag behind the leading or trailing edge points of the first clock signal by the same timing difference.delta.t; and

sampling means for using the second clock signal to sample, in separate lines from the main signal lines, the baseband signal in one of an in-phase channel and a quadrature channel, and which uses the third clock signal to sample the baseband signal in the other of the in-phase and the quadrature channel,

wherein the control means includes arithmetic means for using decision errors obtained from the sampled signals of the in-phase and quadrature channels, and on this basis calculates the amount of phase shift of the phase shift means.

20. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means first outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling a baseband signal obtained by detection of a received signal;

control means for controlling an amount of phase shift of the phase shift means on the basis of an amplitude of sampled signals obtained by sampling a clock timing recovery signal contained in the baseband signal; and

sampling clock signal generating means for generating and for outputting as a sampling clock signal for main signal lines, a second clock signal which alternately has a leading edge or trailing edge point which leads a leading edge or trailing edge point of the first clock signal by a predefined timing difference.delta.t, and a leading edge or trailing edge point which lags behind a leading edge or trailing edge point of the first clock signal by the same timing difference.delta.t, wherein

the control means includes arithmetic means for comparing, with respect to the sampled signals obtained by sampling using the sampling clock signal, the amplitude of the sampled signal at the leading edge or trailing edge point that leads by.delta.t, and the amplitude of the sampled signal at the leading edge or trailing edge point that lags by.delta.t, and on the basis of a result of this comparison, calculates the amount of phase shift of the phase shift means.

21. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling a baseband signal obtained by detection of a received signal;

control means for controlling an amount of phase shift of the phase shift means on the basis of an amplitude of sampled signals obtained by sampling a clock timing recovery signal contained in the baseband signal; and

sampling clock generating means for generating a second clock signal with leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and a third clock signal with leading or trailing edge points which lag behind the leading or trailing edge points of the first clock by the same timing difference.delta.t, and for outputting the second clock signal as a sampling clock signal for one of an in-phase channel and a quadrature channel in main signal lines, and for outputting the third clock signal as the sampling clock signal for the other of the in-phase or quadrature channel,

wherein the control means includes arithmetic means for comparing the amplitudes of the sampled signals in the in-phase and quadrature channels, and on the basis of a result of this comparison, calculates the amount of phase shift of the phase shift means.

22. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling, in main signal lines, a baseband signal obtained by detection of a received signal;

control means for controlling an amount of phase shift of the phase shift means on the basis of an amplitude of sampled signals obtained by sampling a clock timing recovery signal contained in the baseband signal;

sampling clock generating means for generating a second clock signal which alternately has a leading edge or trailing edge point which leads a leading edge or trailing edge point of the first clock signal by a predefined timing difference.delta.t, and a leading edge or trailing edge point which lags behind a leading edge or trailing edge point of the first clock signal by the same timing difference.delta.t; and

samplings means for using the second clock signal to sample the baseband signal in separate lines from the main signal lines,

wherein the control means includes arithmetic means for comparing, with respect to the sampled signals obtained by the sampling means, the amplitude of the sampled signal at a leading edge point or trailing edge point which leads by.delta.t, and the amplitude of the sampled signal at a leading edge point or trailing edge point which lags by.delta.t, and on the basis of a result of the comparison, the arithmetic means calculates the amount of phase shift of the phase shift means.

23. A clock timing recovery circuit comprising:

clock generating means for generating a system clock signal which repeats with a fixed period;

phase shift means for outputting a first clock signal, phase-shifted with respect to the system clock signal, as a clock timing for sampling, in main signal lines, a baseband signal obtained by detection of a received signal;

control means for controlling an amount of phase shift of the phase shift means on the basis of an amplitude of sampled signals obtained by sampling a clock timing recovery signal contained in the baseband signal;

sampling clock generating means for generating a second clock signal with leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and a third clock signal with leading or trailing edge points which lag behind the leading or trailing edge points of the first clock signal by the same timing difference.delta.t; and

sampling means for using the second clock signal to sample, in separate lines from the main signal lines, the baseband signal in one of an in-phase channel and a quadrature channel, and for using the third clock signal to sample the baseband signal in the other of the in-phase and quadrature channel,

wherein the control means includes arithmetic means for comparing the amplitudes of the sampled signals in the in-phase and quadrature channels, and on the basis of a result of the comparison, the arithmetic means calculates the amount of phase shift of the phase shift means.

24. A clock timing recovery method for recovering, from a recovery signal for clock timing recovery contained in a baseband signal obtained by detection of a received signal, a clock timing for sampling the baseband signal that follows the recovery signal, said method comprising:

forming, as a sampling clock signal, a clock signal whereof a phase of its n-th leading edge point or trailing point (n=1, 2, 3,... ) from an origin, where one leading edge point or trailing edge point of a system clock signal which repeats with a fixed period is taken as the origin, is shifted by n.times..DELTA.t relative to a phase of a system clock signal where.DELTA.t is a predefined amount of phase shift;

sampling the recovery signal using the sampling clock signal;

estimating, from sampled signals obtained by the sampling step, a phase difference between a phase of the system clock signal and a clock timing at which a bit error rate is a minimum; and

recovering a clock timing for sampling the baseband signal that follows the recovery signal, by causing the phase of the system clock signal to shift by an estimated amount of phase difference.

25. A clock timing recovery method for recovering clock timing on the basis of decision errors of sampled signals obtained by sampling a baseband signal, said method comprising:

generating, from a first clock signal obtained by phase shifting a system clock signal which repeats with a fixed period, a second clock signal with leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and a third clock signal with leading or trailing edge points which lag behind the leading or trailing edge points of the first clock signal by the same timing difference.delta.t, the second and the third clock signals serving as sampling clock signals for main signal lines;

obtaining decision errors from the sampled signals obtained by using the sampling clock signals to sample the baseband signal;

calculating an amount of phase shift to be applied to the first clock signal on the basis of a result of comparing the decision errors obtained from the sampled signals at the leading edge or trailing edge point of the second clock signal, with the decision errors obtained from the sampled signals at the leading edge or trailing edge point of the third clock signal; and

shifting a phase of the system clock signal on the basis of the amount of phase shift.

26. A clock timing recovery method for recovering clock timing on the basis of decision errors of sampled signals obtained by sampling a baseband signal, said method comprising:

outputting, as a sampling clock signal for main signal lines, a first clock signal obtained by phase shifting a system clock signal which repeats with a fixed period, and forming a second clock signal with leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and a third clock signal with leading or trailing edge points which lag behind the leading or trailing edge points of the first clock signal by the same timing difference.delta.t;

obtaining decision errors from the sampled signals obtained using the second and third clock signals to sample the baseband signal separately from the main signal lines;

calculating an amount of phase shift to be applied to the first clock signal on the basis of a result of comparing the decision errors obtained from the sampled signals at the leading edge or trailing edge point of the second clock signal, with the decision errors obtained from the sampled signals at the leading edge or trailing edge point of the third clock signal; and

shifting a phase of the system clock signal on the basis of the amount of phase shift.

27. A clock timing recovery method for recovering, from a recovery signal for clock timing recovery contained in a baseband signal obtained by detection of a received signal, a clock timing required for decoding the baseband signal, said method comprising:

forming, from a first clock signal obtained by phase shifting a system clock signal which repeats with a fixed period, a second clock signal with leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and a third clock signal with leading or trailing edge points which lag behind the leading or trailing edge points of the first clock signal by the same timing difference.delta.t, the second and the third clock signals serving as sampling clock signals for main signal lines;

sampling the recovery signal using the sampling clock signals;

comparing, with respect to sampled signals obtained by the sampling step, an amplitude of the sampled signal at the leading edge point or trailing edge point of the second clock signal, with the amplitude of the sampled signal at the leading edge point or trailing edge point of the third clock signal;

calculating an amount of phase shift to be applied to the first clock signal on the basis of a result of the comparing step; and

recovering the clock timing by shifting a phase of the system clock signal on the basis of the amount of phase shift.

28. A clock timing recovery method for recovering, from a recovery signal for clock timing recovery contained in a baseband signal obtained by detection of a received signal, a clock timing required for decoding the baseband signal, said method comprising:

outputting, as a sampling clock for main signal lines, a first clock signal obtained by phase shifting a system clock signal which repeats with a fixed period, and forming a second clock signal with leading or trailing edge points which lead leading or trailing edge points of the first clock signal by a predefined timing difference.delta.t, and a third clock signal with leading or trailing edge points which lag behind the leading or trailing edge points of the first clock signal by the same timing difference.delta.t;

sampling the recovery signal using the second and the third clock signals, in separate lines from main signal lines;

comparing, with respect of sampled signals obtained by the sampling step, an amplitude of the sampled signal at a leading edge point or a trailing edge point of the second clock signal, with an amplitude of the sampled signal at the leading edge point or trailing edge point of the third clock signal;

calculating an amount of phase shift to be applied to the first clock signal on the basis of results of the comparing step; and recovering the clock timing by shifting a phase of the system clock signal on the basis of the amount of phase shift.