Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.

Abstract: Circuitry of a physical layer for interfacing with a communication bus of a wired local area network is disclosed. The circuitry includes a variable delay driver operably coupled to a communication bus. The communication bus includes a shared transmission medium. The variable delay driver is configured to control a slew rate of a driven transmit signal at the driver output. The circuitry also includes receiver circuitry operably coupled to the communication bus. The circuitry further includes a common mode dimmer operably coupled to the receiver circuitry and the communication bus. The common mode dimmer is configured to protect the receiver circuitry from common mode interference.

Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.

Abstract: In accordance with various embodiments, a circuit is provided, including an output node, a first potential varying stage, which is designed to couple the output node to a supply potential in reaction to an input signal, and a second potential varying stage, which is designed to couple the output node to the supply potential if the difference between the potential of the output node and the supply potential lies below a predefined threshold value.

Abstract: A delay circuit includes a first flip flop (FF), a transistor connected to the FF, a first resistor capacitor circuit (RCC) coupled to the transistor and between a voltage and a ground, a first comparator for comparing an output of the first RCC and a voltage reference, gate logic coupled to the input line and to an output of the first FF and to a second FF, a second transistor coupled to the second FF, a second RCC coupled to the second transistor and between the voltage and ground, a second comparator for comparing an output of the second RCC and the voltage reference and coupled to the first FF, and output logic coupled to the first and second comparators.

Abstract: According to an embodiment, a load adjusting circuit adjusts the load of an inverter circuit based on a threshold voltage of a first conductive type transistor provided on the inverter circuit, and a driving force adjusting circuit adjusts the driving force of the inverter circuit based on the threshold voltage of the first conductive type transistor.

Abstract: Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.

Abstract: An integrated circuit may include a delay circuit that receives an input signal at a first logic level and produces a delayed output signal at a second logic level at an output terminal. The integrated circuit may include a preset circuit coupled to the delay circuit. The preset circuit may receive the input signal and pre-drive the delayed output signal to an intermediate logic level that lies between the first and second logic levels.

Abstract: Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.

Abstract: A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: A latch circuit which can control a drain avalanche effect and improve reliability is provided. The latch circuit includes an input transistor importing a voltage corresponding to “0” or “1” when the scanning voltage is input to a gate, a storage capacitance storing a voltage imported by the input transistor, and having a first electrode and a second electrode, the first electrode is input with a capacitance control signal and the second electrode is connected to a second electrode of the input transistor, a first conduction type first transistor having a gate connected to the second electrode of the input transistor, a second electrode connected to a first output terminal, and a first electrode input with a first latch control signal, and a second conduction type second transistor having a gate connected to the second electrode of the first transistor, a second electrode connected to a second output terminal, and a first electrode input with a second latch control signal.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values. The delay stage includes M parallel-coupled inverter stages. Each parallel-coupled inverter stage includes N pairs of stacked PMOS transistors and stacked NMOS transistors. The N transistor pairs have configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of the configurable source-drain node connections to adjust a delay value of each of the M inverter stages.

Abstract: A variable delay circuit includes delay units connected in series. Each delay unit includes first to third logic gates. The first logic gates are connected in series so that the output of the previous stage is input to one of inputs of the subsequent stage and first control data is input to the other of the inputs. In each stage, one of inputs of the second logic gate is connected to the one of the inputs of the first logic gate and second control data is input to the other of the inputs. The third logic gates are connected in series, the output of the second logic gate is input to third logic gate, and the delay time of a path from one of the inputs to the output and the delay time of a path from the other of the inputs to the output are substantially the same.

Abstract: A system and method for characterizing process variations are provided. A circuit comprises a plurality of inverters arranged in a sequential loop, and a plurality of transmission gates, with each transmission gate coupled between a pair of serially arranged inverters. Each transmission gate comprises a first field effect transistor (FET) having a first channel, and a second FET having a second channel. The first channel and the second channel are coupled in parallel and a gate terminal of the first FET and a gate terminal of the second FET are coupled to a first control signal and a second control signal, respectively.

Abstract: An integrated circuit 2 includes processing circuitry that includes a plurality of critical path circuits 4, 6, 8, 10. These critical path circuits include variable delay circuits 16 which add an additional delay in to the path delay through the critical paths so as to adjust the path delay to match a target path delay. Variable delay circuit 18 includes a tank capacitor 22 which is charged or discharged to generate a control voltage. This control voltage serves to control a power supply voltage fed to an inverter chain 28. Variation in the power supply voltage of the inverter chain 28 adjust the propagation speed of a processing signal through the inverter chain 28 and accordingly adjusts the additional delay imposed by the variable delay circuit.

Abstract: A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage.

Abstract: A digital time delay circuit is provided in which fabrication process variations and temperature effects on the switching threshold level of digital circuits utilized in the timing delay circuits are substantially eliminated.

Abstract: Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks.

Abstract: Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.

Abstract: Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltage at a gate, and outputs a drain current according to the control voltage; a correction section connected in parallel to a source and a drain of the current controlling MOS transistor, and outputs a correction current on a monotonic decrease as the drain current increases in a range larger than a predetermined boundary current within a normal usage range of the drain current; and a delay element running an output current resulting from adding the correction current to the drain current, between the delay element and an output terminal of the variable delay circuit, in changing a signal value of the output signal according to the input signal.

Abstract: A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.

Abstract: A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.

Abstract: Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.

Abstract: The accuracy of the delay amount to be imparted to a timing signal is improved by increasing the delay amount obtained by a first stage of a delay element. A variable delay 50 which comprises a DA converter 51 which supplies current 51 based on delay setting data; a delay element 53 which imparts a delay amount Tpd to a prescribed signal and outputs the signal; and a bias circuit 52 which is connected such that the amount of current flown in the DA converter 51 and the amount of current flown in the delay element 53 become equal, wherein the DA converter 51 allows the relationship between the delay setting data DATA and the current Id to be hyperbolic (inversely proportional). As a result, the relationship between the delay setting data DATA and the delay amount Tpd can be linear, whereby the delay amount obtained by a first stage of the delay element can be widened.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a circuit adapted to cause an actuation of an output device according to a control output. The control output can be generated comprising a control signal, the control signal extracted from a sequence of clock pulses. The sequence of clock pulses can comprise the control signal.

Abstract: A timer circuit is disclosed. The timer, having a delay configured to track inversely with temperature of the memory device, includes a reference signal configured to increase in voltage, as the temperature of the memory device increases. The reference signal may be generated from a current that is derived from a bandgap reference circuit. The timer circuit includes a pull-down path made up of a plurality of selectable pull down transistors which are coupled to the reference signal at the gate. Resistance of the pull-down path is reduced as the reference signal is increased and the reduced resistance of the pull-down path decreases the delay of timer. A plurality of selectable delay elements may be preconfigured to adjust the delay and are coupled to the output path of the current starved inverter.

Abstract: A sense amplifier enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator.

Abstract: A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal.

Abstract: One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

Abstract: Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltage at a gate, and outputs a drain current according to the control voltage; a correction section connected in parallel to a source and a drain of the current controlling MOS transistor, and outputs a correction current on a monotonic decrease as the drain current increases in a range larger than a predetermined boundary current within a normal usage range of the drain current; and a delay element running an output current resulting from adding the correction current to the drain current, between the delay element and an output terminal of the variable delay circuit, in changing a signal value of the output signal according to the input signal.

Abstract: Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.

Abstract: The delay time variation of transistors caused by the manufacturing variation is desired to be adjusted. A relation table storing a relation between sizes and voltage values (supply voltages and bias voltages) is provided. Macros each of which includes a transistor and a setting voltage generation circuit for applying a setting voltage to the transistor are formed on a chip. A process data indicating a size of the transistor is generated. The voltage value corresponding to the size of the transistor indicated by the process data in the relation table is selected as an optimum voltage value (supply voltage Vdd, bias voltage Bias) for each of the macros. The setting voltage of each of the macros is set to the optimum voltage value. The delay time can be adjusted without requiring a detection circuit for detecting the delay time.

Abstract: According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Abstract: A variable delay element includes first and second input stages, each input stage comprising a charge pumping circuit and a discharging circuit, each charge pumping circuit and each discharging circuit associated with the first and second input stages configured to operate on opposite phases of an input signal, and an output stage comprising at least two transistors. The transistors are independently controlled by the first and second input stages and produce an output signal which is a delayed version of the input signal.

Abstract: A pulse width modulator (100) and method that facilitates high resolution pulse width modulation is provided. The pulse width modulator (100) creates a pulse width modulated signal having a duty cycle that is proportional to a controllable delay in the modulator. The pulse width modulator combines a first digitally controllable delay (102) with a delay adjustment (104) to provide the controllable delay. In one embodiment, a digital counter (202) is used to provide coarse delay, with the delay adjustment device (210) coupled to the digital counter (202) to provide the fine, high resolution, delay control. Together the digital counter (202) and delay adjustment device (210) provide high resolution pulse width modulation. In one particular implementation, the analog delay adjustment device (100) comprises a delay block (500) designed to provide delay adjustment that is selectively controllable by changing a capacitance in the device.

Abstract: Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

Abstract: A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit.

Abstract: A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract: A duty ratio correction circuit includes: a first switching amplifier circuit into which an input pulse signal is input; a current control device connected with the switching device for controlling a current in accordance with a bias voltage signal; a waveform shaping circuit that correct an output of the first switching amplifier circuit; a first integration circuit that integrates a corrected output; a reference voltage setting unit that sets a reference voltage signal defining a duty ratio; a comparator circuit that compares an output of the first integration circuit with the reference voltage signal; a second switching amplifier circuit that includes a switching device connected in series with a constant current circuit, the switching device using a comparison judgment signal as a gate signal; and a second integration circuit that integrates an output of the second switching amplifier circuit and outputs the bias voltage signal.

Abstract: A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.

Abstract: To provide a semiconductor integrated circuit device that reduces charging and discharging currents flowing through clock tree synthesis, thereby reducing current consumption of entire circuits of the semiconductor integrated circuit device. In a semiconductor integrated circuit device including a clock synchronous type circuit that operates in synchronization with either of rising and falling edges flank of a reference clock and a plurality of clock buffer circuits for distributing the reference clock to the clock synchronous type circuit, each clock buffer circuit is constituted from a first transistor that drives a load at one of the edges flank of the reference clock with which the clock synchronous type circuit does not operate in synchronization and a second transistor that drives the load at the other edge flank of the reference clock. A gate width of the first transistor is set so that a change in the edge flank is slowed down, provided that a pulse waveform of the reference clock is not destroyed.

Abstract: A current controlled delay circuit is disclosed. Two currents of constant sum are generated to control the delay of the circuit. The circuit includes a differential pair to switch one of the two currents from one leg of the circuit to another leg of the circuit. The circuit includes a cross-coupled pair to switch the other of the two currents from one leg of the circuit to another leg of the circuit. The circuit may include a fixed or variable load.

Abstract: A ring oscillator stage includes two differential transistor pairs configured to add an adjustable amount of delay to a differential input signal. Each differential pair is biased with a bias current transistor; the bias current transistor is “protected” by a voltage-clamping transistor that limits the drain voltage of the bias current transistor. The voltage-clamping transistors enable use of a power supply voltage (VDD) that would otherwise exceed the reliability breakdown voltage limit of the bias current transistors.

Abstract: A delay circuit delays an input signal to produce an output signal. The input and output signals have a delay which is based on a signal relationship between the input signal and a reference signal. The delay circuit includes configurable devices to vary the reference signal to adjust the delay between the input and output signals.

Abstract: Balanced programmable delay element that has a variable incremental delay. A first inverter is provided that has a first electrode for receiving an input signal, a second electrode, a third electrode, and a fourth electrode for providing an output signal and that has a propagation delay that is dependent on a first current. A second inverter is provided that has a first electrode coupled to the fourth electrode of the first inverter for receiving the output signal of the first inverter, a second electrode, a third electrode, and a fourth electrode for providing an output signal and that has a propagation delay that is dependent on a second current. A current switch is coupled to the first inverter, the second inverter, receives at least two control signals, and responsive thereto, selectively varies the incremental delay of the delay element.

Abstract: An apparatus for minimizing a skew occurring due to a change of data pattern by previously recognizing data pattern before data is outputted from the semiconductor device. The apparatus of compensating for a phase delay in a semiconductor device having a delay locked loop (DLL) for generating DLL clock includes: a data pattern detection block for detecting patterns of data loaded on data line and determining delay compensation amount of the data inputted to data output driver based on the detected data patterns; and a delay compensation block for compensating for phase delay of clock relating to the DLL clock inputted to the data output driver under a control of an output signal of the data pattern detection block.

Abstract: A system and method are provided for replacing dedicated external termination resistors typically used to implement an asymmetrical unidirectional bus I/O standard with programmable resistances that are dynamically selected by programming output driver circuits having digitally controlled impedances.

Abstract: A clock pulse generator includes an input terminal, an input bias setting circuit, first and second pulse shaping circuit and a pulse combining circuit. The input terminal receives a sinusoidal signal. The input bias setting circuit generates an addition sinusoidal signal having a predetermined bias voltage as a central voltage level thereof. The first and second shaping circuits are connected to the input bias setting circuit. The first shaping circuit has a first threshold voltage that is higher than the predetermined voltage and is responsive to the addition sinusoidal signal to generate a first pulse signal. The second shaping circuit has a second threshold voltage that is lower than the predetermined voltage and is responsive to the addition sinusoidal signal to generate a second pulse signal. The pulse combining circuit synchronizes either of the rising edge or the falling edge of the first pulse signal with that of the second pulse signal so as to generate an output clock pulse.

Abstract: A method and apparatus for reducing jitter in a delay line and trim unit is described. The trim unit includes a plurality of delay elements in parallel. At least one of the plurality of delay elements is controllable between on and off states. At least one of the plurality of delay elements includes at least one filter element to filter local supply noise. At least one of the plurality of delay elements includes a plurality of delay circuits having at least one gated delay circuit to control propagation of a clock signal through the plurality of delay circuits. The plurality of delay elements are configured to maintain an overall propagation delay without adding additional circuitry by sizing at least one delay circuit to provide longer propagation delay and sizing the other delay circuits to provide smaller propagation delay. The plurality of delay circuits are sized and arranged to minimize jitter.