Abstract: An apparatus may include a delay line having a first delay value corresponding to first operating conditions of the apparatus and a second delay value corresponding to second operating conditions of the apparatus. A monitoring circuit may monitor a time taken for a first clock edge of a clock signal to propagate through the delay line. A determining circuit may determine whether operating conditions of the apparatus are acceptable in response to the time taken.

Abstract: A method and an apparatus from such method for designing an integrated circuit (IC) that mitigates the effects of process, voltage, and temperature dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits. Conventional design process takes into account power supply voltage Vdd as a variable that must be considered in a skewed corner analysis. The disclosure teaches that the IC design process can be substantially simplified by essentially factoring out voltage based variations in corner lot analysis for IC designs that include dynamic voltage scaling circuitry, because each fabricated IC die of an IC design having dynamic voltage scaling can individually adjust the applied supply voltage Vdd within a range to offset local process-induced variations in the performance of that specific IC die.

Abstract: A method for controlling charging of a secondary cell including a positive electrode containing a positive-electrode active substance having that increases resistance in accordance with an increase in the SOC, a negative electrode; and a non-aqueous electrolyte includes performing constant-current charging at a set current value to a prescribed upper-limit voltage, performing constant-voltage charging at the upper-limit voltage after the upper-limit voltage V1 has been reached, and terminating charging of the secondary cell when the charging current in the constant-voltage charging has decreased to a cutoff current value, the cutoff current value being set to a current value that complies with the relationships in formulas (I) and (II): Cutoff current value A2?set current value A1×X??(I) X=(cell resistance R1 of secondary cell in target SOC [?]×set current value A1 [A])/upper-limit voltage V1 [V].

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a first electrode, and a second semiconductor chip including a second electrode connected to the first electrode. One of the first and second semiconductor chips includes a first temperature sensor circuit generating a first detection signal, the first detection signal taking a first level when a temperature is equal to or higher than a first temperature, the first detection signal taking a second level when the temperature is lower than the first temperature; and a first delay code generation circuit outputting a first delay code signal in response to the first level of the first detection signal, and outputting a second delay code signal different from the first delay code signal in response to the second level of the first detection signal.

Abstract: An apparatus for providing time adjustment of an input signal includes a coarse timing digital-to-analog converter (DAC), a replica delay element and an interpolator. The coarse timing DAC has multiple delay settings for providing a coarse timing adjustment of the input signal, and outputs a first delayed signal by delaying the input signal by a first delay time corresponding to a selected setting of the multiple delay settings. The replica delay element receives the first delayed signal from the coarse timing DAC and outputs a second delayed signal by delaying the first delayed signal by a predetermined second delay time. The interpolator blends either the input signal and the first delayed signal or the first delayed signal and the second delayed signal for providing a fine timing adjustment of the input signal, and outputs a timing adjusted output signal including the coarse timing adjustment and the fine timing adjustment.

Abstract: A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.

Abstract: A panel display device is provided, which includes: a transparent back panel having a first surface and a second surface, where the first surface is adapted for reflecting incident lights from the outside, and the second surface is adapted for transmitting lights from the outside; a backlight source, disposed at one side of the second surface of the transparent back panel, which is adapted for emitting lights to the transparent back panel; a polarized grating, disposed at one side of the first surface of the transparent back panel, which includes a plurality of grating strips with gaps formed between neighboring grating strips, where the polarized grating enables the incident lights from the transparent back panel to be polarized and then pass through the gaps; a semiconductor switch array; and a transmission light valve array. The panel display device of the disclosure increase the utilization efficiency of lights.

Abstract: Representative implementations of devices and techniques provide a time delay based on an input value. A digital delay may be generated based on a coarse delay and a fine delay. The coarse delay may be selected based on the input value. The fine delay may be selected from an overlapping set of fine delay intervals, based on the selected coarse delay. In some implementations, a control component may be used to select the fine delay when more than one fine delay interval is indicated.

Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.

Abstract: Techniques for fixing hold violations using metal-programmable cells are described herein. In one embodiment, a system comprises a first flip-flop, a second flip-flop, and a data path between the first and second flip-flops. The system further comprises a metal-programmable cell connected to the data path, wherein the metal-programmable cell is programmed to implement at least one capacitor to add a capacitive load to the data path. The capacitive load adds delay to the data path that prevents a hold violation at one of the first and second flip-flops.

Abstract: A ring oscillator (RO) based Design-For-Trust (DFTr) technique is described. Functional paths of integrated circuit (IC) are included in one or more embedded ROs by (1) selecting a path in the IC, based on path selection criteria, that has one or more unsecured gates, and (2) embedding one or more ROs on the IC until a stop condition is met. An input pattern to activate embedded RO is determined. Further, a golden frequency which is a frequency at which the embedded RO oscillates, and a frequency range of the embedded RO are determined. A Trojan in the IC may be detected by activating the embedded RO (by applying the input pattern), measuring a frequency at which the embedded RO oscillates, and determining whether or not a Trojan is present based on whether or not the measured frequency of the RO is within a predetermined operating frequency range of the RO.

Abstract: A method of and circuit for improving stabilization of a non-Foster circuit. The method comprises steps of and the circuit includes means for measuring a noise hump power at an antenna port or an output port of the non-Foster circuit, comparing the measured noise hump power with a desired level of noise power that corresponds to a desired operating state of the non-Foster circuit, and tuning the non-Foster circuit to generate the desired level of noise power to achieve the desired operating state of the non-Foster circuit.

Abstract: A pulse generator comprising: an input for receiving a trigger; an output node for outputting a signal; a delay line comprising one or more delay units and a plurality of taps; one or more pull-up devices each connected to the output node for increasing the output voltage on the output node; and/or one or more pull-down devices each connected to the output node for decreasing the output voltage on the output node; wherein the taps of the delay line are operably connected to the pull-up and/or pull-down devices such that a trigger passing along the delay line activates one or more of the pull-up and/or one or more of the pull-down devices more than once. Re-use of the pull-up and/or pull-down devices enables longer and more complex pulse shapes, such as high-order Gaussian pulse shapes to be produced while keeping the number of components low, thus reducing chip area, power requirements and parasitic capacitance.

Abstract: An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.

Abstract: In an embodiment, a delay circuit includes a delay line with a clock input signal and a delayed clock output signal that is based on a setting value. Each delay element of the delay line receives one of several delay element select signals and outputs a delayed signal based on the delay element select signal. The setting value may be a binary encoded value representing the desired delay. The delay element select signals may correspond to a thermometer encoded value of the binary encoded setting value.

Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.

Abstract: An apparatus for delaying a plurality of chain-based time-to-digital circuits (TDCs). The apparatus includes a plurality of propagation path devices each connected to a respective one of the plurality of TDCs, each propagation path device delays a common start signal by a selectable amount based on a delay selection signal received by the propagation path device, and transmits the delayed start signal to the respective one of the TDCs.

Abstract: In an embodiment, a delay circuit includes a delay line with a clock input signal and a delayed clock output signal that is based on a setting value. Each delay element of the delay line receives one of several delay element select signals and outputs a delayed signal based on the delay element select signal. The setting value may be a binary encoded value representing the desired delay. The delay element select signals may correspond to a thermometer encoded value of the binary encoded setting value.

Abstract: A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller.

Abstract: A circuit for skewing differential signals includes a coarse adjustment stage configured to receive a differential input signal having a true component and a complement component, the coarse adjustment stage configured to impart a first controllable delay to at least one of the true component and the complement component of the differential signal, and a fine adjustment stage configured to impart a second controllable delay to at least one of the true component and the complement component of the differential signal, the second controllable delay having a resolution different than a resolution of the first controllable delay, the first controllable delay and the second controllable delay providing a timing skew between the true component and the complement component of the differential signal.

Abstract: A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

Abstract: Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths.

Abstract: A digital delay interpolator may include an array of multiplexers, each multiplexer configured to be input with first and second input voltages, one of the first and second input voltages being delayed in respect to the other, and receive a respective selection signal. The digital delay interpolator may include output lines respectively coupled to the array of multiplexers, and an output terminal configured to be coupled in common to the output lines. Each multiplexer may be configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.

Abstract: A digitally controlled delay device includes at least one delay generating gate device, whose propagation delay is controlled by limiting operating current by means of a tail transistor that is controlled by its gate voltage, a gate control voltage control means for controlling the current limiting transistor gate voltage, and a bank of digitally controlled MOSFET transistors in parallel configuration, and the digital control is adapted to switch the transistors to off and to diode mode connection, current feeding means to feed current through the bank of MOSFET transistors, and the voltage over the bank of parallel transistors is used for gate source control voltage of the tail transistors.

Abstract: A selected-parameter adaptively switched power conversion system, for example, includes a counter for determining a period of an output oscillation a power supply switch, where the output oscillation starts when an output current generated by stored power of the power supply coil decays substantially to zero. An event generator for generating a switching delay event in response to the determined output oscillation period and generates a switching delay event in response to a determination of a phase of the output oscillation.

Abstract: In an approach for calibrating a delay line having a plurality of taps, a first clock signal is input to the delay line. A second clock signal is input to a reference circuit having a plurality of taps. In response to determining that output signals of selected taps of the delay line and reference circuit do not align, a next tap of the reference circuit is selected, to determine whether or not the output signals align. In response to determining that the output signals align, reference tap data indicative of the current reference tap is stored in association with a delay tap number of the current delay tap. A next tap of the delay line is selected to determine whether or not the output signals align.

Abstract: A multi-stage phase mixer circuit includes: a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to control of a first coarse control signal; a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to control of a second coarse control signal; and a third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to control of a fine control signal.

Abstract: There is provided a clock generating apparatus for generating a recovered clock by recovering a clock from an edge of a received signal, including a recovered clock generating section that generates the recovered clock, a multi-strobe generating section that generates a plurality of strobes with different phases, in accordance with a pulse of the recovered clock, a detecting section that detects a position of an edge of the received signal relative to the strobes, by referring to values of the received signal obtained at respective timings of the strobes, and an adjusting section that adjusts a phase of the recovered clock, in accordance with the position of the edge of the received signal.

Abstract: Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.

Abstract: Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control variation of the delay time of the delayer. In various embodiments, current generators can be arranged to provide reference voltages to each inverter stage of an inverter chain. Additional apparatus, systems, and methods are disclosed.

Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.

Abstract: A semiconductor device includes a plurality of driving units configured to drive an output node based on an input signal and be on/off controlled based on driving force control codes, respectively, a slew rate control signal generation block configured to generate a slew rate control signal based on the driving force control codes, and a plurality of signal delay units configured to delay the input signal by respectively different delay amounts, transfer resultant signals to the plurality of driving units, and be respectively controlled in their delay amounts based on the slew rate control signal.

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Abstract: Techniques and mechanisms for operating an integrated circuit to communicate via a hardware interface for the integrated circuit, wherein a pinout with the hardware interface is based on the configuration. In an embodiment, the integrated circuit receives a first plurality of signals via the hardware interface, and sequentially latches a second plurality of signals based on the first plurality of signals. In another embodiment, some or all of the second plurality of signals are variously latched by the integrated circuit in an order which is based on the first configuration.

Abstract: A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop comprises a filter unit to provide filtering of noise on a phase control signal to substantially reduce a false delay lock loop state.

Abstract: A link-path delay estimator estimates a signal-path delay of a signal path between a master device and a remote device, by combining coarse delay estimates and a fine delay estimate. The coarse delay estimates indicate only an integral portion of the signal-path delay, selected as an integral multiple of a symbol period. The fine delay estimate indicates only a fractional portion of the signal-path delay, selected from a range of values that extends over one symbol period. The link-path delay estimator can combine the coarse and fine delay estimates using a first rule if the two most recent coarse delay estimates are equal, and a second rule if the two most recent coarse delay estimates differ. The coarse delay estimates can arise from both rising edges and falling edges of periodic signals sent along the signal path.

Abstract: An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.

Abstract: Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.

Abstract: Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.

Abstract: Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.

Abstract: Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.

Abstract: A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for generating a reference clock signal and delaying a received clock signal based on the reference clock signal. In one implementation, a circuit includes a control block configured to generate a control signal. The circuit includes an oscillator configured to generate a reference clock signal. The oscillator includes a plurality of delay elements each configured to receive the control signal and to introduce a delay in the reference clock signal based on the control signal. The delay elements of the oscillator are arranged to generate the reference clock signal. The circuit further includes a delay block configured to receive a clock signal and to generate a delayed clock signal. The delay block includes one or more delay elements each configured to receive the control signal and to introduce a delay in the clock signal based on the control signal.

Abstract: The invention relates to a control circuit (250) for a power supply unit (200) that has an input (207, 209) for receiving a mains supply (208), the control circuit (250) configured to: sample the input (207, 209) in order to obtain a first sample value; sample the input (207, 209) in order to obtain a second sample value subsequent to obtaining the first sample value; compare the first and second sample values to provide an outcome; set a delay interval in accordance with the outcome of the comparison of the first and second sample values; and sample the input (207, 209) in order to obtain a third sample value after the delay interval has elapsed.

Abstract: A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.

Abstract: Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.

Abstract: A local oscillator signal generation circuit is presented. The circuit comprises: a delay device adapted to delay a data signal according to a control signal; a data flip-flop having the delayed data signal provided to its data input terminal and a reference clocking signal provided to its clock input terminal; and a control circuit adapted to generate first and second partially overlapping pulse windows from the delayed data signal and to generate a control signal based on the first and second partially overlapping pulse windows and the reference clocking signal. The control signal is provided to the delay device to control the amount by which the data signal is delayed so as to align the rising edges of the data signal and the reference clock signal. A local oscillator signal is derived from the output of the data flip-flop.

Abstract: A delay circuit includes a delay unit configured to generate a delayed transmission signal by delaying a transmission signal activated when a first signal or a second signal is activated, a signal type storing unit configured to store whether the first signal and the second signal is activated, and a transmitting unit configured to transmits the delayed transmission signal as a first delayed signal or a second delayed signal in response to a value stored in the signal type storing unit.

Abstract: Method, modules and a system formed by connecting the modules for controlling payloads. An activation signal is propagated in the system from one module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to an external power source such as AC power.