Abstract: A delay circuit is provided including first and second resistive elements electrically coupled in series having first and second resistance values. The first resistance value varies in proportion to temperature and the second resistance value varies in inverse proportion to temperature.

Abstract: A low voltage, low power versatile and compact delay circuit for CMOS integrated circuits. The biasing circuit and comparator of the delay circuit are implemented with a relatively few simple transistor stages. This approach makes the circuit compact and allows for operation at very low supply voltages (e.g., 1.5 volts). The time delay of the delay circuit is made to depend only on passive resistive and capacitive components. The time delay is thus insensitive to fluctuations in the supply voltage, as well as fluctuations in temperature. This configuration is particularly advantageous in circuits where several timing elements need to track with one another, as they can all be formed with resistors and capacitors of the same construction. The design also makes the circuit insensitive to process parameters, as well as later environmental effects due to operating temperature, circuit aging, and the like.

Abstract: The back bias voltage on a functional circuit is controlled through a closed loop process. A delay element receives a clock pulse and produces a delay output. The delay element is advantageously constructed of the same materials as the functional circuit so that the aging and degradation of the delay element parallels the degradation of the functional circuit. As the delay element degrades, the transistor switching time increases, increasing the time delay of the delay output. An AND gate compares a clock pulse to an output pulse of the delay element, the AND output forming a control pulse. A duty cycle of the control pulse is determined by the delay time between the clock pulse and the delay element output. The control pulse is received at the input of a charge pump. The charge pump produces a back bias voltage which is then applied to the delay element and to the functional circuit.

Abstract: A semiconductor integrated circuit comprising a voltage controlled delay cell including a first voltage controlled resistor and a current source transistor of a MOS type differential amplifier circuit, the first voltage controlled resistor functioning as a load resistor, wherein a resistance value of the first voltage controlled resistor is controlled according to a first bias voltage, and a current of the current source transistor is controlled according to a second bias voltage, and a bias circuit including a first replica circuit and a second replica circuit, the first replica circuit having a structure equivalent to that of the voltage controlled delay cell, the second replica circuit having a structure equivalent to a structure in which the first voltage controlled resistor is replaced by a constant resistor, the bias circuit configured to generate and supply the first bias voltage and the second bias voltage to the voltage controlled delay cell.

Abstract: A generator includes an oscillator for producing a clock signal from N logic signals representing an N-bit control number, with N being an integer greater than 1. The oscillator has N+1 components. The N most significant components are each assigned a place value i ranging from 1 to N, and a least significant component provides the clock signal. At least one component with a place value i greater than 1 includes first and second arms. The first arm includes a cell and a first switch connected in series, and the second arm includes 1+21 cells and a second switch connected in series. Each cell includes an odd number of inverters.

Abstract: According to one aspect of the invention, a method is provided in which an input signal is received at a first node of a buffer circuit. The propagation of the input signal from the first node to a second node in the buffer circuit is delayed by a delay period based upon a first control input. The delay period is adjusted by a factor based upon a second control input.

Abstract: A voltage controlled oscillator includes an oscillation controller, first and second current sources, oscillation section, and first and second fluctuation transmitters. The oscillation controller generates first and second control potentials. The first and second current sources generate control currents corresponding to the first and second control potentials, respectively. The oscillation section is connected to a power source potential node via the first current source and connected to a ground potential node via the second current source, and generates a clock. The first fluctuation transmitter is disposed between the power source potential node and the first control potential node, and transmits a potential fluctuation in the power source potential node to the first control potential node.

Abstract: According to one aspect of the invention, a method is provided in which an input signal is received at a first node of a buffer circuit. The propagation of the input signal from the first node to a second node in the buffer circuit is delayed by a delay period based upon a first control input. The delay period is adjusted by a factor based upon a second control input.

Abstract: A digital phase interpolator including a plurality of delay stages to control delay time of an output signal from first and second input signals having different phase delays. The plurality of delay stages are connected serially, have a same internal structure, determine corresponding axes for interpolation in each stage, and each includes a first inverting section for inverting first and second signal inputs from the previous stage, a phase blender for blending outputs of the first inverting section, a second inverting section for inverting outputs of the first inverting section, and a multiplexer for generating input signals for the next stage in response to a selection signal for determining phase delay time of the output signal of the phase interpolator. Total area and current may be reduced by the present invention because the number of inverters comprising each stage is equal.

Abstract: A two-stage ring oscillator system that provides a phase shift of 90° in each of the two stages. Each stage includes an LC-based stage including a voltage controlled oscillator (VCO) and an in-line signal buffer that provides an additional controllable phase shift in the forward path and reduces loading capacitance of each LC-based stage by an estimated 10-50 percent. In-phase and quadrature output signals are provided by the system.

Abstract: A voltage controlled delay circuit comprising n-type inverter delay circuits comprised of n-type inverters each having a PMOS transistor, as a load, with a source connected to a power supply node and with a gate to which a delay time amount control voltage is applied and having an NMOS transistor for driving, an NMOS transistor for bias with a drain-source pass connected between a ground node and a node at which sources of NMOS transistors of the inverter delay circuits each as a stage are commonly connected and with a gate to which a bias voltage to set to be “ON” is applied, and a push-pull inverter circuit which inputs a signal of which the amplitude changes over the entire amplitude in a range of power supply voltage to a first-stage delay circuit.

Abstract: A delay stage used in a ring-type voltage-controlled oscillator has an inverter, a memory element, and tuning circuitry. The memory element is coupled to the output of the inverter to delay the time before the inverter's output begins to switch states in response to the inverter's input switching states. The tuning circuitry receives a control voltage and is coupled to the inverter to alter the strength of the inverter without altering the strength of the memory element. Altering the strength of the tuning circuitry alters the delay of the delay stage, and hence the frequency of the VCO's operation. Because the strength of the memory element is not altered, the speed at which the inverter's output switches remains substantially constant at all tuned frequencies. The switching speed is primarily dictated by the FT of the process.

Abstract: A variable delay circuit includes a ramp voltage generating unit having a storage capacitor, a charging transistor for charging the capacitor and a constant-current source for discharging the capacitor, and a comparator for comparing the output of the ramp voltage generating circuit against a voltage setting to output a delayed signal. The electric charge flowing out from the output node of the ramp voltage generating unit through the charging transistor during generating the ramp voltage is compensated by a compensating capacitor to output a linear ramp voltage.

Abstract: MOS devices are added respectively to each stage of the voltage-controlled oscillator in a phase-locked loop circuit for improving the operating frequency range and the stability of middle/low frequency thereof, and for continuously and accurately adjusting the frequency.

Abstract: A method for dynamically selecting an input threshold on an input pin comprising the steps of (A) generating one or more control signals from a user selectable register and (B) selecting the input threshold from a plurality of thresholds in response to at least one of the control signals.

Abstract: A CMOS logic circuit is supplied with a power supply potential via current control gate transistors, and has current flowing towards ground via current control transistors. The gate potential of each current control transistor is controlled by a current control circuit. When leakage current is generated in the CMOS logic circuit, self bias to suppress leakage current is generated in the transistor forming a logic gate due to a voltage drop by the current control transistor.

Abstract: A method of adjusting a circuit operating characteristic. The method includes generating a first signal for application to a reference termination. The method then includes generating a first voltage based on the first signal at a first point on the reference termination and generating a second voltage based on the first signal at a second point on the reference termination. The method also includes adjusting an operating characteristic based upon the first voltage and the second voltage. In an embodiment, the operating characteristic can be an impedance.

Abstract: A voltage-controlled CMOS delay cell includes a pair of inverters and a pair of load cells. The load cells are controllable by independent N and P bias control voltages to vary the delay of the delay cell. Symmetric P and N load capacitors in the delay cells, together with the N and P bias control voltages, provide effective rejection of noise on the power supply rails and enable the delay cell to generate symmetric low-going and high-going delays. The P bias control voltage is generated from the N bias control voltage by a closed-loop voltage control circuit. Also described are a voltage-controlled load cell, an integrated circuit, an electronic system, and a data processing system that incorporate one or more of the symmetric CMOS voltage-controlled delay cells.

Abstract: A circuit for improving the performance of a charging capacitor inverter used in VCO and similar circuits. The disclosed approach is used to provide both trip point and charging current delay control to reduce the amount of “jitter” associated with the circuit. Trip point delay control is accomplished by adding an in-line transistor, output in a typical charged capacitor inverter, between the charging capacitor and the circuit. The threshold of this transistor is controlled by a dc bias level (control voltage) which allows this transistor to turn “ON” or “OFF” when the node voltage of the capacitor reaches the controllable preset level. Further control of the circuit's delay is obtained by means of circuitry which allows the amount of capacitor charging current to be selected.

Abstract: A duty ratio correction circuit includes a pair of circuit blocks each having an input stage inverter for receiving one of complementary clock signals, a first waveform correction circuit for receiving an output from a corresponding one of the input stage inverter, and a second waveform correction circuit for receiving the other of the complementary signals. Each of the waveform correction circuits has a lower output impedance at an initial stage of signal transition of the input signal and a higher output impedance at a subsequent stage of the signal transition.

Abstract: There is provided a semiconductor integrated circuit including a clock buffer capable of suppressing the increase of its chip size and decreasing its electric power consumption even if the capacity increases or even if the functional operations are varied.

Abstract: In an high-frequency LSI chip, a clock signal generating circuit establishes accurate synchronization between an input clock signal and an internal clock signal to prevent an input circuit from causing a synchronization shift. The clock signal generating circuit includes an input circuit for amplifying an input signal and outputting an amplified signal as a first internal signal; a variable delay circuit, on the basis of a control signal, for delaying the first internal signal and outputting a delayed signal as a second internal signal; a phase comparator for finding a phase difference between the input signal and second internal signal and outputting a phase difference signal indicative of the phase difference; and a control circuit for generating the control signal on the basis of the phase difference signal. Thus, the influences of a delay caused by the input circuit, which would not be avoided in the prior art, can be avoided and the accurate internal clock signal can be generated.

Abstract: The present invention provides a power model for a semiconductor integrated circuit, wherein the power model comprises a logic gate circuit part representing an operating part of the semiconductor integrated circuit and an equivalent internal capacitive part representing a non-operating part of the semiconductor integrated circuit.

Abstract: The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

Abstract: Integrated circuit output buffers include an integrated circuit substrate, an output buffer in the substrate which drives a respective load, an supplemental voltage supply pad on the substrate, a first switch and at least one external capacitor which is electrically coupled to the supplemental voltage supply pad. The first switch is electrically coupled in series between an output of the output buffer and the supplemental voltage supply pad. During operation, the first switch is closed to facilitate the forward transfer of stored charge from the at least one external capacitor (e.g., 1 &mgr;F) to a capacitive load (e.g., 100 pF) during a first portion of a pull-up time interval. The output buffer is then turned on to complete the pull-up operation. Next, the transferred charge is recycled back from the load into the external capacitor by closing the first switch again during a first portion of a pull-down time interval. The output buffer is then turned on to complete the pull-down operation.

Abstract: A variable delay section comprises a gate element and a plurality of (N) delay elements for delaying the signal change on the output of the gate element. A difference between a first delay provided by n-th delay section and a second delay provided by (n+1)th delay section is constant for any of n's between 1 and N−1. A plurality of variable delay sections are cascaded to form a frequency multiplier, with the output of the last stage variable delay section being fed-back to the input of the first stage variable delay section through a selector. The other input of the selector is connected to the input of the variable delay circuit to allow the internal signal to pass the variable delay sections for K times.

Abstract: A digital delay generator device is based on a series arrangement of cells, wherein each cell has a first input for receiving a single-phase clock signal, a second input for receiving a delayable signal for thereto imparting a cell delay, and an output for a so-delayed signal. Each cell comprising a series stack of transistors, and various cells comprise further transistor means for receiving a bypass control signal. Such further transistor means are arranged for under control of a bypass control signal effectively bypassing one or more cells to thereby effect a quantized overall delay shortening. In particular, such various cells form a contiguous pair in said string, and the transistor means effectively form respective transistor bypasses over clock-signal-controlled transistors in the associated series stack at mutually opposite sides of their respective stack.

Abstract: There is provided a semiconductor integrated circuit including a clock buffer capable of suppressing the increase of its chip size and decreasing its electric power consumption even if the capacity increases or even if the functional operations are varied.

Abstract: A circuit and method configured to generate a variable impedance. The circuit may comprise a voltage controlled resistor configured to generate the variable impedance in response to (i) a first transistor configured to receive a first control signal and (ii) a bias transistor configured to receive a bias signal. In one example, the variable impedance may be generated in further response to a clamp transistor.

Abstract: The invention is to provide a programmable delay element that can produce a variable delay with many different delay combinations. The invention creates a variable delay through logic gates. A plurality of transmission gates are used to transfer a signal through a plurality of fixed delay lines. Four parallel coupled signal paths, each path having a fixed delay, form the basis of the invention. By selecting a path or by serially adding successive paths, the desired delay of the signal present on the delay line can be achieved.

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract: A transistor output circuit generates an output signal having a voltage greater than a breakdown voltage of the transistors used to construct the output circuit. The output circuit includes an NMOS transistor and a PMOS transistor that are connected in series and have their gates connected to each other. A potential control circuit is also connected to the gates and the sources of the NMOS and PMOS transistors. The potential control circuit receives power from a high potential power supply and a low potential power supply. The potential control circuit applies a reference voltage, which has a voltage value between the voltages generated by the high and low potential power supplies, to the gates of the transistors. Then, in response to an input signal, the potential control circuit controls the voltages applied to the sources of the transistors. The output circuit may be connected to a level converter circuit, an op amp circuit, and other logic circuits.

Abstract: An input-output (I-O) buffer for an I-O node of an integrated circuit. The buffer includes a group of transistors to pull the node up. A shift register has each of two or more of its storage cells coupled to a gate of each of the transistors to control the impedance of the buffer.

Abstract: A delay cell for use within a voltage controlled oscillator capable of operating at two different selectable frequencies, the delay cell having a first delay stage including a first differential pair of transistors, wherein the emitter or each transistor is coupled to a first common node and further wherein a first current exiting the first common node is selectively variable. The delay cell further having a second delay stage including a second differential pair of transistors, each having an emitter coupled to a second common node wherein a second current exiting the second common node is selectively variable and wherein a sum of the first current and the second current is substantially constant. The amount of delay associated with the first delay stage is dependent upon the level of the first current.

Abstract: In one embodiment, a multistage output buffer supplies current to a load by successively turning ON output buffer circuits which transition from an OFF state to approximately a saturated state during approximately mutually exclusive periods of time. Thus, the aggregate dI/dt of the contributed by the output buffer drivers is primarily associated with a single output buffer driver. Additionally, the respective output driver transition periods are controlled by delay stage impedance to reduce dI/dt. The consecutive activation of the output buffer drivers may be achieved by using respective delay stages to control activation of associated, respective output buffer drivers. Each delay stage receives a delayed output control signal from a previous delay stage, except for the first delay stage which receives a control input signal from a signal source. Each delay stage also delays activation of its own output control signal with delay circuit elements such as relatively HIGH impedance IGFETs.

Abstract: In a CMOS noise eliminating circuit, a plurality of PMOS transistors or NMOS transistors are connected in series so as to cause of switching speeds or switching timings of the PMOS transistors or the NMOS transistors, which are connected in series, to differ from each other, thereby improving the noise-resistant performance of a semiconductor integrated circuit.

Abstract: Circuits such as Phase Lock Loops which use VCO's are affected by temperature and power supply variations which effect the performance of the circuit, particularly at high frequencies and low supply voltages. The present invention provides a variable delay circuit stage comprising one or more delay stages and an analogue multiplexer arranged to control the amount of delay introduced by the delay stages; a supply voltage pushing compensation circuit stage comprising a transconductance stage connected to the multiplexer and arranged to produce a compensating current upon deviation from nominal supply voltage which changes said delay; and a temperature pushing compensation circuit stage comprising a transconductance stage connected to the multiplexer and arranged to produce a compensating current upon deviation from nominal temperature which changes said delay.

Abstract: Disclosed is a delay circuit for delaying at least the timing of a rising edge or the timing of a falling edge of an input signal alternating between first and second levels. The delay circuit includes (1) a charge pump in which first and second field-effect transistors of different channels are serially connected; (2) a capacitor connected in parallel with the first field-effect transistor; (3) a charging current control circuit for passing a charging current into the capacitor via the second field-effect transistor of the charge pump when the input signal is at the first level; (4) a discharge current control circuit for releasing a discharge current from the capacitor via the first field-effect transistor when the input signal is at the second level; and (5) a discrimination circuit for outputting a signal of a prescribed logic level based upon a terminal voltage of the capacitor.

Abstract: A variable delay circuit includes a load on a signal transfer line, at least one transistor connected to the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.

Abstract: To generate a signal delay, a current source, a reference voltage generator and a comparator are turned on. Once turned on, the current source raises the voltage across an initially discharged capacitor to a minimum required threshold. The comparator then compares the capacitor voltage to the reference voltage thereby to generate the delay signal. Thereafter, the current source, the reference voltage generator and substantial blocks of circuitry in the comparator are switched off to reduce quiescent power consumption.

Abstract: A ring-type signal controlled oscillator comprising a series of active delay elements, each including a respective differential pair of transistors. The inputs and outputs of the differential pair transistors are interconnected in a closed ring to produce oscillations at a frequency determined by the delay of each delay element. The differential pair of transistors further has a pair of current source inputs for controlling an amount of delay of the delay element, and a pair of load inputs for stabilizing the amount of delay. The invention advantageously provides high frequency operation with substantially symmetric rise and fall time, while limiting spread in oscillation frequency and spread in amplitude in relation to fabrication process variability and power supply variability.

Abstract: Of the MOSFETs used to implement an oscillator circuit or a delay circuit in a semiconductor device, minimally the MOSFETs P12 (N12) used in a part of the circuit that affects the oscillation period or delay time are low-threshold-voltage type MOSFETs.

Abstract: An apparatus that includes a driver circuit and an active load circuit coupled to an output of the driver circuit. The active load circuit is configured to actively adjust the slew rate of a signal outputted by the driver circuit.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: An output buffer circuit capable of controlling a through rate at a constant rate. Each decision circuit of a plurality of decision circuits (11-13, 18-20) receives a voltage potential from an output terminal (10) and compares it with a respective predetermined voltage value. Flip flops (15-17) with an asynchronous set function or flip flops (22-24) with an asynchronous reset function receive respective comparison results as decision results when receiving a respective trigger signal from a respective delay circuit from a plurality of delay circuits (14, 21) after the elapse of a respective predetermined time period from a time at which an input terminal (1) receives a H level control signal or an L level control signal. The flip flops (15-17 and 22-24) control the operation of output transistors (3-5 and 7-9) based on the respective decision results.

Abstract: A delay circuit includes a reference voltage generation circuit for generating a reference voltage which changes to a prescribed voltage level during the operation of a comparison circuit, an RC delay stage for integrating an input signal, a comparison circuit for comparing an output signal from the RC delay stage and the reference voltage of the reference voltage generation circuit, and a logic circuit for buffering the output signal of the comparison circuit. Since the reference voltage is pulled to a prescribed voltage level only during a comparison operation, the reference voltage may accurately be maintained at the prescribed voltage level only when necessary free from the influence of other circuits and noises. A delay circuit with reduced current consumption which is capable of changing an output signal with fixed delay time independently of the influence of fluctuations of the power supply voltage and the input logical threshold value of a logic circuit in a succeeding stage is provided.

Abstract: A high resolution variable time delay circuit is disclosed. In one embodiment, a current digital to analog converter (DAC) is used to sequentially charge two capacitors having similar capacitance construction. A threshold level capacitor provides the threshold level to a comparator, and a ramping capacitor is used for ramping to the threshold to provide a delay time. The comparator provides a delayed pulse using the threshold level provided by the threshold level capacitor and the ramp provided by the ramping capacitor. Thus, resolution is better than that provided by digital elements alone. This circuit also automatically cancels errors due to capacitance variations and unit current variation of the DAC introduced during the manufacturing process. In another embodiment a single capacitor is used in combination with two current DACs and a comparator to provide a controllable time delay.

Abstract: A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.

Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.

Abstract: A variable frequency ring oscillator is controlled by a control signal and has an odd number of cascaded inverting gates. The inverting gates each have input terminals receiving an input signal. Except for the first of the cascaded inverting gates, each input signal on a gate is the output from the preceding inverting gate. The input terminal of the first of the inverting gates receives the output of the last of the inverting gates. At least one inverting gate is a cell having a gain variable as a function of a control signal. An output signal ext of the circuit is an inversion of an input signal inp and has a hysteresis that is a function of a control signal cont. The term “hysteresis” as used herein signifies, for example, a variable frequency signal remaining substantially in its current state for a certain length of time after which the variable frequency signal changes state with a magnitude that is a function of a control signal, upon change of state of an input signal.