Abstract: An adjustable delay circuit for digital signals includes a series circuit which is disposed between two supply potentials and has at least a first transistor of a first conduction type and second and third transistors of a second conduction type. Control connections of the first and second transistors are connected to a signal input of the delay circuit. One connection of the first transistor, which is remote from the first supply potential, is connected to a signal output. A fourth transistor of the second conduction type is connected in parallel with the third transistor. A first control input is connected to a control connection of the third transistor and a second control input is connected to a control connection of the fourth transistor. The control inputs are used to adjust the delay time of the delay circuit.

Abstract: A time delay generator (20) includes a threshold generator (30), a ramp generator (32) and a comparator (34). The threshold generator provides a fixed threshold at one input of the comparator while the ramp generator provides at the other input a ramp signal whose slope is programmable. The ramp generator includes current switches (86 and 90) and a current converter (74). In response to input and range signals, the current switches provide a programmed input current and a programmed range current. The current converter generates a ramp current that is proportional to the range current and inversely proportional to the input current and couples that ramp current to an integrating ramp capacitor. The structure of the time delay generator facilitates noise filtering of the threshold signal and positioning of the threshold signal away from ramp nonlinearities.

Abstract: A voltage controlled oscillator which causes little interference to and receives little interference from other circuits via a parasitic capacitance of an integrated capacitor, has a good control linearity, and is capable of being used over a wide range of frequency including ultra high frequencies, constituting a ring oscillator by being provided with three or more logic buffer circuits having differential input and output terminals cascade connected at the differential inputs and outputs and making the n-th differential output a negative feedback to the terminal of the 1st differential input. Each of the logic buffer circuits comprises a differential transistor pair comprised of first and second transistors, first and second diode array each comprising at least one diode, first and second integrated capacitors, and a current source for frequency control. The sum of emitter currents of the pair of the differential transistors is set by the current source for frequency control.

Abstract: A delay circuit which is capable of maintaining a constant delay time. The circuit includes a plurality of first delay circuits connected in series and each having an inverter for inverting an input voltage signal, and a variable capacitor connected to an output terminal of the inverter.

Abstract: A programmable delay line has delay elements that are responsive to at least one of two different calibration signals for varying their drive power characteristics and hence the delay period. Preferably, there are two sets of delay elements, responsive to a respective calibration signal, with one set comprising much fewer delay elements than the other set. The delay elements may be responsive to a digital calibration signal for discrete control, an analog calibration signal for continuous control, or both.

Abstract: A voltage controlled oscillator (VCO), for use in a phase locked loop for clock multiplication, for example in recovery of data pulses from a data stream input comprising digital data with unknown phase. According to the invention, the VCO comprises a plurality of VCO stages, each stage being implemented as a differential amplifier. The amplifier load is formed of two cross-coupled gate devices and of two gate devices which are connected as diodes. The differential input is applied to a source coupled input pair as well as to two pull-down gate devices.

Abstract: An integrated circuit complementary metal-oxide silicon (CMOS) voltage controlled oscillator (VCO) includes a plurality of variable delay elements, connected in a ring configuration, each variable delay element including a pair of parallel connected differential CMOS sections. The parallel-connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element. These relative levels of operation determine the delay through the variable delay element. A current mirror circuit provides the differential control voltage.

Abstract: A single-gate SCFL delay cell is disclosed for implementation in a common ring oscillator VCO. The delay cell has a differential input stage the output current from which is fixed by two resistors. The differential input stage drives a source follower output stage providing an output capable of driving the differential input of the next stage of the oscillator. The current sources typically used in the source follower output stage have been replaced by voltage-to-current converters. The voltage-to-current converters are comprised of two MESFET devices the gates of which are coupled to a differential control voltage. The source of each of the two devices is coupled to a current source the value of the two current sources being equal. The resistor couples the two sources together such that the voltage drop across the resistor governs how much current is conducted by each of the two devices.

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract: A voltage controlled oscillator is implemented by odd inverters forming a loop, and a depletion type load transistor, a depletion type frequency control transistor and a depletion type compensating transistor supply driving current to an enhancement type driving transistor in each inverter; the compensating transistor is controlled by a reference voltage generator implemented by a series of resistor and a depletion type load transistor, and fluctuation in a fabrication process equally affects the depletion type transistors; when the depletion transistors increases the driving current, the resistor decreases the reference voltage supplied to the gate electrode of the depletion type compensating transistor, and the depletion type compensating transistor cancels the increment of the driving current so as to make the voltage controlled oscillator less sensitive to the fluctuation of the threshold.

Abstract: A voltage-controlled oscillator (VCO) generates an oscillating signal that is substantially resistant to noise fluctuations in the supply voltage. The VCO is a delay-based VCO which preferably includes a compensation circuit for each delay cell and a noise-immune reference current generator for providing a noise-immune bias current to the conditioning circuit of the VCO. The compensation circuit preferably adjusts the capacitance of the delay cell to compensate for the variations in current caused by the supply noise. The noise-immune reference current generator preferably utilizes a configuration of transistors which maintains through at least one transistor a substantially constant current which is used to bias the conditioning circuit.

Abstract: A variable frequency ring oscillator is controlled by a control signal and has an odd number of cascaded inverting gates. The inverting gates each have input terminals receiving an input signal. Except for the first of the cascaded inverting gates, each input signal on a gate is the output from the preceding inverting gate. The input terminal of the first of the inverting gates receives the output of the last of the inverting gates. At least one inverting gate is a cell having a gain variable as a function of a control signal. An output signal ext of the circuit is an inversion of an input signal inp and has a hysteresis that is a function of a control signal cont. The term "hysteresis" as used herein signifies, for example, a variable frequency signal remaining substantially in its current state for a certain length of time after which the variable frequency signal changes state with a magnitude that is a function of a control signal, upon change of state of an input signal.

Abstract: A variable delay circuit for controlling delay time includes P channel transistors connected in parallel, with respective source electrodes connected to a power supply, respective drain electrodes connected to an output terminal for providing delayed signal, and respective gate electrodes connected to respective control signal input terminals for receiving control signals. The circuit further includes N channel transistors with respective source electrodes connected to ground, respective drain electrodes connected to the output terminal, and respective gate electrode connected to the respective control signal input terminals. Identical or mutually inverted data signals or control signals are supplied to the respective gate electrodes of the P channel transistors and the respective gate electrodes of the N channel transistors.

Abstract: A ring oscillator includes a plurality of inverting delay elements connected in a ring. Each inverting delay element includes an inverter having an output node. The oscillator also includes a programmable current circuit operable to rob a variable amount of current from the output node of the inverter to control the duration of a delay period associated with the delay element.

Abstract: The present invention provides a novel circuitry comprising a series connection of a plurality of invertor gates, each of which has field effect transistors, wherein at least one of the field effect transistors has a back bias control terminal; and a various bias voltage generator being capable of generating at least one bias voltage and also capable of varying the at least one bias voltage individually, the various bias voltage generator being also electrically connected to the back bias control terminal of the at least one of the field effect transistors for applying the at least one bias voltage to the back bias control terminal so that the various bias voltage generator is operated to individually vary the at least one bias voltage thereby to individually vary a threshold voltage of the at least one of the field effect transistors.

Abstract: A programmable delay line. The programmable delay line includes a series of delay cells which are programmably connected in series. The programmable delay line includes a main delay chain and auxiliary delay chains. The main delay chain includes unit delay cells. The auxiliary delay chains include a unit delay cell, and a delay cell which has a delay that is between one and two time greater than the delay through a unit delay cell. The delay resolution of the programmable delay line is less than the delay of a unit delay cell. The programmable delay line further includes a reference oscillator and calibration circuitry. The reference oscillator includes a series of unit delay cells, and generates a reference signal having a period which is an integer multiple of the delay of a unit delay cell. Variations in the delay of a unit delay cell influence the period of the reference signal.

Abstract: Two voltage controlled resistance elements are coupled together in parallel. The first voltage controlled resistance element is coupled to a first voltage input, a voltage source, and an output. The second voltage controlled resistance element is coupled to a second voltage input, the voltage source, the first voltage controlled resistance element, and the output. The parallel resistance elements provide a variable resistance based on the resistance values of the first and second voltage controlled resistance elements.

Abstract: A slew rate control circuit for an output circuit of an integrated circuit includes an input node for obtaining an input signal and an output node for providing an output signal. A first stage of the control circuit includes at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor are connected together to the input node. The first main terminal of each at least one transistor are connected to a voltage rail. The second main terminal of each at least one transistor is connected to the output node through its own individual resistor. One or more subsequent stages of the control circuit each contain at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor in each one or more subsequent stages of the control circuit are connected together to a control node driven from the control terminals of the preceding stage through at least one inverter.

Abstract: A variable delay circuit that delays an input signal for a desired time and outputs the delayed signal includes N (N is an integer of 2 or more) load transistors and N control transistors for controlling the load transistors respectively connected in pairs in series to form N load transistor pairs. The load transistor pairs are connected in parallel to form a load transistor group. A switching transistor that is turned on or off according to an input signal input to a gate, and the load transistor group are connected in series between first and second power supplies. The input signal is delayed according to control signals that are respectively input to the control transistors, and a delayed signal is output from a connection node of the load transistor group and the switching transistor. Since no selector is required, a delay circuit operation due to differences in delay times between paths in a selector is avoided, thereby obtaining a variable delay circuit having minute resolution and a good yield.

Abstract: A variable delay circuit for arbitrarily change of a signal delay helps easily attain a desired resolution with a high precision, which has been difficult due to device process dependence of a voltage control circuit applying a voltage to a CMOS circuit. A variable voltage controller is provided between a power source and a CMOS circuit propagating a signal such that a delay time of signal propagation is supervised by controlling the voltage at a connecting point in the variable voltage controller. The controller includes two MOS transistors and an npn transistor, which solves the process dependence and hence leads to a low power consumption and a high resolution.

Abstract: A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: A delay circuit comprising at least one capacitor with one electrode thereof is connected to a fixed potential, a signal transmission line, and at least one switch means between the other electrode of the capacitor and the signal transmission line. The switch means makes electrical connection or disconnection between the capacitor and the signal transmission line in accordance with an actual supply voltage value.

Abstract: A control transistor is connected in parallel with an input transistor of a bias generation circuit in a voltage control delay circuit. A power supply potential Vcc is divided by voltage divider resistors to be applied to the gate of the control transistor. Reduction in the power supply potential Vcc causes reduction in a current Ib flowing to the control transistor, and a current Ic=Ia+Ib flowing to a delay time variable element. When the power supply potential Vcc is reduced, the factor of a delay time period of delay time variable elements becoming shorter due to a smaller amplitude of a clock signal is canceled with the factor of the delay time period of the delay time variable elements become longer due to a smaller current Ic flowing thereto. Therefore, variation in the delay time period can be suppressed to a low level.

Abstract: A precision delay circuit in an integrated circuit chip includes a transistor switching circuit in combination with a control circuit and a compensation circuit. The transistor switching circuit receives an input signal; and in response, the transistors switch on and off at an unpredictable speed to generate an output signal with a delay that has a large tolerance. The control circuit estimates the unpredictable speed at which the transistors switch and it generates control signals that identify the estimated speed. The compensation circuit includes a plurality of compensation components for the transistor switching circuit. This compensation circuit receives the control signals from the control circuit; and in response, it selectively couples the compensation components to the transistor switching circuit such that the combination of the transistors and the selectively coupled components generates the output signal with a precise delay that has an insignificant tolerance.

Abstract: A voltage-controlled oscillator includes at least one voltage-controlled delay element and a reference voltage generator. The voltage-controlled delay element has first and second voltage supply inputs, a control voltage input, a signal input and a signal output. The reference voltage generator has a voltage input coupled to the control voltage input and a voltage output coupled to the first voltage supply input.

Abstract: A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof.

Abstract: A CMOS delay cell with feedback circuitry to ensure that the delay cell is operating in saturation mode. A voltage controlled oscillator (VCO) comprising a loop of an odd number of delay cells, where the VCO is operating in a saturation mode. Under normal operation any intermediate node in the VCO will generate an output signal from a delay cell with reduced supply noise. The output signal can be used to generate a PLL clock signal with a lower phase jitter than prior art VCO's operating at low supply potentials.

Abstract: A voltage-controlled delay element utilizes a current-starved inverter configuration with a feedback path that ensures a rapid discharge of the storage node to ground once the desired delay time has elapsed. The circuit comprises a circuit path for charging the storage node (preferably rapidly), a first pull-down path capable of discharging the storage node at a rate determined by the control voltage, a second pull-down path capable of rapidly discharging the storage node, an output inverter, and a feedback connection between the output terminal of the output inverter and the second pull-down path to rapidly discharge the storage node when the output voltage starts rising. The circuit further comprises a means for programmably adjusting the delay in response to logic signals.

Abstract: A VCO includes a ring oscillator formed by connecting a plurality of voltage controlled inverting delay cells together, and a plurality of transistors for providing control voltages to the plurality of voltage controlled inverting delay cells. Preferably, each transistor has a drain connected to a reference voltage, and a source connected to a voltage controlled inverting delay cell paired to that transistor. Consequently, each transistor acts as a source-follower so that it provides a control voltage to its corresponding voltage controlled inverting delay cell which follows a control voltage driving its gate, thereby isolating the control voltage provided to its corresponding voltage controlled inverting delay cell from power supply noise.

Abstract: A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof.

Abstract: A ring oscillator having an odd number of single ended stages, each stage including two transistors connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.

Abstract: Circuitry for switching between a first and second clock signal is provided having a first local clock circuit 202, a first synchronizing circuit 200 connected to said first clock circuit 202, a first delay circuit 206a-d connected to said first synchronizing circuit 200 and said first clock circuit 202, a second delay circuit 206e, 210, connected to said first delay circuit 206a-d and said first clock circuit 202, a first logic circuit 220 connected to said first 206a-d and second 206e, 210 delay circuits and said first synchronizing circuit 200, a second local clock circuit 102, a second synchronizing circuit 100 connected to said second clock circuit 102, a third delay circuit 106, 108, 110, connected to said second synchronizing circuit 100 and said second clock circuit 102, a second logic circuit 104 connected to said second clock circuit 102 and a portion of said third delay circuit 106, 108, 110, a third logic circuit 120 connected to said third delay circuit 106, 108, 110, and said second clock circui

Abstract: A digitally adjustable time delay circuit which is able to precisely and selectively provide fine delay steps increments, which increments can be one nth of the delay time of one CMOS inverter, including means to adjust the total range of the delay and size of each delay step.

Abstract: A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units.

Abstract: A digital circuit for independently controlling the delay of the falling edge and the delay of the rising edge of a digital signal which consist of two serially connected circuits which contain identical synchronous delay lines connected to a logical switch.

Abstract: A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit generates a second supply voltage (constant voltage) on the basis of the first supply voltage, and supplies the constant voltage to this delay circuit, so that a stable constant delay time can be obtained by the delay circuit without being subjected to the influence of fluctuations of the first supply voltage. All the circuit elements are formed on the same semiconductor substrate. Further, it is preferable to construct the constant voltage supply circuit in such a way that the output voltage thereof is programmable.

Abstract: A delay circuit comprises first modified inverter circuits, a first compensating circuit, second modified inverter circuits and second compensating circuit. Each first modified inverter circuit is composed of a CMOS inverter and an additional NMOS transistor. The CMOS inverter has an NMOS and a PMOS transistor connected in complementary connection between a positive power supply and ground. The additional NMOS transistor controls the current from the first modified inverter circuit to the ground. The first compensating circuit is connected to the gate of each additional NMOS transistor to supply an output signal for compensating a change in characteristic of the additional NMOS transistors. Each second modified inverter circuit is composed of a CMOS inverter and an additional PMOS transistor. The additional PMOS transistor controls a current from the second modified inverter circuit to the positive power supply.

Abstract: A semiconductor integrated circuit having a plurality of power source voltages in one chip and which comprises delaying means which accurately implements a predetermined delay time into a signal. An inverter circuit block receives at its input part an output from a NAND gate. An output from the inverter circuit block is coupled to a node of a phase comparing part through a switch. The output from the inverter circuit block is also coupled through another switch to an input part of another inverter circuit block whose output is coupled to the node of the phase comparing part through still another switch. A control signal is set at a L level if the phase comparing part is to operate at a first power source voltage and set at a H level if the phase comparing part is to operate at a second power source voltage which is larger than the first power source voltage.

Abstract: A controlled oscillator comprising a delay chain having a plurality of series coupled delay lines, the output of the delay chain being fed back as an input to each of the delay lines. Each delay line comprising an invertor such that the delay imparted by the invertor is controlled by a voltage controlled resistance means. The length of the delay chain is controlled by a selection control means which in turn controls the frequency range of operation of the oscillator.

Abstract: A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

Abstract: The gate of a CMOS transistor formed by a series connection of p-channel and n-channel FETs 21 and 22 is connected to an input terminal 23, and the drain of the CMOS transistor is connected to an output terminal 24. The source of the FET 21 is connected to a positive power supply terminal 20 via parallel-connected switchable resistance elements 37.sub.0, 37.sub.1, 37.sub.2, . . formed by p-channel FETs and having resistance values R.sub.0, R.sub.1, R.sub.2, . . . , respectively. The source of the other FET 22 is connected to a negative power supply terminal 30 via parallel-connected switchable resistance elements 38.sub.0, 38.sub.1, 38.sub.2, . . . formed by n-channel FETs and having resistance values R.sub.0, R.sub.1, R.sub.2, . . . , respectively. Delay setting signals S.sub.0, S.sub.1, . . . are decoded by a decoder 39 and one of more of its output terminals Y.sub.0, Y.sub.1 , . . . go to the high level. The output terminals Y.sub.0, Y.sub.1, Y.sub.2, . . .

Abstract: An integrated circuit (40) has a low-power mode in which at least one switched inverter stage (60) of a clock amplifier (41) is disabled in response to a stop signal. The stop signal indicates that the integrated circuit (40) is in low-power mode. In one embodiment, each switched inverter stage is a complementary metal-oxide-semiconductor (CMOS) switched inverter (60), in which an additional P-channel transistor (61) is connected between the source of an inverter P-channel transistor (62) and a positive power supply voltage terminal, and in which an additional N-channel transistor (64) is connected between a source of an inverter N-channel transistor (63) and a negative power supply voltage terminal. A non-switched inverter stage (52) remains active during low-power mode to maintain a DC value of a clock input signal near a switchpoint of the clock amplifier (41).

Abstract: Disclosed is a digital phase-locked loop circuit which provides a control signal (332, 334) for a delay circuit (304, 306, 308, 310) within the feedback path of the phase-locked loop. The circuit has a first series of delay circuits (304, 306, 308, 310), which have an incremental control signal input (332, 334), to delay an input clock signal (302) to provide the D input (311) to a D flip flop (312). The input clock signal (302) is also connected to a second series of delay circuits (314, 316, 318, 320, 322). The output of this second series (314, 316, 318, 320, 322) is connected to the clock input (323) of the D flip flop (312). The voltage controlled delay signal input for the second series of delay circuits (314, 316, 318, 320, 322) is supplied by a reference control signal (124, 126). The output of the D flip flop (312) is passed through a resistor-capacitor filtering circuit (324, 325) and fed back to the first series of delay circuits (304, 306, 308, 310) as the incremental control signal.

Abstract: A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements.

Abstract: A control and monitoring circuit for a power switch comprises a first portion (20) connected to this switch and fed with reference to a floating voltage (V.sub.F) of an electrode of this switch, a second portion (10) connected to circuits external to the switch and fed with reference to a fixed voltage, a coder (40) arranged on the side of the second portion and a suitable decoder (50) arranged on the side of the first portion.