Including Delay Line Or Charge Transfer Device Patents (Class 327/284)
  • Patent number: 10419699
    Abstract: According to one aspect, embodiments herein provide a digital unit cell comprising a photodiode, an integration capacitor coupled to the photodiode and configured to accumulate charge generated by the photodiode responsive to an input light signal incident on the photodiode over an integration period, a comparator coupled to the integration capacitor and configured to compare a voltage across the integration capacitor with a voltage reference and to generate a clock signal at a first level each time a determination is made that the voltage across the integration capacitor is greater than the voltage reference, a shift register coupled to the comparator and configured to receive the clock signal from the comparator and increase a count value each time the clock signal at the first level is received from the comparator, and an output coupled to the shift register and configured to provide the count value to an external system.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: September 17, 2019
    Assignee: RAYTHEON COMPANY
    Inventors: John F. McGee, III, Matthew Jonas
  • Patent number: 9590602
    Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 7, 2017
    Assignee: STMicroelectronics International N.V.
    Inventors: Shishir Kumar, Tanmoy Roy
  • Patent number: 9276663
    Abstract: Methods, systems, and apparatuses for providing layer-2 connectivity through a non-routed ground segment network, are described. A system includes a non-autonomous gateway in communication with a satellite configured to relay data packets. The non-autonomous gateway is configured to receive the data packets from the satellite at layer-1 (LI) of the OSI-model, generate a plurality of virtual tagging tuples within the layer-2 packet headers of the plurality of data packets. The non-autonomous gateway is further configured to transmit, at layer-2 (L2) of the OSI-model, the virtually tagged data packets. Each of the packets may include a virtual tagging tuple and an entity destination. The system further includes a L2 switch in communication with the non-autonomous gateway. The L2 switch may be configured to receive the data packets and transmit the data packets to the entity based on the virtual tuples associated with each of the data packets.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: March 1, 2016
    Assignee: ViaSat, Inc.
    Inventors: Michael Foxworthy, Girish Chandran, Jason Lau
  • Patent number: 9030245
    Abstract: Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 12, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Mototada Sakashita, Satoshi Morishita, Yoshinori Matsui, Yasushi Matsubara
  • Patent number: 8981848
    Abstract: Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: March 17, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Michael R. Kay, Philippe Gorisse, Nadim Khlat
  • Patent number: 8981828
    Abstract: A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Kwang Jang, Jen Lung Liu, Nan Xing, Jae Jin Park
  • Patent number: 8970420
    Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventors: Stephan Henzler, Markus Schimper, Stefan Tertinek
  • Patent number: 8941420
    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 27, 2015
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Masum Hossain
  • Patent number: 8742814
    Abstract: Method, modules and a system formed by connecting the modules for controlling payloads. An activation signal is propagated in the system from one module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to an external power source such as AC power.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: June 3, 2014
    Inventor: Yehuda Binder
  • Patent number: 8698537
    Abstract: In at least one aspect, an apparatus includes a plurality of inverter groups and a plurality of bias current sources. The plurality of inverter groups is configured to amplify a signal. Each of the inverter groups has one or more inverters and is in communication with at least one other inverter group of the plurality of inverter groups. Each of the bias current sources is configured to provide a bias current to a different inverter group of the plurality of inverter groups to perform signal amplification.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: April 15, 2014
    Assignee: Marvell International Ltd.
    Inventors: Yonghua Song, Pantas Sutardja
  • Patent number: 8674740
    Abstract: The present invention relates to a semiconductor circuit including: a delay unit for delaying an input signal by a predetermined time to output the delayed signal; a voltage adjusting unit for charging and discharging voltage according to a level of the input signal; and a combination unit for controlling the charging and discharging operations of the voltage adjusting unit according to signals generated using the level of the input signal and a level of the signal output from the delay unit, and it is possible to effectively remove low level noise and high level noise which are respectively mixed in a high level signal and a low level signal input to the semiconductor circuit.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chang Jae Heo
  • Patent number: 8664994
    Abstract: Embodiments of the disclosure relate to an all-digital technique for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A sub-sampling technique based delay measurement unit capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. A significant improvement in accuracy is obtained for a commercial programmable delay generator chip. The time-precision trade-off feature of the delay measurement unit is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 4, 2014
    Assignees: Department of Electronics and Information Technology, Indian Institute of Science
    Inventors: Bharadwaj Amrutur, Pratap Kumar Das
  • Publication number: 20130200937
    Abstract: A delay line with cell by cell power down capability and methods of use are provided. The delay cell includes a first gate transistor coupled to a voltage supply, a second gate transistor coupled to ground, and a reset signal provided to at least one of the first gate transistor and the second gate transistor. The reset signal turns the delay cell on and off.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 8, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vishwanath A. PATIL, Pradeep THIAGARAJAN
  • Publication number: 20130162315
    Abstract: A signal transmission/reception system includes a transmission line, a signal transmission circuit configured to generate a transfer signal and transfer the transfer signal through the transmission line, wherein a logic value of the transfer signal is changed whenever a pulse signal is input to the signal transmission circuit, and a signal reception circuit configured to receive the transfer signal through the transmission line and generate a restoration signal using the transfer signal and a delayed transfer signal obtained by delaying the transfer signal.
    Type: Application
    Filed: September 14, 2012
    Publication date: June 27, 2013
    Inventors: Sang-Mook Oh, Tae-Sik Yun
  • Publication number: 20130156131
    Abstract: An apparatus for demodulating an Amplitude Shift Keying (ASK) encoded signal is provided. The apparatus comprises a peak detector, a first comparator, a threshold generator, a delay circuit, and a second comparator. The peak detector is configured to detect a peak voltage, and the first comparator is coupled to the peak detector and receives a first threshold voltage. The threshold generator is coupled to the peak detector and is configured to generate a second threshold voltage that is proportional to peak voltage. The delay circuit is coupled to the first comparator, and the second comparator is coupled to the delay circuit and that is coupled to the threshold generator so as to receive the second threshold voltage.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Anant S. Kamath, Sriram Ramadoss, Shrinivasan Jaganathan
  • Patent number: 8461894
    Abstract: In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: June 11, 2013
    Assignee: Lattice Semiconductor Corporation
    Inventors: Fulong Zhang, Zheng Chen, Chien Kuang Chen, John Schadt
  • Publication number: 20130141151
    Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.
    Type: Application
    Filed: June 6, 2012
    Publication date: June 6, 2013
    Applicant: Ramtron International Corporation
    Inventors: Agustin Ochoa, Howard Tang
  • Patent number: 8441295
    Abstract: A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: May 14, 2013
    Assignee: University of Macau
    Inventors: He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
  • Patent number: 8390614
    Abstract: The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: March 5, 2013
    Assignee: Himax Technologies Limited
    Inventors: Wen-Teng Fan, Shih-Chun Lin
  • Publication number: 20120286840
    Abstract: A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.
    Type: Application
    Filed: November 4, 2011
    Publication date: November 15, 2012
    Applicant: University of Macau
    Inventors: He-Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
  • Patent number: 8305127
    Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Chul Shin
  • Patent number: 8294503
    Abstract: A driver chain circuit and methods are provided. The driver chain circuit includes a plurality of voltage regulators and an inverter chain. The plurality of voltage regulators are operable to provide a bias to respective groups of one or more inverters within the inverter chain. The inverter chain includes a plurality of groups of one or more inverters. Each group of inverters is configured to receive a bias from a respective one of the plurality of voltage regulators.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: October 23, 2012
    Assignee: Marvell International Ltd.
    Inventors: Yonghua Song, Pantas Sutardja
  • Patent number: 8248136
    Abstract: In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: August 21, 2012
    Assignee: Lattice Semiconductor Corporation
    Inventors: Fulong Zhang, Zheng Chen, Chien Kuang Chen, John Schadt
  • Patent number: 8242823
    Abstract: A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: August 14, 2012
    Assignee: Oracle America, Inc.
    Inventors: Hanh-Phuc Le, Robert P. Masleid
  • Patent number: 8228763
    Abstract: A device is disclosed for measuring a plurality of time intervals.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: July 24, 2012
    Assignee: Infineon Technologies AG
    Inventor: Stephan Henzler
  • Patent number: 8207786
    Abstract: A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: June 26, 2012
    Assignee: Kenet, Inc.
    Inventors: Edward Kohler, Michael P. Anthony
  • Patent number: 8203377
    Abstract: A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: June 19, 2012
    Assignee: SS SC IP, LLC
    Inventors: Robin Lynn Kelley, Fenton Rees
  • Patent number: 8198931
    Abstract: A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: June 12, 2012
    Assignee: Oracle America, Inc.
    Inventors: Hanh-Phuc Le, Robert P. Masleid, David Greenhill
  • Patent number: 8184740
    Abstract: Test signal generator (3) generates test signals represented, by four points, which comprise two sets of two points positioned in point symmetry with respect to the origin of an I/Q orthogonal coordinate system. Envelope detector (8) detects the amplitude of an envelope of the output signal from an orthogonal modulator when the test signals represented by four points are generated, and outputs a signal proportional to the square of the amplitude. Comparing unit (9) calculates an average value of output signals from envelope detector ( ) when the test signals represented by the two points of each set are generated. Controller (10) adjusts the amplitudes and/or phases of the test signals so that the average values produced when the test signals represented by the two sets of the two points are generated are equal to each other, and calculates an I/Q mismatch quantity based on the adjusted results.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: May 22, 2012
    Assignee: NEC Corporation
    Inventors: Noriaki Matsuno, Kiyoshi Yanagisawa
  • Patent number: 8179165
    Abstract: A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: May 15, 2012
    Assignee: Oracle America, Inc.
    Inventors: Hanh-Phuc Le, Robert P. Masleid
  • Patent number: 8149025
    Abstract: An exemplary gate driving circuit is adapted for receiving an external gate power supply voltage and an external control signal, sequentially generating multiple internal shift data signal groups and thereby sequentially outputting multiple gate signals. Each of the internal shift data signal groups includes multiple sequentially-generated internal shift data signals. The gate driving circuit includes multiple gate signal generating modules. Each of the gate signal generating modules includes a voltage modulation circuit and a gate output buffer circuit. The voltage modulation circuit modulates the external gate power supply voltage according to a corresponding one of the internal shift data signal groups and the external control signal, and thereby a modulated voltage signal is obtained. The gate output buffer circuit includes a plurality of parallel-coupled output stages. The output stages output the modulated voltage signal as a part of the gate signals during the output stages being sequentially enabled.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: April 3, 2012
    Assignee: AU Optronics Corp.
    Inventors: Wen-Chiang Huang, Chih-Sung Wang, Yu-Hsi Ho
  • Patent number: 8125257
    Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: February 28, 2012
    Assignee: Mosaid Technologies Incorporated
    Inventor: William Petrie
  • Patent number: 8125256
    Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 28, 2012
    Assignee: Research In Motion Limited
    Inventor: Peter A. Vlasenko
  • Patent number: 8058919
    Abstract: A delay circuit with a delay time being more accurate and a circuit area being reduced is provided. The delay circuit includes a resistance element 3, a capacitor element 4 and a connection wiring 6. The connection wiring 6 includes a first polysilicon layer 13a above a substrate 10, and a first silicide layer 14a which connects the resistance element 3 and the capacitor element 4 and is on the first polysilicon layer 13a. The capacitor element 4 includes a diffusion layer 12b in the surface region of the semiconductor substrate 10, a gate insulating layer 15b on the diffusion layer 12b, a second polysilicon layer 13b on the gate insulating layer 15b, and a second silicide layer 14b on the second polysilicon layer 13b. The resistance element 3 includes a third polysilicon layer 13c above the semiconductor substrate 10. The first, second and third polysilicon layers 13a, 13b and 13c are integrally provided. The first and second silicide layers 14a and 14b are integrally provided.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: November 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Takahashi
  • Patent number: 8030981
    Abstract: A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: October 4, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung-Hoon Kim
  • Publication number: 20110221497
    Abstract: Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.
    Type: Application
    Filed: February 1, 2011
    Publication date: September 15, 2011
    Inventors: Yan Chong, Joseph Huang, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle, Adam J. Wright
  • Patent number: 8004329
    Abstract: An apparatus includes a delay line having multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal through the delay cells. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the delay line and to output sampled values. The delay line has (i) a finer resolution closer to a target tap and (ii) a coarser resolution farther away from the target tap on each side of the target tap. For example, taps nearer the target tap can be closer to each other in order to support the finer resolution, and taps farther from the target tap can be farther apart from each other in order to support the coarser resolution. The apparatus can further include an encoder configured to encode the sampled values in order to generate an encoded value.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: August 23, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Hsing-Chien Roy Liu, Wai Cheong Chan
  • Patent number: 7999592
    Abstract: A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Patent number: 7999591
    Abstract: A deskew system includes a first voltage control delay receiving a data signal and generating N-numbered delayed data signals obtained by delaying a phase of the data signal in units of 90/N, where N is a natural number that is not less than 1. In response to a phase control signal, a second voltage control delay receives a clock and generates N-numbered delayed clocks by delaying a phase of the clock in units of 90/N. A skew compensation control unit generates a plurality of skew control signals to compensate for skew between the data signal and the clock based on the data signal, the N-numbered delayed data signals, the clock, and the N-numbered delayed clocks.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Kim, Jang Jin Nam
  • Patent number: 7982516
    Abstract: A programmable delay element with a variable delay generator employs feed forward and feedback control signals to corresponding feed forward and feedback control elements integrated within the variable delay generator. The variable delay generator is responsive to a control signal. The variable delay generator uses transfer switches to couple reactive circuit elements to a signal node in accordance with the control signal. The feed forward element couples a fixed voltage to corresponding nodes of the feed back element. The feedback element completes a bypass circuit to apply the fixed voltage to the signal node once the programmable delay element has delayed a source signal. The feed forward element is responsive to a buffered version of the source signal. The feedback element is responsive to a buffered version of the output of the delay element. A corresponding method for reducing frequency induced delay variation in a programmable delay element is disclosed.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: July 19, 2011
    Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
    Inventor: Gerald Lee Esch, Jr.
  • Patent number: 7977985
    Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: July 12, 2011
    Assignee: Mosaid Technologies Incorporated
    Inventor: Peter A. Vlasenko
  • Patent number: 7961559
    Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert C. Dixon, Robert L. Franch, Phillip J. Restle
  • Patent number: 7961021
    Abstract: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: June 14, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung-Nam Kim, Tae-Yun Kim
  • Patent number: 7956931
    Abstract: A delay circuit is disclosed. A switched-capacitor group includes a plurality of switched-capacitor units, each of which have a switching element and a capacitive element charged/discharged by turning on/off the switching element. The switched-capacitor units are connected such that the input signal is input in common to all of the switched-capacitor units and the capacitive elements are charged as well such that the capacitive elements are discharged to allow the output signal to be output from the switched-capacitor units. A switching control unit performs on/off control of the switching elements to cause the capacitive elements to be charged in sequence based on the input signal, causing the capacitive element charged last time to be discharged to allow the output signal to be output in sequence from the switched-capacitor units, and performs control of all of the switching elements to be turned off upon on/off switching of the switching elements.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: June 7, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Shunsuke Serizawa
  • Patent number: 7952411
    Abstract: A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay element, the control signal selectively being in a first logic state or a second logic state wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to the
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Robert G. Warren
  • Patent number: 7952404
    Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: May 31, 2011
    Assignee: Mosaid Technologies Incorporated
    Inventor: William Petrie
  • Patent number: 7893741
    Abstract: Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: February 22, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lipeng Cao, Khoi B. Mai, Hector Sanchez
  • Patent number: 7880524
    Abstract: A DLL circuit includes a delay unit configured to generate a DLL clock signal by delaying a reference clock signal while adjusting a delay amount in response of a level of a control voltage. An initial operation control unit is configured to control an initial level of the control voltage and generate a detection enable signal. A delay control unit is configured to generate the control voltage by comparing a phase of the reference clock signal and a phase of the DLL clock signal in response to the detection enable signal.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: February 1, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwan Dong Kim
  • Publication number: 20100327934
    Abstract: Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters.
    Type: Application
    Filed: August 5, 2009
    Publication date: December 30, 2010
    Inventors: Ronald A. KAPUSTA, Doris Lin
  • Patent number: 7859318
    Abstract: A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Daniel Dreps, Daniel Friedman, Seongwon Kim, Hector Saenz, Glen Wiedemeier