Abstract: A delay circuit having a delay element circuit composed of a plurality of series-connected first circuit elements being connected to a common power supply line and having a delay time varying correspondingly to a voltage of the common power supply line, the delay element circuit being adapted to receive an input signal and output an output signal obtained by delaying the input signal, and a PLL circuit including an oscillator circuit composed of a plurality of series-connected second circuit elements, which are equivalent to the first circuit elements, respectively, are connected to the common power supply line. The PLL circuit is adapted to oscillate the oscillator circuit at a predetermined frequency locked to a reference clock frequency by comparing a phase of the reference clock signal with a phase of an output frequency of the oscillator circuit and controlling the voltage of the power supply line according to a result of the comparison.

Abstract: An analog synchronization circuit includes an input buffer which is supplied with an external clock signal, a delay monitor which is supplied with a clock signal output from the input buffer, an output buffer for outputting a clock signal synchronous with the external clock signal and two charge balance delay circuits. The two charge balance delay circuits are equivalent to delay lines in a mirror type delay locked loop. Each charge balance delay circuits operates once in two consecutive cycles of the external clock signal. The two charge balance delay circuits alternately operate and output signals of the charge balance delay circuits are supplied to the output buffer via an OR gate. First and second capacitors are provided in each charge balance delay circuits. A first current source circuit charges the first capacitor for a time equivalent to a delay time of a forward pulse. The second capacitor is charged by a second current source circuit.

Abstract: A delay circuit comprises a charge/discharge circuit and a logic circuit. The charge/discharge circuit is used to moderate a slope of change of an input signal. The logic circuit receives a charge/discharge signal output from the charge/discharge circuit, and is used to change an output signal of the logic circuit when the charge/discharge signal exceeds a threshold value of the logic circuit. A time constant in the charge/discharge circuit is varied in accordance with the change in the output signal of the logic circuit. This serves to alleviate the malfunctioning and timing constraint problems that occur after the threshold value of the next-stage circuit (logic circuit) is exceeded.

Abstract: Circuitry for introducing a delay to a signal comprising input means for receiving the signal to be delayed; a first delay path; a second delay path; selection means for causing the signal passing through a selected one of the delay paths to be output from said circuitry; comparing means for comparing the phase difference between the signal output by said circuitry and the input to said selected delay path to provide a first comparison signal and for comparing the phase delay of said first delay path with that of said second delay path to provide a second comparison signal, wherein said first and second comparison signals are used by the selection means to determine which of said delay paths selected.

Abstract: A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: The present invention discloses a delay circuit having a constant delay time. The delay circuit comprises an electric wire for transmitting a driving signal from a driver; a capacitor connected between said electric wire and ground, and for delaying transmission of said driving signal; and a current source connected to said electric wire and capacitor in parallel, and for keeping an amount of an electric current applied to said capacitor constant when a signal applied to said capacitor is varied.

Abstract: A system and method for providing a programmable delay to an input signal in a device requiring setup and hold times for input signal, such as a DRAM device. In one embodiment, the programmable delay network 5 comprises a plurality of delay devices and at least one fuse connected between the input of the delay network 5 and the output of the delay network 5. Each fuse can connect in series with at least one delay device in such a manner that opening a fuse, or a combination of fuses, changes the amount of delay time the input signal experiences through the delay network.

Abstract: A delay circuit having: a first delay inverter having complementarily-connected first p-channel FET and first n-channel FET, one of the first p-channel and first n-channel FETs being provided with a gate length elongated; a second delay inverter having complementarily-connected second p-channel FET and second n-channel FET, one of the second p-channel and second n-channel FETs being provided with a gate length elongated; a NAND gate having a first input to which the input signal is applied and a second input to which the output signal of the second delay inverter is applied; and an inverter to output inverting the output signal of the NAND gate.

Abstract: An interface cell transmits a signal with a delay time corresponding to a delay time control signal. A delay time control circuit consists of a delay chain and a PLL circuit. The delay chain consists of a plurality of series-connected interface cells to a head cell of which a clock signal is supplied, and a delay signal of a clock signal is then fetched from the interface cell at an arbitrary stage. The PLL circuit generates a delay time control signal so as to make phase difference between the clock signal and the delay signal equal. This is true of a delay cell. A phase difference compensation circuit is provided on an output end of a clock line of the integrated circuit to delay an input clock signal based on an input control signal.

Abstract: A delay circuit using MOS transistors for use of load capacitance which produces a stable delay effect for variations in signal voltage is provided. A gate of a P-type MOS transistor for load capacitance and a gate of an N-type MOS transistor for load capacitance are connected to a signal line. A resistor and CMOS inverters are used to apply a boosted voltage higher than a supply voltage VDD to a source-drain of the P-type MOS transistor for load capacitance and a substrate voltage lower than a ground voltage to a source-drain of the N-type MOS transistor for load capacitance. As a result, a gate voltage range for allowing the MOS transistors for load capacitance to have a capacitance is extended, and a stable delay effect is assured for a widened variation of signal current flowing on the signal line.

Abstract: A signal processor connected to a charge-coupled device includes a plurality of delay lines with different delay times connected to a node on a signal line extending from the charge-coupled device to an output terminal of the signal processor, and a selector connected to the plurality of delay lines for selecting an optimum one of the plurality of delay lines. As a result, an effective signal time period of a time delay-free signal inputted into an input terminal of a selected one of the delay lines is superimposed with a field through time period of a delayed signal reciprocally transmitted through the selected one of the delay lines and returned to the input terminal of the selected one of the delay lines.

Abstract: A variable digital delay line with an insertion delay as low as a single delay element yet capable of providing a large programmable delay with a small simple control mechanism. A loop connects an input to an output through selectable first delay elements such as 2:1 muxes and selectable second delay elements such as pairs of inverters by way of a plurality of intermediate nodes having a tap. A plurality of sneak paths are available wherein the loop by passes a remainder of first delay elements and/or second delay elements by way of the taps at the intermediate nodes.

Abstract: A method of controlling a clock, including the steps of (a) receiving an external clock signal, (b) calculating a first period of time defined as (T1-T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, (c) stopping the external clock signal to be transmitted by the first period of time, and (d) driving the external clock signal to thereby turn the external clock signal into an internal clock signal. The method makes it possible to detect delay in a clock signal, and generate no delay error inherent to a digital circuit.

Abstract: A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. Unlike previous circuits and methods, a single synchronization step is sufficient, provided that the frequency of the input clock signal is stable. A circuit according to the invention includes an input clock terminal supplying an input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that provides the necessary additional delay to synchronize the feedback clock signal to the input clock signal.

Abstract: In digital circuits, such as memory circuits, it is sometimes necessary to delay one signal a precise amount of time relative a reference signal. One way to do this is to feed the reference signal to a delay-locked loop which generates a set of signals, each delayed a different amount relative the reference signal. However, as circuits get faster and faster, conventional delay-locked loops require the addition of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal.

Abstract: A method and system for synchronizing a reference signal and an output signal produced by an electrical circuit, the electrical circuit comprising an analog portion and a digital portion, is disclosed. The method comprises the steps of utilizing the digital portion to produce a phase-adjusted signal and utilizing the analog portion to produce an output signal in substantially the same phase as the phase-adjusted signal. Through the use of the method and system in accordance with the present invention, the large bi-direction shift register of conventional hybrid DLLs is no longer necessary and high speed DLLs will be capable of providing high resolution deskewed clocks in a shorter amount of time. The use of the present invention also facilitates the coverage of a wider range of clock frequencies.

Abstract: A delayed matching signal generator and frequency multiplier using scaled delay networks for providing precisely delayed matching signals and multiplied frequency signals is provided. The system and method of phase shifting a periodic input digital signal comprises a reference delay line, a replica delay line, and a matched characteristics control system. The reference delay line is composed of multiple reference delay stages through which the input signal is propagated, and the replica delay line is composed of replica delay stages scaled in proportion to the multiple reference delay stages by a scaled delay factor wherein the input signal is propagated. The matched characteristics control system is coupled to the reference delay line and the replica delay line for extracting a phase shifted signal from the replica delay line based upon the scaled delay factor and a scaled propagation of the input signal through the reference delay line.

Abstract: An analog delay line uses an analog-to-digital (A/D) converter which converts an analog signal into a plurality of digital signals. Digital delay lines, each including a series of digital delay elements, delay the respective digital signals. A digital-to-analog (D/A) converter converts the digital signals back into a delayed analog signal.

Abstract: A method and apparatus are provided for reducing distortion in a dynamically delayed digital sample stream of an imaging system. The method includes the steps of delta-sigma modulating an input analog signal of the imaging system at a frequency above the Nyquist frequency of the input analog signal to generate a digital sample stream and changing a length of the sample stream to delay a portion of the sample stream while maintaining synchronism between a delta-sigma modulator and a demodulator of the system.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: The delay unit has first delay elements each having a first delay time and second delay elements each having a second delay time. The second delay time is greater than the first delay time. A control unit controls the delay time of the delay unit by, first, incrementally increasing or by incrementally reducing the number of second delay elements in the signal path and thereby altering the actual value of the delay in the direction towards a desired (setpoint) value until the desired value is exceeded. The control unit then, by incrementally reducing or increasing, respectively, the number of first delay elements in the signal path, alters the actual value of the delay in the direction towards the desired value until the desired value is exceeded once more. In the event of subsequent changes in the desired value or in the actual value, the number of first delay elements is incrementally altered, while the number of second delay elements in the signal path is kept constant.

Abstract: An edge triggered adjustable delay line circuit to determine the difference in time between a transition of a first signal and a transition of the second signal; a variably additive delay line circuit that will delay an input signal by a delay factor that is the sum of a multiplicity of variable delay factors; and a timing synchronization circuit to synchronize an internal timing signal with an external timing signal within one timing cycle is described. The timing synchronization circuit will utilize the edge triggered delay line and the variably additive delay line circuits to determine the synchronization parameters to synchronize the internal timing signal with the external timing signal.

Abstract: A delay circuit based on gate delay enables precise adjustment of a delay value. The delay circuit is composed of a plurality of p-channel transistors and n-channel transistors connected in series which are provided with capabilities that differ, ranging from the transistors closer to a power supply to the transistors closer to an output end so as to change the output drive capability and the input capacity independently, thereby improving the adjustment accuracy of the delay value of the circuit.

Abstract: Delay Locked Loop device generates an internal clock by receiving an external clock. Multiplexer is provided to receive N delay signals outputted from the first to Nth delay elements which receives the external clock. The Delay Locked Loop device generates the internal clock by selecting one of the N delay signals. The phase of the internal clock follows the phase of the external clock.

Abstract: A timing signal synchronization circuit to align an internal timing clock within an integrated circuit with an external system clock with minimum skew and within one cycle of the external system clock is disclosed. A timing signal synchronization circuit has an input buffer subcircuit to receive and delay the external system clock. A fixed delay line circuit is connected to the input buffer subcircuit to delay the received external system clock by a second delay factor to create a first timing signal. The first timing signal is the input to a first and a second measurement delay line. Each will respectively measure a first part and a second part of a period of the first timing signal. A first latch array will receive the measurement and create a first latch signal. A second latch array will receive the measurement and create a second latch signal.

Abstract: A programmable phase shifter includes a tapped delay line for successively delaying a periodic reference signal to produce a set of phase distributed tap signals. A multiplexer selects one of the tap signals as input to a programmable delay circuit which further delays the selected tap signal to produce an output signal that is phase shifted from the reference signal. A programmable data converter converts input data indicting a desired phase shift between the reference signal and the output signal into data for controlling the multiplexer selection and the amount of delay provided by the programmable delay circuit. The relationship between conversion table input and output data is adjusted so that the period of the output signal has a desired linear relationship to the input data value.

Abstract: A system for aligning the phase of signals generated by a selectable standby clock source which has a predetermined frequency with the phase of signals generated by a selected clock source which has the same frequency as signals generated by the standby clock source. The system comprises (1) a delay line having a plurality of delay elements which is configured to receive the signals generated by the standby clock source so that the output signal of each delay element is a delayed version of the standby clock source; (2) a decoder configured to receive each of the delayed versions of the signals generated by the standby clock signal source and generates a selection signal corresponding to a desired one of the delayed version signals that is aligned with signals generated by the selected clock source within a specifiable phase difference; and (3) a selector configured to receive the selection signal so as to select the desired delayed version signal as a new standby clock source.

Abstract: A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.

Abstract: A controlled delay circuit having a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.

Abstract: An apparatus and method for delaying a signal using a variable delay line circuit. A variable delay line circuit includes first and second delay lines, each including a plurality of delay elements. A multiplexer is coupled to respective outputs of the first and second delay lines and selectively couples the output of one of the first or second delay lines to an output of the multiplexer. A control circuit is coupled to the multiplexer and the first and second delay lines, and controls the multiplexer so as to produce a delayed signal at the multiplexer output using one of the first or second delay lines, and changes a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines.

Abstract: A delay cell for use in binary delay line which includes a delay circuit having N outputs where N.gtoreq.2, each delay circuit coupled to an input through N-1 serially connected unit cells. For each output there are P unit cells having a unit delay of t.sub.P0 and N-1-P unit cells having a unit delay of t.sub.p1. The N outputs are ordered such that each output other than the first is delayed with respect to an immediately preceding output by t.sub.p1 -t.sub.p0, and P goes in succession from N-1 to 0 in unit steps. Each value of P corresponds to only one of the N outputs.

Abstract: An electric charge is supplied to or received from capacitors (C1, C2) when a piezoelectric element (C3) is charged or discharged by controlling transistors (Q17, Q18, Q15, Q10) which are in a first charging path (CL1) for charging from a power supply to the piezoelectric element (C3), a second charging path (CL2) for charging from the capacitors (C1, C2) to the piezoelectric element (C3), a first discharging path (DL1) for discharging from the piezoelectric element (C3) to ground (G) and a second discharging path (DL2) for discharging from the piezoelectric element (C3) to the capacitors (C1, C2), respectively.

Abstract: A programmable delay line has delay elements that are responsive to at least one of two different calibration signals for varying their drive power characteristics and hence the delay period. Preferably, there are two sets of delay elements, responsive to a respective calibration signal, with one set comprising much fewer delay elements than the other set. The delay elements may be responsive to a digital calibration signal for discrete control, an analog calibration signal for continuous control, or both.

Abstract: A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.

Abstract: This invention describes a circuit and method for creating a double clock frequency. The circuit uses a sequence of delay elements to delay the primary clock. A delay detector determines when a delayed clock is out of phase with the primary clock. A delay is selected that is one half the delay producing the out of phase delayed clock. The selected delay is used to combine with the primary clock to produce a double clock frequency. Control signals for selecting the "half" delayed clock are latched to prevent clock jitter and spurious signal from producing error signals in the double frequency clock. Different duty cycles can be established by varying the selected delay.

Abstract: A clock circuit including a first delay circuit comprising an input terminal and a series of logic circuits, each of the logic circuits including an output terminal and first and second input terminals. The input terminal is coupled to the first input terminal of a first logic circuit in the series and the output of the first logic circuit is coupled to the second input terminal of a second logic circuit in the series. The output of the second logic circuit is coupled to the first input terminal of a third logic circuit in the series, and subsequent logic circuits in the series have alternately the first or second input terminal coupled to the output terminal of an immediately preceding logic circuit in the series. The circuit also includes a second delay circuit comprising an output terminal and a series of logic circuits, each of the logic circuits including an output terminal and first and second input terminals.

Abstract: Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n, 32.sub.0 -32.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a first embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus.

Abstract: A delay element including a stack of p-channel transistors connected in series and a stack of n-channel transistors connected in series with the source of the top p-channel transistor connected to a positive voltage and the source of the bottom n-channel transistor connected to ground. The drain of each n-channel transistor is connected to the drain of a corresponding one of the p-channel transistors and all gates are interconnected and serve as the input to the delay element. The output of the delay element can be any one of the drain connections.

Abstract: A programmable delay circuit produces an OUTPUT signal following an INPUT signal with a delay selected by input delay selection data. The delay circuit includes a tapped delay line, a multiplexer, a delay adjustment stage and a programmable encoder. The delay line includes a set of N delay elements connected in series for successively delaying the INPUT signal to produce a set of N output TAP signals. The multiplexer passes a selected TAP signal to the delay adjustment stage. The delay adjustment stage delays the selected TAP signal to produce the OUTPUT signal. The programmable encoder encodes the input delay selection data to provide signals for controlling the multiplexer and for adjusting the delay of the delay adjustment stage. The manner in which the encoder encodes each separate delay selection data value is adjustable so that each of the N selectable delays can be separately calibrated.

Abstract: A delay circuit includes a charge/discharge circuit and a logic circuit. The charge/discharge circuit is used to moderate a slope of change of an input signal. The logic circuit receives a charge/discharge signal output from the charge/discharge circuit, and is used to change an output signal of the logic circuit when the charge/discharge signal exceeds a threshold value of the logic circuit. A time constant in the charge/discharge circuit is varied in accordance with the change in the output signal of the logic circuit. This serves to alleviate the malfunctioning and timing constraint problems that occur after the threshold value of the next-stage circuit (logic circuit) is exceeded.

Abstract: By setting the substrate potential of a transistor of a driver means lower than the substrate potential of a transistor of a bias means in an intermediate potential generation circuit which supplies a cell plate potential of a memory cell and a precharge potential of a bit line, a flow of a through current in a transistor of the driver means is prevented. Therefore, reduction of a power consumption of the device during standby can be realized.

Abstract: A frequency generator is disclosed including a plurality of inverters employing the gate of a PMOS and NMOS as their common input, and employing the source of the PMOS and drain of the NMOS as their common output, the plurality of inverters being serially connected, the output node of the output inverter being connected to the input node of the input inverter; and a current mirror consisting of two transistors having the same electrical characteristic, the current mirror being connected to the source of the NMOS of the input inverter, a signal transmission delay time of the current mirror being controlled by a predetermined current value applied from an external current source.

Abstract: A delay line formed by a set of series-connected logic gates produces a sequence of output pulses in delayed response to a sequence of input pulses. The delay provided by a delay line changes with the frequency of its input pulse sequence because of temperature change in the gates due to changing power usage. Therefore a pulse stuffing circuit is provided to monitor the sequence of input pulses supplied to the delay line and to generate one or more stuff pulses when a period between successive input pulses exceeds a target maximum period. Each stuff pulse is sent as an additional input pulse to the delay circuit to decrease the period between input signal pulses. Although the delay circuit adds extra pulses to its output pulse sequence in response to the stuff pulses, the pulse stuffing circuit includes a gating circuit for removing those extra pulses from the output pulse sequence.

Abstract: The present invention discloses a delay circuit which obtains constant a delay time of delay circuit using an output capacitor by making the resistance of MOS transistor lowest, at the low voltage, middle at the intermediate voltage, and largest at the high voltage, so that the delay time of delay circuit using an output capacitor is kept constant regardless of the change in power source voltage.

Abstract: A delay circuit which employs a Miller effect to delay a signal while driving a subsequent amplifier stage. The Miller effect is dependent upon loading of the circuits on an integrated circuit upon which the delay circuit is implemented, which allows the delay circuit to compensate its delay in relation to other process variation delays present on the integrated circuit. The delay circuit has a first delay stage which delays an input signal and drives a second stage. The delay circuit incorporates a dummy drive stage which adds loading to the first delay stage. In addition, the dummy stage experiences dynamic loading of the delay chain between the first and second stages which allows the coupling of the effect of this dynamic loading back to the first stage through the Miller effect.

Abstract: A layout area includes a clock interconnection consisting of an upward interconnection and a downward interconnection. The upward interconnection extends from the output terminal of a clock buffer which receives an external clock signal to a turning point while passing along the vicinity of a plurality of flip-flops. The downward interconnection extends from the turning point to a free end, reversing along the upward interconnection. Clock branch circuits are provided in the vicinity of the flip-flops. The clock branch circuits have a function of letting a third clock signal make a transition when the sum of the time integral of a first clock signal on the upward interconnection and the time integral of a second clock signal on the downward interconnection has become equal to the time integral for one pulse of one of the first clock signal and the second clock signal.

Abstract: A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for

Abstract: A phase adjusting circuit includes a circuit for providing an internal clock signal in synchronization with a reference clock signal, a delay circuit for delaying the internal clock signal for a predetermined delay time and an adjusting section for adjusting a phase difference between a phase of the reference clock signal and a phase of the internal clock signal delayed for the predetermined delay time.