Including Delay Line Or Charge Transfer Device Patents (Class 327/284)
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Patent number: 7952404Abstract: A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Switching jitter of the DLL is reduced since the delay of the step of the CDL that is switched when on an underflow or overflow condition of the FDL is detected is equivalent to the delay of the provided number of steps of the FDL.Type: GrantFiled: August 15, 2008Date of Patent: May 31, 2011Assignee: Mosaid Technologies IncorporatedInventor: William Petrie
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Patent number: 7893741Abstract: Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.Type: GrantFiled: June 12, 2009Date of Patent: February 22, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Lipeng Cao, Khoi B. Mai, Hector Sanchez
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Patent number: 7880524Abstract: A DLL circuit includes a delay unit configured to generate a DLL clock signal by delaying a reference clock signal while adjusting a delay amount in response of a level of a control voltage. An initial operation control unit is configured to control an initial level of the control voltage and generate a detection enable signal. A delay control unit is configured to generate the control voltage by comparing a phase of the reference clock signal and a phase of the DLL clock signal in response to the detection enable signal.Type: GrantFiled: December 30, 2008Date of Patent: February 1, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kwan Dong Kim
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Publication number: 20100327934Abstract: Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters.Type: ApplicationFiled: August 5, 2009Publication date: December 30, 2010Inventors: Ronald A. KAPUSTA, Doris Lin
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Patent number: 7859318Abstract: A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator.Type: GrantFiled: February 14, 2008Date of Patent: December 28, 2010Assignee: International Business Machines CorporationInventors: Daniel Dreps, Daniel Friedman, Seongwon Kim, Hector Saenz, Glen Wiedemeier
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Patent number: 7830191Abstract: A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted.Type: GrantFiled: March 2, 2009Date of Patent: November 9, 2010Assignee: Advantest CorporationInventors: Shoji Kojima, Masakatsu Suda
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Patent number: 7830193Abstract: A time-delay buffer having a CMOS inverter and a capacitor is disclosed. The CMOS inverter of the time-delay buffer has a silicide layer partially disposed on the transistor gate of the CMOS and a non-silicide region lain in between the silicide layers. Therefore, the time-delay buffer of the present invention has a resistance therein, and results in a period of time delayed in the circuit.Type: GrantFiled: November 24, 2008Date of Patent: November 9, 2010Assignee: United Microelectronics Corp.Inventor: Hung-Sung Lin
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Patent number: 7800696Abstract: A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors; and a switching control unit that performs on/off control of the charging and the discharging of the MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence.Type: GrantFiled: September 7, 2006Date of Patent: September 21, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Shunsuke Serizawa, Tetsuo Sakata, Masato Onaya
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Publication number: 20100156468Abstract: The even-number-stage pulse delay includes a ring delay line constituted of an even number of inverter circuits connected in a ring around which main edge and a reset edge circulate together. The even-number-stage pulse delay is provided with an operation monitoring section configured to detect whether or not the main and reset edges are circulating around the ring delay line.Type: ApplicationFiled: December 16, 2009Publication date: June 24, 2010Applicant: DENSO CORPORATIONInventors: Takamoto Watanabe, Shigenori Yamauchi
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Patent number: 7741892Abstract: Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.Type: GrantFiled: June 27, 2008Date of Patent: June 22, 2010Assignee: Hynix Semiconductor Inc.Inventor: Tae Jin Kang
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Patent number: 7737747Abstract: A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry.Type: GrantFiled: August 31, 2007Date of Patent: June 15, 2010Assignee: Texas Instruments IncorporatedInventor: Anant Shankar Kamath
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Patent number: 7719332Abstract: Delay lock loop circuits are described, which may include two or more delay stages that each includes a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, which provides a first output. The first output drives an input of the second delay stage, which provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the values maintained in the first and second selector registers are synchronized to the first and second outputs, respectively.Type: GrantFiled: August 1, 2007Date of Patent: May 18, 2010Assignee: Texas Instruments IncorporatedInventors: Keerthinarayan P. Heragu, Padattil K. Nisha
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Patent number: 7642866Abstract: A dynamic dual domino oscillating ring circuit is described, which has multiple non-inverting dual domino circuits, each having a signal input, N and P-domino triggers, precharge and pre-discharge, N and P-domino cutoffs and an output inverter. A number of the dual domino circuits are coupled in series, the output of one feeding the input of the next, to form a dual domino chain, which form stages of the dual domino ring. A number of the stages are coupled in series, the output of one feeding the input of the next, to form the ring. The first dual domino circuit of the chain receives a signal input and the N and P triggers for the chain. Within the ring, the output of each stage feeds the input signal to the next stage and is fed back to clock an earlier stage to allow the ring to oscillate.Type: GrantFiled: December 30, 2005Date of Patent: January 5, 2010Inventor: Robert Masleid
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Patent number: 7629856Abstract: A delay stage for a semiconductor device includes at least one delay branch and at least one controllable switching apparatus. The at least one controllable switching apparatus is configured to connect a predefined amount of the at least one delay branch to a supply voltage.Type: GrantFiled: October 27, 2006Date of Patent: December 8, 2009Assignee: Infineon Technologies AGInventor: Edwin Thaller
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Patent number: 7626435Abstract: A delay line architecture is presented. In one embodiment, the delay line is used to introduce delay compensation into a circuit design at the top level of the circuit design.Type: GrantFiled: July 27, 2005Date of Patent: December 1, 2009Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Benjamin Haugestuen
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Patent number: 7605630Abstract: A delay circuit respectively delays rising and falling edges of an input signal. The delay circuit comprises first and second delay lines, a control circuit, and first and second logic circuits. The first delay line delays the first input signal the first delay time to output the first delay output signal. The second delay line delays the first input signal the second delay time to output the second delay output signal. The control circuit outputs the control signal according to the first input signal. The first logic circuit receives the first delay output signal and outputs the first output signal according to the control signal and the first input signal. The second logic circuit receives the second delay output signal and outputs the second output signal according to the control signal and the first input signal. The first and second delay times are different.Type: GrantFiled: August 27, 2007Date of Patent: October 20, 2009Assignee: Nanya Technology CorporationInventor: Wen-Chang Cheng
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Patent number: 7576585Abstract: A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.Type: GrantFiled: March 12, 2008Date of Patent: August 18, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Shigetaka Asano, Kazuyoshi Kikuta
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Patent number: 7576586Abstract: In a differential bucket-brigade device (BBD) pipeline it is necessary for proper circuit function to maintain the common-mode charge within an acceptable range at each pipeline stage. Embodiments of the present invention provide for reducing common-mode charge variations in a differential charge-domain pipeline. Common mode charge at a given stage of the pipeline is adjusted according to one or more measured characteristics, thereby controlling common mode charge variation throughout the differential charge-domain pipeline.Type: GrantFiled: February 8, 2008Date of Patent: August 18, 2009Assignee: Kenet, Inc.Inventor: Michael P. Anthony
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Publication number: 20090146717Abstract: A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.Type: ApplicationFiled: December 8, 2008Publication date: June 11, 2009Applicant: Kenet, Inc.Inventors: Edward Kohler, Michael P. Anthony
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Patent number: 7545195Abstract: A variable delay element includes first and second input stages, each input stage comprising a charge pumping circuit and a discharging circuit, each charge pumping circuit and each discharging circuit associated with the first and second input stages configured to operate on opposite phases of an input signal, and an output stage comprising at least two transistors. The transistors are independently controlled by the first and second input stages and produce an output signal which is a delayed version of the input signal.Type: GrantFiled: November 14, 2006Date of Patent: June 9, 2009Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.Inventor: Michael Martin Farmer
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Publication number: 20090135040Abstract: An inverter circuit configuring a delay unit is a so-called CMOS transistor including a PMOS transistor and an NMOS transistor, of which respective gates are interconnected and respective drains are interconnected. The source and a back gate of the NMOS transistor are connected to the ground. The source of the PMOS transistor is connected to a positive drive terminal and controlled by an analog input signal. The back gate of the PMOS transistor is connected to a control terminal and controlled by a control signal.Type: ApplicationFiled: November 25, 2008Publication date: May 28, 2009Applicant: DENSO CORPORATIONInventors: Takamoto Watanabe, Shigenori Yamauchi
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Patent number: 7501973Abstract: A time-to-digital converter includes a first delay line, a second delay line, comparators, and an encoder. The first delay line includes first resistors coupled in series and receives a first signal through a start node. The second delay line includes second resistors coupled in series and receives a second signal through a node corresponding to an end node of the first delay line. The comparators compare first voltages of nodes on the first delay line with second voltages of corresponding nodes on the second delay line. The encoder generates a digital code based on outputs of the comparators. Therefore, the time-to-digital converter may decrease a chip size thereof and lower power consumption, and the time-to-digital converter may increase a range of a maximum delay time between two signals.Type: GrantFiled: November 15, 2007Date of Patent: March 10, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyoung-Chul Choi, Seong-Hwan Cho, Soh-Myung Ha
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Patent number: 7492204Abstract: One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.Type: GrantFiled: August 13, 2007Date of Patent: February 17, 2009Assignee: NVIDIA CorporationInventors: Hwong-Kwo Lin, Ge Yang, Ethan A. Frazier, Charles Chew-Yuen Young
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Publication number: 20080309386Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, careful selection of parameters for providing the reference voltage and/or providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.Type: ApplicationFiled: June 15, 2007Publication date: December 18, 2008Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventor: Peter A. Vlasenko
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Publication number: 20080309392Abstract: A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay element, the control signal selectively being in a first logic state or a second logic state wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to theType: ApplicationFiled: December 16, 2005Publication date: December 18, 2008Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITEDInventor: Robert G. Warren
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Patent number: 7456667Abstract: The duty cycle of a signal is modified by passing the signal through a plurality of inverting stages. The inverting stages each have bias circuitry to influence the input switching threshold of inverters. Multiple duty cycle modification circuits produce non-overlapping local oscillator signals in a system.Type: GrantFiled: December 22, 2006Date of Patent: November 25, 2008Inventors: Stewart S. Taylor, Jing-Hong C Zhan
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Patent number: 7446585Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.Type: GrantFiled: April 23, 2007Date of Patent: November 4, 2008Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Shiun-Dian Jan, Yuan-Hua Chu
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Patent number: 7432753Abstract: A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2?k?N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1?i?N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.Type: GrantFiled: October 18, 2007Date of Patent: October 7, 2008Assignee: Elpida Memory Inc.Inventor: Tadashi Onodera
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Patent number: 7425858Abstract: A delay line is periodically configured into a delay-locked loop for calibration purposes. That is, the delay line is operated in an open loop mode during a first time period in which a signal, such as an aperiodic signal, is the input signal into the delay line. Periodically, the delay line is configured into a delay-locked loop and the delay line is recalibrated based on a periodic signal supplied to the delay-locked loop.Type: GrantFiled: January 6, 2006Date of Patent: September 16, 2008Assignee: Advanced Micro Devices, Inc.Inventor: Anand Daga
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Patent number: 7425857Abstract: A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.Type: GrantFiled: February 9, 2005Date of Patent: September 16, 2008Assignee: STMicroelectronics S.r.l.Inventors: Pierangelo Confalonieri, Marco Zamprogno, Federico Garibaldi
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Patent number: 7417478Abstract: Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay units, among the delay units, are coupled to an even clock line to generate a first intermediate clock. Odd delay units are coupled to an odd clock line to generate a second intermediate clock. The even and odd delay units are configured to in a manner intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.Type: GrantFiled: February 6, 2006Date of Patent: August 26, 2008Assignee: Micron Technology, Inc.Inventors: Kang Yong Kim, Jongtae Kwak
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Patent number: 7378892Abstract: A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously. The device is configured to generate the at least one output clock signal depending on the differently delayed clock signals with a settable phase relationship to the non-delayed input clock signal, wherein the phase relationship is settable independently of the delay provided by the delaying means. It is particularly provided that the phase relationship between the delayed output clock signal and the non-delayed input clock signal is automatically controlled to a desired phase relationship independently of the delay supplied by the delaying means.Type: GrantFiled: August 1, 2005Date of Patent: May 27, 2008Assignee: Infineon Technologies AGInventor: Peter Gregorius
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Patent number: 7375564Abstract: A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes delay cells having various unit time delays. The number of delay cells is adjusted in response to a shift signal. The delay line receives the external clock signal and outputs an output clock signal. The filter unit generates the shift signal in response to the error control signal. In the delay-locked loop, the front delay cells, which compensate for a delay of an external clock signal having a high frequency, have short unit time delays. The rear delay cells, which compensate for a delay of the external clock signal having a low frequency, have long unit time delays.Type: GrantFiled: November 18, 2003Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Geun-Hee Cho, Byung-Hoon Jeong, Kyu-Hyoun Kim
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Patent number: 7368967Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.Type: GrantFiled: March 21, 2007Date of Patent: May 6, 2008Assignee: Fujitsu LimitedInventor: Yoshinori Okajima
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Patent number: 7339409Abstract: An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT(Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the pre-driving unit; and a slew rate modeling unit for generating a pre-driver bias signal to constantly maintain effective resistances of a pull-up path and a pull-down path of the pre-driving unit by modeling the pre-driving unit.Type: GrantFiled: December 21, 2004Date of Patent: March 4, 2008Assignee: Hynix Semiconductor Inc.Inventors: Seok-Woo Choi, Hong-June Park
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Publication number: 20080042715Abstract: A delay circuit comprises a first inverter, a resistor, a first capacitor and a second capacitor. The first inverter comprises an input end and a first node and an input signal is received by the input end. The resistor is coupled between the first node and a second node. The first capacitor is coupled between the second node and a voltage source. The second capacitor is coupled between the second node and a ground.Type: ApplicationFiled: March 30, 2007Publication date: February 21, 2008Inventors: Wen-Wann Sheen, Ming-Hsin Chan
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Patent number: 7332950Abstract: A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured delay during a reset operation.Type: GrantFiled: June 14, 2005Date of Patent: February 19, 2008Assignee: Micron Technology, Inc.Inventor: Greg A. Blodgett
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Patent number: 7295054Abstract: The present invention relates generally to a buffer of a drive Integrated Circuit (IC) and, more particularly, to a buffer of a drive IC for driving a spatial light modulator that can meet a desired dynamic slew rate characteristic by controlling current that affects a slew rate.Type: GrantFiled: November 18, 2004Date of Patent: November 13, 2007Assignee: Samsung Electro-Mechanics Co., LtdInventors: Byung-Hoon Kim, Kyoung-Soo Kwon, Chae-Dong Go, Chan-Woo Park
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Patent number: 7248125Abstract: An even number phase ring oscillator having at least eight, equally spaced phases. The oscillator includes at least eight stages, defining at least four pairs of stages, with each pair including a first stage and an associated second stage. The first stages are arranged such that an output of a first stage defines a primary input of another first stage, with the output of the first stage of the last pair defining the primary input of the second stage of the first pair. The second stages are arranged such that an output of a second stage defines a primary input of an another second stage, with the output of the second stage of the last pair crossing over the output of the first stage of the last pair and defining a primary input of the first stage of the first pair, thereby defining a closed loop.Type: GrantFiled: January 13, 2005Date of Patent: July 24, 2007Assignee: Advanced Micro Devices, Inc.Inventor: Gerald Robert Talbot
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Patent number: 7233185Abstract: A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.Type: GrantFiled: April 29, 2004Date of Patent: June 19, 2007Assignee: Atmel CorporationInventors: John L. Fagan, Mark A. Bossard, Daniel S. Cohen
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Patent number: 7230498Abstract: A delay line for a ring oscillator circuit includes at least one delay stage having a multiple logic gate delay cells driven by a multiplexer. The multiplexer is symmetrically configured and includes multiple logic gates that are similar to the logic gates of the delay stage.Type: GrantFiled: April 22, 2005Date of Patent: June 12, 2007Assignee: STMicroelectronics S.R.L.Inventor: Mauro Osvaldella
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Patent number: 7222036Abstract: Delays through components of a programmable device are determined transparently to the user through the use of mimic paths. For each delay path to be measured, at least one mimic path is created that has similar components and characteristics to the actual path to be measured. A signal fed through this mimic path will experience similar delay to a signal passing through the actual path, which can be affected by temperature and voltage variations during operation. A swept clock signal can be passed to a register latching the mimic signal data, producing output that can be fed to lead/lag logic to determine a current value of the delay through the mimic path. This delay can be compared to a previous delay determination to approximate an adjustment to be made to a sampling clock used to latch the actual data into the appropriate register at the middle of the latching window.Type: GrantFiled: March 31, 2006Date of Patent: May 22, 2007Assignee: Altera CorporationInventor: Neil Kenneth Thorne
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Patent number: 7173468Abstract: A delay line includes a delay chain consisting of series-connected NAND gate delay stages with a delayed output signal extracted from the final delay stage. Tap decode gates are preferably used to “inject” the input signal to be delayed into the delay chain using one input of the NAND gate delay stage, referred to as an “injection point.” The desired delay is achieved by selecting an injection point relative to the final delay stage, or exit point, of the delay chain. Selection of an injection point is provided by the binary decode of a tap address that activates the injection NAND gate delay stage, allowing the injected signal to propagate from the activated injection point to the exit point of the delay chain.Type: GrantFiled: September 27, 2004Date of Patent: February 6, 2007Assignee: Synopsys, Inc.Inventors: Hansel A. Collins, John E. Linstadt
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Patent number: 7154324Abstract: Delay chain circuitry is provided. The delay chain circuitry has a number of delay chain inverters. Each delay chain inverter is connected in series with a load resistor and has an associated capacitor between its input and ground. The electrodes of each capacitor may be formed from metal separated by non-gate-oxide dielectric to maintain accurate capacitor tolerances. A stable current source such as a bandgap reference current source may apply a current to a sensing resistor. The resulting bias voltage is indicative of changes in resistance due to changes in operating temperature. A temperature compensation circuit may use the bias voltage to produce temperature-compensation control signals. The temperature-compensation control signals are applied to the delay chain inverters to adjust their resistances and compensate for temperature-induced changes in the resistances of the load resistors. This ensures that the delay of the delay chain is independent of operating temperature.Type: GrantFiled: September 7, 2004Date of Patent: December 26, 2006Assignee: Altera CorporationInventors: Simardeep Maangat, Sergey Y. Shumarayev
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Patent number: 7145376Abstract: A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may be asymmetry associated with the physical layout of each individual delay line cell or stage, it is advantageous to cross-connect every x stage of an n-stage delay line. Method, integrated circuit, electronic system and substrate embodiments including the differential solid state delay lines are also disclosed.Type: GrantFiled: September 1, 2004Date of Patent: December 5, 2006Assignee: Micron Technology, Inc.Inventors: Ronnie M. Harrison, Brent Keeth
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Patent number: 7142032Abstract: A delay locked loop includes a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal, and a controller responsive to a timing relationship between the feedback signal and the input signal for adjusting a timing of the output signal. The feedback path includes an adjustable delay circuit for adjusting a timing of the feedback signal.Type: GrantFiled: December 3, 2004Date of Patent: November 28, 2006Inventor: Paul A. Silvestri
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Patent number: 7142031Abstract: To enhance the accuracy of the delay time of the delay device by reducing the change in the power supply voltage for the delay device, and a delay device that delays an incoming transmission signal, comprising: a delay element that operates on a power supply voltage Vdd and a power supply voltage Vss and delays the transmission signal, the voltage Vdd being larger than the voltage Vss; an addition circuit that outputs to an output of the delay element, a predetermined voltage that is larger than the voltage Vss and smaller than the voltage Vdd. This delay element includes a digital circuit that outputs one of output voltages of two possible values in correspondence with an input voltage. Furthermore, the addition circuit outputs a voltage substantially similar to a threshold voltage that said output of the digital circuit inverts from one of the output voltages of two possible values to another thereof.Type: GrantFiled: May 25, 2004Date of Patent: November 28, 2006Assignee: Advantest CorporationInventors: Toshiyuki Okayasu, Masakatsu Suda
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Patent number: 7110718Abstract: RF phase distortion circuits and methods for controllably phase distorting an RF signal based on amplitude of the RF signal. An MOS device is provided having a body of a first conductivity type and at least one region of a second conductivity type in the body, with a conductive layer over at least part of the body and the region of the second conductivity type and insulated therefrom. The MOS device may be coupled into a phase distortion circuit individually or in back-to-back pairs and biased to invert the body under the conductive layer for small signal amplitudes and not for large signal amplitudes, or to not invert the body under the conductive layer for small signal amplitudes and to invert the body under the conductive layer for large signal amplitudes. Various embodiments are disclosed.Type: GrantFiled: June 9, 2003Date of Patent: September 19, 2006Assignee: Maxim Integrated Products, Inc.Inventors: Gregory Krzystof Szczeszynski, Jean-Marc Mourant
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Patent number: 7106117Abstract: A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (?), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.Type: GrantFiled: August 4, 2004Date of Patent: September 12, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Gun-Ok Jung, Jin-Han Kim, Sung-Bae Park, Chul-Woo Kim, Seok-Soo Yoon, Seok-Ryoung Yoon
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Patent number: 7099424Abstract: A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit, a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase relationship between the input signal and a first clock signal. The select circuit is coupled to receive the first control signal from the control circuit and coupled to receive a second control signal. The select circuit is responsive to a select signal to select either the first control signal or the second control signal to be output as a selected control signal. The phase adjust circuit is coupled to receive the selected control signal from the select circuit, the phase adjust circuit being responsive to the selected control signal to adjust the phase of the first clock signal.Type: GrantFiled: August 28, 2001Date of Patent: August 29, 2006Assignee: Rambus Inc.Inventors: Kun-Yung K. Chang, Jason C. Wei, Donald V. Perino