Clock Fault Compensation Or Redundant Clocks Patents (Class 327/292)
  • Patent number: 10396922
    Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Eric Hansen, Denis Beaudoin, Thomas Anton Leyrer
  • Patent number: 10326647
    Abstract: Provided is a network-on-chip (NoC). The NoC includes a plurality of routers configured to receive power through each corresponding power gating switch, and a controller configured to control a power gating switch of each of the plurality of routers based on temperature information provided from each of the plurality of routers and control a driving clock of the plurality of routers. The controller controls the power gating switch to turn off at least one first router by referring to the temperature information and over-scale a clock frequency of at least one turned-on second router.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 18, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kyuseung Han, Woojoo Lee, Jae-Jin Lee, Sung Weon Kang
  • Patent number: 10248083
    Abstract: A reference time generator including a first clock source including a reference synthesizer and cesium atomic clock configured to produce a cesium reference signal and a cesium QOT metric, a second clock source including a reference synthesizer and rubidium atomic clock configured to produce a rubidium reference signal and a rubidium QOT metric, and a circuit for selecting from the clock sources one reference signal based on the best QOT metric.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: April 2, 2019
    Inventor: Benjamin J. Sheahan
  • Patent number: 10199857
    Abstract: Disclosed are a transformer circuit and a method of reducing idling power consumption. The transformer circuit comprises a transformer and an auxiliary winding circuit. The transformer comprises a core, a primary winding, a secondary winding and an auxiliary winding. The auxiliary winding circuit is connected to the auxiliary winding. The auxiliary winding circuit comprises a first power supply circuit and a second power supply circuit. The auxiliary winding comprises a first end, a second end and a tap located between the first end and the second end. The present invention can reduce idling power consumption.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 5, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Wendong Li
  • Patent number: 10172093
    Abstract: Disclosed is a closed-loop clock calibration method, comprising: performing clock calibration according to a calibration factor of an nth calibration period within the nth calibration period, and obtaining a calibration error of the nth calibration period; and according to the calibration error and calibration factor of the nth calibration period, obtaining a calibration factor of an (n+1)th calibration period, n being a positive integer. Also disclosed are a terminal and a computer storage medium.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 1, 2019
    Assignee: Sanechips Technology Co. Ltd.
    Inventors: Yan Li, Junling Zhang
  • Patent number: 10158351
    Abstract: According to one or more embodiments, a skew control circuit for controlling the skew between at least two digital signals is provided. The skew control circuit may include a pulse generator that may generate a pulse with a pulse width, whereby the pulse width of the pulse may depend on a skew between edges of the two digital signals. The skew control circuit may also include a pulse width sensor that may output a pulse width value that represents the pulse width of the generated pulse. The skew control circuit may further include a skew controller that may adjust a delay of the at least one of the digital signals based on a target skew value and the pulse width value.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe
  • Patent number: 10110404
    Abstract: Embodiments of the present disclosure provide a phase calibration method and apparatus, where the apparatus includes a first phase detector and a phase shift control device connected to the first phase detector. The first phase detector is configured to obtain N first signals, compare the N first signals with a reference signal, so as to obtain a phase difference between the reference signal and each first signal in the N first signals, and output the phase difference to the phase shift control device, where N is not less than 2, the N first signals are signals respectively phase-shifted by N phase shifters, and a carrier frequency of the reference signal is the same as a carrier frequency of the N first signals. The phase shift control device is configured to adjust phase shift of the N phase shifters on a one-to-one basis according to the N phase differences.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 23, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jun Ma, Yanxing Luo
  • Patent number: 9985646
    Abstract: Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: May 29, 2018
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventor: Travis C. Mallett
  • Patent number: 9800232
    Abstract: A method for providing a stitchable clock mesh, a dual operation mode system, and a method for providing a master clock stratum are, in turn, provided for a 3D chip stack having two or more strata. The method for providing a stitchable clock mesh includes providing, by at least one clock mesh disposed on each stratum and having multiple sectors, a global clock signal to various chip locations. The method further includes collecting, by mesh data sensors on each stratum, mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The method also includes selectively performing, by joining circuitry, a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: October 24, 2017
  • Patent number: 9766651
    Abstract: The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: September 19, 2017
    Assignee: NXP USA, Inc.
    Inventors: Michael Priel, Dan Kuzmin, Sergey Sofer
  • Patent number: 9741455
    Abstract: A semiconductor memory device includes: a cell array region storing and outputting data selected based on an input address and including a first cell region storing a failure address; an input control signal generator generating a compression signal informing presence of failure cells, and generating an input control signal based on the compression signal; an output control signal generator generating an output control signal in response to the input control signal and a pre-charge signal; a failure address latch storing the input address as the failure address in response to the input control signal, and outputting the failure address based on the output control signal; a failure address mapper mapping the failure address to the data line to store the failure address in the first cell region; and a non-volatile memory device receiving the failure address from the first cell region and programming it in a rupture mode.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 22, 2017
    Assignee: SK Hynix Inc.
    Inventor: Mun-Phil Park
  • Patent number: 9444473
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: September 13, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Alireza Khalili, Mazhareddin Taghivand, Arvind Keerti
  • Patent number: 9413346
    Abstract: A conversion circuit measures individual period lengths for periods of a clock signal. Two of the measured period lengths are selected and compared. The comparison operates to compare a first period length against a threshold set as a function of the second period length. The result of the comparison is indicative of the presence of a clock error. If the threshold is set less than the second period length, the comparison functions to detect a clock glitch. If the threshold is set more than the second period, the comparison functions to detect a loss of clock. The result of the comparison may be used to control further handling of the clock signal by, for example, blocking logic state changes in the clock signal for the length of one period in response to the detection of the clock error.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: August 9, 2016
    Assignee: STMicroelectronics International N.V.
    Inventor: Anand Kumar
  • Patent number: 9350324
    Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsiung Lee, Shi-Hung Wang, Kuang-Kai Yen, Wei-Li Chen, Yung-Hsu Chuang, Shih-Hung Lan, Fan-ming Kuo, Chewn-Pu Jou, Fu-Lung Hsueh
  • Patent number: 9136850
    Abstract: A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: September 15, 2015
    Assignee: Oracle International Corporation
    Inventors: Robert P. Masleid, Anand Dixit
  • Patent number: 9128511
    Abstract: A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: September 8, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hae-Rang Choi, Yong-Ju Kim, Dae-Han Kwon, Jae-Min Jang
  • Patent number: 9030244
    Abstract: An integrated circuit includes a duty cycle detection circuit, a comparator circuit, and a tuning circuit. The duty cycle detection circuit receives a clock signal, such as a system clock signal, and detects the level of duty cycle distortion in the clock signal. The comparator circuit then generates an output based on the level of duty cycle distortion that is detected in the clock signal. The tuning circuit may accordingly adjust the clock signal based on the output generated by the comparator circuit to produce an adjusted clock output signal. As an example, the clock output signal produced by the tuning circuit after the adjustment may have a 50% (or significantly close to 50%) duty cycle.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventors: Mei Luo, Allen K. Chan, Thungoc M. Tran
  • Patent number: 9026835
    Abstract: The present invention relates to a computer system and a clock configuring method. The computer system comprises at least two nodes, wherein each of the at least two nodes includes a selecting module and a CPU, inputs to the selecting module of any node comprise a clock of the node and a clock output from other node, and an output terminal of the selecting module is connected to the CPU and an input terminal of the selecting module of other node; the computer system further comprises a clock controlling module, whose output terminal is connected to a control terminal of the selecting module to control the clocks of the at least two nodes to be the same clock. When clocks of plural nodes are abnormal, the computer system can still normally operate as long as there is a normal clock in the computer system.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: May 5, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Dengben Wu, Yu Zhang, Baifeng Yu
  • Patent number: 9024683
    Abstract: A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 5, 2015
    Assignee: Altera Corporation
    Inventors: David Lewis, Ryan Fung
  • Publication number: 20150116021
    Abstract: A clock generation device measures a frequency ratio between a clock signal CK1 (32.768 kHz+?) and a reference frequency value based on a clock signal CK3 (25 MHz), generates a clock signal CK2 obtained by masking at least one clock pulse of the clock signal CK1 based on the measurement result of the frequency ratio, and controls the measurement interval of the frequency ratio based on the difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results of the frequency ratio.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventor: Yuichi TORIUMI
  • Patent number: 9018999
    Abstract: A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 28, 2015
    Assignee: M&R Printing Equipment, Inc.
    Inventor: Keith R. Falk
  • Patent number: 9013232
    Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 21, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: David Welland, Donald Kerth, Caiyi Wang
  • Patent number: 8970277
    Abstract: An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Koazechi, Tatsufumi Kurokawa
  • Patent number: 8901983
    Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator configured to generate an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of temperature, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Micro Crystal AG
    Inventors: David Ruffieux, Nicola Scolari
  • Patent number: 8896359
    Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator that generates an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of the temperature signal, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Micro Crystal AG
    Inventors: David Ruffieux, Nicola Scolari
  • Patent number: 8884673
    Abstract: A clock trimming apparatus includes an oscillator, a judging unit, a latching unit, and a tracking unit. The oscillator has an input terminal receiving a bias signal and an output terminal generating a clock signal. After a frequency division is performed on the clock signal, the judging unit generates a frequency-divided signal. If the frequency-divided signal matches the reference signal, a pass signal generated by the judging unit is activated. The latching unit is used for generating a trimming completion signal. After the pass signal is activated, the trimming completion signal is activated. The tracking unit is used for counting a pulse number of the reference signal and providing the bias signal to the oscillator according to a trimming code. After the trimming completion signal is activated, the trimming code is stopped being adjusted.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: November 11, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Chi-Yi Shao, Chi-Chang Lin, Yu-Hsiung Tsai
  • Patent number: 8841954
    Abstract: An input signal processing device includes an oscillator circuit, a signal processing circuit, and a control circuit. The oscillator circuit performs an oscillation operation to output a clock signal. The signal processing circuit operates based on the clock signal outputted from the oscillator circuit. The signal processing circuit performs a predetermined process to an input signal when a level of the input signal changes and outputs a signal after the predetermined process. The control circuit instructs the oscillator circuit to start the oscillation operation based on a level change of the input signal. The control circuit instructs the oscillator circuit to stop the oscillation operation when the signal processing circuit finishes the predetermined process.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: September 23, 2014
    Assignee: DENSO CORPORATION
    Inventors: Takuya Honda, Takuya Harada
  • Publication number: 20140253202
    Abstract: The clock circuit of an integrated circuit operates with tolerance of variation in power. A compensation circuit is powered by a supply voltage. The compensation circuit generates a compensated voltage reference, which is compensated for variation in the supply voltage. The compensated voltage reference is compared by comparison circuitry against an output of timing circuitry, to determine timing of the clock signal.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chung-Kuang Chen
  • Patent number: 8816743
    Abstract: An integrated circuit includes a clock circuit that may be used to provide clock signals to multiple input-output circuits. The integrated circuit may also include different clock structures. As an example, one of the clock structures may have multiple clock paths of substantially equal lengths while another clock structure may have a fly-by clock path. The multiple clock paths may be used to convey a subset of the clock signals to the input-output circuits. Similarly, the fly-by clock path may be used to transmit a second subset of the clock signals to the input-output circuits.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: August 26, 2014
    Assignee: Altera Corporation
    Inventors: Sean Shau-Tu Lu, Yan Chong, Kin Hong Au, Khai Nguyen
  • Patent number: 8816744
    Abstract: An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: August 26, 2014
    Assignee: Alchip Technologies, Ltd.
    Inventor: Fang-Ting Chou
  • Patent number: 8812256
    Abstract: An intelligent electronic device incorporates a first port that accepts a time signal from a time server over a network and a second port for receiving a second time signal over a separate network. The intelligent electronic device approximates the amount of error in the second time signal based on calculations of the error in the first time signal.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: August 19, 2014
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Tony J. Lee, Keith C. Henriksen
  • Patent number: 8797082
    Abstract: A system and method for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins. An integrated circuit includes a clock generator that generates a high-speed clock signal. A clock characterizer circuit receives the high-speed clock signal. The clock characterizer generates a corresponding low-speed clock signal. The generated low-speed clock signal is output through a low-speed general-purpose input/output (GPIO) pin for measurement. The generated low-speed clock signal is sent to a sequential element for staging. The staging of the generated low-speed clock signal is done with sequential elements that use a reverse polarity of a clock signal than the polarity used by a previous stage. The high-speed clock signal is used for the staging. The output of each stage is sent to a low-speed GPIO pin for measurement.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Apple Inc.
    Inventors: Ravi K. Ramaswami, Geertjan Joordens
  • Patent number: 8797083
    Abstract: Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M?N equals ±1).
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung Kyu Kim
  • Publication number: 20140210536
    Abstract: In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one Nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency. A digital-to-analog converter (DAC) digitizes an analog input signal based on the filtered clock signal. Attenuating noise in the Nyquist zones reduces jitter of the filtered clock signal, and passing at least one harmonic frequency of the clock signal other than the fundamental frequency limits the degradation of the slew rate of the clock signal. As a result, the filtered clock signal increases the signal-to-noise ratio of the output of the DAC.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: Aicatel-Lucent USA Inc.
    Inventor: Boris A. Kurchuk
  • Publication number: 20140159791
    Abstract: An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicant: Alchip Technologies, Ltd.
    Inventor: Fang-Ting CHOU
  • Patent number: 8692586
    Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 8, 2014
    Assignee: Precision Digital Corporation
    Inventor: Wayne Shumaker
  • Patent number: 8659588
    Abstract: A display substrate includes a base substrate including a display area and a peripheral area, a pixel disposed on the display area, wherein the pixel includes; a pixel transistor connected to a gate line and a data line which cross each other, and a pixel electrode connected to the pixel transistor and the pixel electrode, and a gate driving circuit disposed on the peripheral area, wherein the gate driving circuit outputs a gate signal to the gate line and comprises a plurality of stages, an n-th stage of the gate driving circuit including a plurality of circuit transistors and a boosting capacitor including a first capacitor and a second capacitor, the plurality of circuit transistors and the first capacitor being disposed on a first area and the second capacitor being disposed on a second area of the peripheral area positioned between the first area and the display area.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: February 25, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Bon-Yong Koo
  • Publication number: 20140035647
    Abstract: An embodiment relates to an apparatus and method for enhancing stability of electronic device having a high-accuracy clock. Specifically, there is disclosed a controller for an electronic device, including a control core configured to generate a signal for controlling operation of the electronic device, an internal clock source coupled to the control core and configured to provide a high-speed internal (HSI) clock signal to the control core to act as a drive signal, and at least one timing-sensitive component coupled to an external clock source of the controller and configured to receive a high-speed external (HSE) clock signal generated by an external clock source to act as a drive signal. There is further disclosed a method for driving such kind of controller. According to an embodiment, the high-clock-accuracy requirement and the stability and robustness requirement can be satisfied simultaneously.
    Type: Application
    Filed: July 2, 2013
    Publication date: February 6, 2014
    Inventors: Frank YIN, Zongchao MA, Minlin CHEN
  • Patent number: 8638154
    Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: January 28, 2014
    Assignee: Panasonic Corporation
    Inventors: Katsuyuki Imamura, Kosei Fujisaka
  • Publication number: 20140021997
    Abstract: A method and an apparatus for calibrating a low frequency clock are disclosed. The method includes: calculating a frequency of a low frequency clock in a current low frequency clock calibration; and calculating an average value of low frequency clock frequencies in n clock calibrations before the current calibration, where n is greater than 1 and is an integer; judging whether a difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than a preset threshold for the difference; and if the difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than the preset threshold for the difference, calculating the number of sleep cycles according to the calculated and obtained frequency of the low frequency clock in the current low frequency clock calibration.
    Type: Application
    Filed: September 24, 2013
    Publication date: January 23, 2014
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Dongsheng Liu, Yu Liu
  • Patent number: 8633774
    Abstract: Improvements in and relating to electronic pulse generation or oscillation circuitry based on a signal path exhibiting endless electromagnetic continuity and affording signal phase inversion in setting pulse duration or half-cycles of oscillation within time of signal traverse of said signal path, and having active switching means associated with said signal path to set rise and fall times of each said pulse or said half-cycle of oscillation, including for frequency adjustment by selective inductance and power saving without stopping pulse generation or oscillation.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: January 21, 2014
    Assignee: Analog Devices, Inc.
    Inventor: John Wood
  • Publication number: 20140002147
    Abstract: An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 2, 2014
    Inventors: Tomoki YASUKAWA, Kazuyoshi KAWAI
  • Patent number: 8587357
    Abstract: There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jae-Joon Kim, Yu-Shiang Lin, Liang-Teck Pang, Joel A. Silberman
  • Patent number: 8552900
    Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Haydar Bilhan, Maher Mahmoud Sarraj
  • Patent number: 8531322
    Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: September 10, 2013
    Assignee: Mediatek Singapore Pte. Ltd.
    Inventors: Changhua Cao, Xiaochuan Guo, Yen-Horng Chen, Caiyi Wang
  • Publication number: 20130223152
    Abstract: A clock generator or oscillating circuit is provided to generate a clock signal with high Power Supply Rejection Ratio (PSSR), or a stable clock signal that is resistant to variations in the power supply. The clock generator or oscillating circuit may also adjust the clock period (T) of the clock signal, either or both upwards and downwards, around its central value to compensate fabrication process variations.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 29, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Elpida Memory, Inc.
  • Patent number: 8462034
    Abstract: A synchronizing circuit compatible with a quad switching scheme in a digital-to-analog converter (DAC) to synchronize turning on or off of switches for steering current to a differential output. The synchronizing circuit receives signals from a decoder and synchronizes control signals to the switches by a clock signal. In one embodiment, the synchronizing circuit includes a predictor circuit and a latch circuit. The latch circuit may include four sets of cross-coupled inverters where a set of cross-coupled inverters are activated at a time. By using the synchronizing circuit in conjunction with the quad switching scheme, linearity of analog output from the DAC can be improved and data dependent noise in the analog output can be removed or reduced.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: June 11, 2013
    Assignee: Synopsys, Inc.
    Inventors: Bruno M. S. Santos, Antonio I. R. Leal, Carlos M. A. Azeredo-Leme
  • Patent number: 8433020
    Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: April 30, 2013
    Assignee: Broadcom Corporation
    Inventors: Aaron W. Buchwald, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
  • Publication number: 20130088275
    Abstract: A clock tree power decoupling system includes a pre-decoupling processor that provides a clock tree that supports a critical timing path condition. The clock tree power decoupling system also includes a clock tree power decoupler having a clock tree module that identifies clock buffers in the clock tree corresponding to synchronous start and end points of the critical timing path condition, and a power decoupling module that inserts a decoupling capacitance proximate the clock buffers in the clock tree, wherein the decoupling capacitance is sized to rectify the critical timing path condition. The clock tree power decoupling system additionally includes a post-decoupling processor that provides a power-decoupled clock-inserted database employing the decoupling capacitance. A method of clock tree power decoupling is also provided.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 11, 2013
    Applicant: LSI Corporation
    Inventors: Martin Fennell, Iain Stickland, James G. Monthie
  • Patent number: 8384463
    Abstract: A clock supply circuit includes a clock generating portion configured to generate a clock signal and to change a frequency of the clock signal from a first frequency to a second frequency being higher than the first frequency; and a intermittent clock generating portion configured to receive the clock signal and to mask a clock pulse of the clock signal at a predetermined rate for a predetermined period when the frequency of the clock signal is changed to the second frequency.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: February 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Tokue