Abstract: A full-path circuit delay measurement device for a field-programmable gate array (FPGA) and a measurement method are provided. The measurement device includes two shadow registers and a phase-shifted clock, where the two shadow registers take an output of a measured combinational logic circuit as a clock and sample the phase-shifted clock SCLK as data; the two shadow registers are respectively triggered on rising and falling edges of the output of the measured combinational logic circuit to sample the phase-shifted clock; outputs of the two shadow registers are delivered by an OR gate as an input into a synchronization register; a clock of the synchronization register serves as a clock MCLK of the measured combinational logic circuit; an output of the synchronization register serves as that of the circuit delay measurement device; the phase-shifted clock SCLK and the clock MCLK of the measured combinational logic circuit have the same frequency.

Abstract: A clock multiplexer device includes first and second control circuitries and an output circuitry. The first control circuitry generates a first enable signal and a first signal according to a first clock signal and a first selection signal, and determines whether to output the first signal to be a first output clock signal according to a second selection signal and a second enable signal. The first and the second selection signals have opposite logic values. The second control circuitry generates the second enable signal and a second signal according to a second clock signal and the second selection signal, and determines whether to output the second signal to be a second output clock signal according to the first selection signal and the first enable signal. The output circuitry outputs one of the first output clock signal and the second output clock signal to be a final clock signal.

Abstract: A delay circuit provides a programmable delay and includes an input selector circuit to select between a loop delay output signal and an input signal. A loop delay circuit provides a loop delay to the input signal and supplies the loop delay output signal. The input signal can be recirculated through the loop delay circuit to extend the range of the delay. The input selector circuit selects the feedback signal during recirculation. A variable delay circuit provides a variable delay to the loop delay output signal after the recirculation is complete and supplies a variable delay output signal. An output selector circuit selects the output of the output selector circuit during the recirculation and selects the variable delay output signal after the recirculation is complete to thereby provide a delayed signal with the delay based on the loop delay, the number of loops of recirculation, and the variable delay.

Abstract: The present technology improves synchronization of a slave node with a master node in a network using PTP packets in which the slave node is coupled to the working master node through at least one boundary node. The technology establishes a synchronization communication session between the boundary node and the slave node in which the synchronization communication session is configured to measure a first timing delay from the boundary node to the slave node, and establishes a transparent communication session between the master node and the slave node through the boundary timing node in which the transparent communication session configured to measure a second timing delay from the master node to the slave node. Using the sessions, the technology adjusts a timing delay correction factor according to the first timing delay and the second timing delay, and synchronizes the slave node with the master node according to the correction factor.

Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.

Abstract: Ensuring resiliency to storage device failures in a storage system, including: determining a number of storage device failures within a particular write group that are to be tolerated by the storage system; for a plurality of datasets stored within the storage system, writing each dataset to at least a predetermined number of storage devices within the particular write group, wherein the predetermined number of storage devices is greater than the number of storage device failures within the particular write group that are to be tolerated by the storage system; and responsive to recovering from a system interruption: determining a number of readable storage devices that contain a copy of the dataset; and if the number of readable storage devices that contain a copy of the dataset is not greater than the number of failures that are to be tolerated, writing the dataset to one or more additional storage devices.

Abstract: A method for operating a redundant automation system having a plurality of subsystems, wherein one subsystem of the plurality of subsystems operates as a master and assumes process control and the other subsystem operates as a reserve during redundant operation, where measures are provided by which the availability of the redundant automation system is increased, and where regardless of whether transient errors occur on the subsystem of the plurality of subsystems operating as the master or on the subsystem operating as the reserve, a total failure of the automation system is largely avoided.

Abstract: The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and one or more tunable delay buffers, disposed at junctures of the clock network, that operate to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

Abstract: A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.

Abstract: A system on chip includes a clock generator configured to generate a clock signal, and output the clock signal to a component device external to the system on chip. The system on chip further includes a duty ratio determiner configured to determine a component duty ratio, in response to a response that is received from the component device according to the clock signal, and a duty ratio adjustor configured to adjust a current duty ratio of the clock signal to the component duty ratio, and output the clock signal of which the current duty ratio is adjusted, to the component device.

Abstract: A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.

Abstract: The invention concerns a computing system comprising: an island (102) comprising a group of circuits capable of operating in one of a plurality of operating modes, the island being coupled to an island control circuit (122); and a clock generation circuit (902) supplying a further clock signal to the island control circuit (122) for controlling a change of mode of the island, the clock generation circuit (902) being configured to select one of a plurality of clock frequencies for the further clock signal, the selection being based on the change of operating mode to be applied.

Abstract: Ensuring resiliency to storage device failures in a storage system, including: determining a number of storage device failures within a particular write group that are to be tolerated by the storage system; for a plurality of datasets stored within the storage system, writing each dataset to at least a predetermined number of storage devices within the particular write group, wherein the predetermined number of storage devices is greater than the number of storage device failures within the particular write group that are to be tolerated by the storage system; and responsive to recovering from a system interruption: determining a number of readable storage devices that contain a copy of the dataset; and if the number of readable storage devices that contain a copy of the dataset is not greater than the number of failures that are to be tolerated, writing the dataset to one or more additional storage devices.

Abstract: A buffering circuit includes a first signal input/output unit that generates an output bar signal in response to an input signal, a second signal input/output unit that generates an output signal in response to an input bar signal, and a connection unit that electrically connects and disconnects an output node of the first signal input/output unit and a current sink node of the second signal input/output unit to/from each other in response to a control signal, and electrically connects and disconnects a current sink node of the first signal input/output unit and an output node of the second signal input/output unit to/from each other in response to the control signal.

Abstract: Embodiments of an oscillator and a method of operating an oscillator are disclosed. In an embodiment, an oscillator can include a ring oscillator core, a control circuit, and a timer that coordinates timing of the control circuit to avoid a current resulting from a voltage level associated with an output of the ring oscillator core during a startup and to allow the ring oscillator core to operate with a low startup current and a low operational power.

Abstract: This application discloses a computing system to perform one or more static checks on clock domain crossings in a circuit design to detect combinational logic configured to generate output signals having glitches that cross clock domains in a circuit design. The computing system can identify the combinational logic is configured to generate the output signal based, at least in part, on an input signal and an inversion of the input signal. The computing system can identify conditions that, when satisfied, allow the combinational logic to generate the output signal based, at least in part, on the input signal and the inversion of the input signal, and generate a glitch expression based, at least in part, on the identified conditions. The computing system can determine the combinational logic is configured to generate at least one glitch in the output signal based, at least in part, on the glitch expression.

Abstract: A method of designing a semiconductor device including a memory device, a buffer, and a plurality of head circuits connected to the buffer is disclosed. The method includes generating a layout pattern of a power line of the semiconductor device, generating an improved layout pattern of a pre-routing line that connects the buffer to the head circuits, and generating a layout pattern of signal lines of the semiconductor device. The signal lines include both normal signal lines and signal lines for a central clock of the semiconductor device. A layout of the semiconductor device includes a plurality of layers.

Abstract: An emulator emulating a DUT emulates a clock generator for generating clock signals of the DUT with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock parameter stored for the clock signal and sums the clock parameter with a jitter value randomly selected from the jitter range of the clock signal. When a system fast clock cycle starts, the emulator determines the lowest value from the generated jitter clock values. The emulator outputs an edge on clock signal having the lowest jitter clock value. The emulator generates a new jitter clock value for each clock signal and the process repeats during the next system fast clock cycle.

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Abstract: Provided is a network-on-chip (NoC). The NoC includes a plurality of routers configured to receive power through each corresponding power gating switch, and a controller configured to control a power gating switch of each of the plurality of routers based on temperature information provided from each of the plurality of routers and control a driving clock of the plurality of routers. The controller controls the power gating switch to turn off at least one first router by referring to the temperature information and over-scale a clock frequency of at least one turned-on second router.

Abstract: A reference time generator including a first clock source including a reference synthesizer and cesium atomic clock configured to produce a cesium reference signal and a cesium QOT metric, a second clock source including a reference synthesizer and rubidium atomic clock configured to produce a rubidium reference signal and a rubidium QOT metric, and a circuit for selecting from the clock sources one reference signal based on the best QOT metric.

Abstract: Disclosed are a transformer circuit and a method of reducing idling power consumption. The transformer circuit comprises a transformer and an auxiliary winding circuit. The transformer comprises a core, a primary winding, a secondary winding and an auxiliary winding. The auxiliary winding circuit is connected to the auxiliary winding. The auxiliary winding circuit comprises a first power supply circuit and a second power supply circuit. The auxiliary winding comprises a first end, a second end and a tap located between the first end and the second end. The present invention can reduce idling power consumption.

Abstract: Disclosed is a closed-loop clock calibration method, comprising: performing clock calibration according to a calibration factor of an nth calibration period within the nth calibration period, and obtaining a calibration error of the nth calibration period; and according to the calibration error and calibration factor of the nth calibration period, obtaining a calibration factor of an (n+1)th calibration period, n being a positive integer. Also disclosed are a terminal and a computer storage medium.

Abstract: According to one or more embodiments, a skew control circuit for controlling the skew between at least two digital signals is provided. The skew control circuit may include a pulse generator that may generate a pulse with a pulse width, whereby the pulse width of the pulse may depend on a skew between edges of the two digital signals. The skew control circuit may also include a pulse width sensor that may output a pulse width value that represents the pulse width of the generated pulse. The skew control circuit may further include a skew controller that may adjust a delay of the at least one of the digital signals based on a target skew value and the pulse width value.

Abstract: Embodiments of the present disclosure provide a phase calibration method and apparatus, where the apparatus includes a first phase detector and a phase shift control device connected to the first phase detector. The first phase detector is configured to obtain N first signals, compare the N first signals with a reference signal, so as to obtain a phase difference between the reference signal and each first signal in the N first signals, and output the phase difference to the phase shift control device, where N is not less than 2, the N first signals are signals respectively phase-shifted by N phase shifters, and a carrier frequency of the reference signal is the same as a carrier frequency of the N first signals. The phase shift control device is configured to adjust phase shift of the N phase shifters on a one-to-one basis according to the N phase differences.

Abstract: Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

Abstract: A method for providing a stitchable clock mesh, a dual operation mode system, and a method for providing a master clock stratum are, in turn, provided for a 3D chip stack having two or more strata. The method for providing a stitchable clock mesh includes providing, by at least one clock mesh disposed on each stratum and having multiple sectors, a global clock signal to various chip locations. The method further includes collecting, by mesh data sensors on each stratum, mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The method also includes selectively performing, by joining circuitry, a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.

Abstract: The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit.

Abstract: A semiconductor memory device includes: a cell array region storing and outputting data selected based on an input address and including a first cell region storing a failure address; an input control signal generator generating a compression signal informing presence of failure cells, and generating an input control signal based on the compression signal; an output control signal generator generating an output control signal in response to the input control signal and a pre-charge signal; a failure address latch storing the input address as the failure address in response to the input control signal, and outputting the failure address based on the output control signal; a failure address mapper mapping the failure address to the data line to store the failure address in the first cell region; and a non-volatile memory device receiving the failure address from the first cell region and programming it in a rupture mode.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.

Abstract: A conversion circuit measures individual period lengths for periods of a clock signal. Two of the measured period lengths are selected and compared. The comparison operates to compare a first period length against a threshold set as a function of the second period length. The result of the comparison is indicative of the presence of a clock error. If the threshold is set less than the second period length, the comparison functions to detect a clock glitch. If the threshold is set more than the second period, the comparison functions to detect a loss of clock. The result of the comparison may be used to control further handling of the clock signal by, for example, blocking logic state changes in the clock signal for the length of one period in response to the detection of the clock error.

Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.

Abstract: A phase alignment circuit is disclosed. In one embodiment, the circuit includes a register configured to capture and store, in parallel from a delay unit, a plurality of samples of a first signal, responsive to a change of state of a second signal. The circuit further includes a detection circuit configured to detect a bit position in the register at which a state change of the first signal occurs based on a concurrent evaluation of all samples of the first signal. Selection circuitry in the phase alignment circuit is configured to select an output from a one of a plurality of delay elements of the delay unit based on in the bit position at which the state change was detected. The selection circuitry is configured to output a third signal that is a delayed version of the first signal.

Abstract: A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.

Abstract: An integrated circuit includes a duty cycle detection circuit, a comparator circuit, and a tuning circuit. The duty cycle detection circuit receives a clock signal, such as a system clock signal, and detects the level of duty cycle distortion in the clock signal. The comparator circuit then generates an output based on the level of duty cycle distortion that is detected in the clock signal. The tuning circuit may accordingly adjust the clock signal based on the output generated by the comparator circuit to produce an adjusted clock output signal. As an example, the clock output signal produced by the tuning circuit after the adjustment may have a 50% (or significantly close to 50%) duty cycle.

Abstract: The present invention relates to a computer system and a clock configuring method. The computer system comprises at least two nodes, wherein each of the at least two nodes includes a selecting module and a CPU, inputs to the selecting module of any node comprise a clock of the node and a clock output from other node, and an output terminal of the selecting module is connected to the CPU and an input terminal of the selecting module of other node; the computer system further comprises a clock controlling module, whose output terminal is connected to a control terminal of the selecting module to control the clocks of the at least two nodes to be the same clock. When clocks of plural nodes are abnormal, the computer system can still normally operate as long as there is a normal clock in the computer system.

Abstract: A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.

Abstract: A clock generation device measures a frequency ratio between a clock signal CK1 (32.768 kHz+?) and a reference frequency value based on a clock signal CK3 (25 MHz), generates a clock signal CK2 obtained by masking at least one clock pulse of the clock signal CK1 based on the measurement result of the frequency ratio, and controls the measurement interval of the frequency ratio based on the difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results of the frequency ratio.

Abstract: A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range.

Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator configured to generate an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of temperature, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.

Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator that generates an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of the temperature signal, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.

Abstract: A clock trimming apparatus includes an oscillator, a judging unit, a latching unit, and a tracking unit. The oscillator has an input terminal receiving a bias signal and an output terminal generating a clock signal. After a frequency division is performed on the clock signal, the judging unit generates a frequency-divided signal. If the frequency-divided signal matches the reference signal, a pass signal generated by the judging unit is activated. The latching unit is used for generating a trimming completion signal. After the pass signal is activated, the trimming completion signal is activated. The tracking unit is used for counting a pulse number of the reference signal and providing the bias signal to the oscillator according to a trimming code. After the trimming completion signal is activated, the trimming code is stopped being adjusted.

Abstract: An input signal processing device includes an oscillator circuit, a signal processing circuit, and a control circuit. The oscillator circuit performs an oscillation operation to output a clock signal. The signal processing circuit operates based on the clock signal outputted from the oscillator circuit. The signal processing circuit performs a predetermined process to an input signal when a level of the input signal changes and outputs a signal after the predetermined process. The control circuit instructs the oscillator circuit to start the oscillation operation based on a level change of the input signal. The control circuit instructs the oscillator circuit to stop the oscillation operation when the signal processing circuit finishes the predetermined process.

Abstract: The clock circuit of an integrated circuit operates with tolerance of variation in power. A compensation circuit is powered by a supply voltage. The compensation circuit generates a compensated voltage reference, which is compensated for variation in the supply voltage. The compensated voltage reference is compared by comparison circuitry against an output of timing circuitry, to determine timing of the clock signal.

Abstract: An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases.

Abstract: An integrated circuit includes a clock circuit that may be used to provide clock signals to multiple input-output circuits. The integrated circuit may also include different clock structures. As an example, one of the clock structures may have multiple clock paths of substantially equal lengths while another clock structure may have a fly-by clock path. The multiple clock paths may be used to convey a subset of the clock signals to the input-output circuits. Similarly, the fly-by clock path may be used to transmit a second subset of the clock signals to the input-output circuits.

Abstract: An intelligent electronic device incorporates a first port that accepts a time signal from a time server over a network and a second port for receiving a second time signal over a separate network. The intelligent electronic device approximates the amount of error in the second time signal based on calculations of the error in the first time signal.

Abstract: Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M?N equals ±1).