Abstract: In one embodiment, a clock generation system comprises a redundant clock source (RCS) device for receiving multiple timing signals and for generating at least one clock from the timing signals for distribution to other circuits, and first and second hot-swappable oscillator (HSO) devices that each comprise a base housing and an oscillator unit for generating a timing signal, the base housing including an interconnect for coupling to the oscillator unit, the interconnect providing a first connection for the timing signal and providing a second connection to enable detection of insertion and removal of the oscillator unit, wherein the RCS device switches between timing signals from the first and second HSO devices in response to oscillator unit removal detected through the interconnect and switches between timing signals in response to timing signal failure.

Abstract: A synchronized optical clocking signal is provided to a plurality of optical receivers by providing a layer of a high absorption coefficient material, such as SiGe or Ge, on a front surface of a low absorption coefficient substrate, such as silicon. Diodes are formed in the germanium containing layer for receiving an optical signal and converting the optical signal into an electrical signal. An optical clocking signal is shined on the back surface of the silicon substrate. The light has a wavelength long enough so that it penetrates through the silicon substrate to the germanium containing layer. The wavelength is short enough so that the light is absorbed in the germanium containing layer and converted to the electrical clocking signal used for neighboring devices and circuits. The germanium concentration is graded so that minority carriers are quickly swept across junctions of the diodes and collected.

Abstract: A reference clock oscillating circuit intermittently carries out an oscillating operation on the basis of an oscillation control signal from an oscillation control circuit. A frequency multiplying circuit successively measures the period of a reference clock signal by using a measuring clock signal generated therein during a period for which the reference clock signal is input from the reference clock oscillating circuit, and generates a multiplied clock signal by using the period data thus measured. During a period for which no reference clock signal is input, the multiplied clock signal is generated by using the period data stored in a period data register. The interval of the intermittent oscillating operation is set on the basis of temperature variation of IC or the like.

Abstract: An apparatus for indicating clock skew within integrated circuits (ICs) of a system. There are first and second IC chips operating on respective clocks in the system. According to the invention, the first IC chip operating on a first clock is configured to provide the first clock as output. The second IC chip operating on a second clock has a detection circuit to receive as input the first and the second clocks and to generate a compare signal as output, where the width of the compare signal is proportional to the amount of skew between the input clocks. The second IC chip also includes a sampling circuit coupled to receive the compare signal. With the sampling circuit, an output signal indicative of skew existing between the first and the second clocks can be asserted according to the compare signal.

Abstract: An output circuit device has an output circuit connected between a first power supply line and a second power supply line via a control circuit having at least one isolating transistor. A control voltage held at a constant level is applied to a control electrode of the isolating transistor, and the control voltage is a voltage at a level that works to attenuate high-frequency components contained in a voltage supplied from the first or the second power supply line.

Abstract: The interleaved clock generator generates N interleaved clock signals in response to an input clock signal. The interleaved clock generator comprises an interleaved clock generator of a first type for receiving the input clock signal and for generating M interleaved intermediate clock signals in response to the input clock signal. The interleaved clock generator of the first type includes either a multi-stage serial-delay circuit or a ring counter circuit. The interleaved clock generator additionally comprises M interleaved clock generators of a second type, each of which is each for receiving a respective one of the intermediate clock signals from the clock generator of the first type and for generating N/M of the N interleaved clock signals in response to the respective one of the intermediate clock signals.

Abstract: A clock monitoring apparatus according to the invention including a main clock monitoring portion including a first counter for counting a main clock, issuing a normal operation confirming flag indicating that a normal operation is being carried out when the first counter is overflowed or reaches a previously determined set value, monitoring the normal operation confirming flag by a sub clock, issuing a first main clock stop flag having an output in correspondence with H (high level)/L (low level) of the normal operation confirming flag and a main clock initializing signal for initializing the main clock when the main clock is determined to stop and resetting the first main clock stop flag when the main clock is recovered by receiving the main clock initializing signal, and a sub clock switching control portion including a second counter for counting a signal output produced by calculating a logical sum of the sub clock and the first main clock stop flag at fall of the sub clock at a time point of generating

Abstract: An oscillation detection circuit is constituted by at least one circuitry comprising a first current source for charging a capacitor and a second current source for discharging the capacitor, which are connected in series via a switch controlled to be opened or closed in response to an output signal of an oscillation circuit, wherein the first current source is greater than the second current source in current value. Herein, a signal emerging at a connection point of the first and second current sources is integrated as the switch is repeatedly turned on and off in response to the oscillation signal whose level is periodically changed in an oscillation mode. A Schmitt trigger is arranged to produce a detection signal based on the signal at the connection point between the first and second current sources.

Abstract: A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.

Abstract: A circuit configuration regenerates clock signals. The circuit configuration includes an input differential amplifier, first and second inverters, and an offset compensation circuit. The input differential amplifier generates first and second amplified signals in response to first and second differential input clock signals. The first and second inverters generate a first and a second differential output clock signal. The offset compensation circuit controls the difference between the two output clock signals to zero or to a constant value. As an alternative to or in supplementation of the offset compensation circuit, it is possible to provide a control circuit for driving the two inverters, which shifts the input pulse shapes of the inverters to the optimum switching point of the inverters. The circuit configuration enables a regeneration of clock signals with simultaneous equalization of pulse distortions.

Abstract: An integrated circuit designed to reduce on-chip noise coupling. In one embodiment, circuit (60) includes the following: a circuit transformer (62) capable of converting a noise sensitive input reference clock signal to an output signal having a voltage compatible with a predetermined sink voltage logic level; and a biased receiver network (64) having a PFET current mirror (74) coupled with a NFET current (72), the biased receiver transistor network designed to multiply the transformer signal to offset a mutual coupling loss of the transformer. In at least one alternative embodiment, the input reference clock signal originates at an off-chip clock generator circuit (42) and the output signal from receiver (64) is input to a PLL (44). In another alternative embodiment, the transformer is a monolithic integrated transformer. Another alternative embodiment of the present invention is a method of reducing on-chip noise coupling.

Abstract: A method and a circuit for regenerating a clock signal based on a flip-flop and on two complementary signals at the clock rate, the flip-flop being assembled as a divider by two of a combination of shaping signals each translating a direction, respectively rising or falling, of the edges of one of the complementary signals, and one of said shaping signals being used to reset the flip-flop.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: A clock deciding apparatus generates a plurality of delay clock signals and outputs a clock signal most similar to an outer clock signal to reduce the time used to decide the clock greatly. Also, even if a frequency of the clock signal is changed slightly or phase shift happens due to outer causes, the clock deciding apparatus according to the present invention is able to correspond to the above situations rapidly, and therefore, stable clock signal can be provided to the system.

Abstract: The present invention is related to method and apparatus for clock shrinking that includes a detector, a controller, a switching device, and a buffer. The detector includes one or more counters and detects activation of a trigger. The trigger starts and stops the counters. The controller generates select signals based on output from the counters. The switching device receives vectors and receives the select signals from the controller and outputs the vectors in a sequence based on the select signals. The buffer receives a clock signal and the sequence of vectors and outputs one or more shrunk clock pulses in the clock signal based on the received vectors continuously while the trigger is active. A mode selects the desired shrinking pattern for the clock pulses. The shrinking delays in time or advances in time the rising edge and/or the falling edge of the clock pulses.

Abstract: A reset pulse generator. The CPU generates an oscillating disable signal after initialization. The oscillating circuit is coupled to the CPU to output a sequence of reset pulses to the CPU. The oscillating disable circuit is coupled to the oscillating circuit for disabling the oscillating circuit and initiating normal mode CPU operation when the oscillating disable signal is received.

Abstract: Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.

Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

Abstract: Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: Methods include receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal.

Abstract: Disclosed are novel methods and apparatus for efficiently providing high-resolution single-ended source synchronous receivers. In an embodiment of the present invention, a source-synchronous receiver is disclosed. The receiver includes: a first amplifier to receive a clock signal and a data signal, the first amplifier providing a first output signal; a second amplifier to receive a complementary clock signal and the data signal, the second amplifier providing a second output signal; a third amplifier to receive the clock signal and the data signal, the third amplifier providing a third output signal, the second and third output signals being combined to provide a fifth output; and a fourth amplifier to receive the complementary clock signal and the data signal, the fourth amplifier providing a fourth output signal, the first and fourth output signals being combined to provide a sixth output signal.

Abstract: A clock analyzer includes an input port for receiving a reference clock signal from an external source, a plurality of functionally identical delay cells for delaying the reference clock signal and generating a plurality of delayed clock signals, each delayed clock signal being delayed by a unique number of delay cells, and at least one comparator for comparing the reference clock signal to the plurality of delayed clock signals and choosing a selected clock signal from the plurality of delayed clock signals that at least partially overlaps the reference clock signal.

Abstract: The present invention is related to method and apparatus for clock shrinking that includes a detector, a controller, a switching device, and a buffer. The detector includes one or more counters and detects activation of a trigger. The trigger starts and stops the counters. The controller generates select signals based on output from the counters. The switching device receives vectors and receives the select signals from the controller and outputs the vectors in a sequence based on the select signals. The buffer receives a clock signal and the sequence of vectors and outputs one or more shrunk clock pulses in the clock signal based on the received vectors continuously while the trigger is active. A mode selects the desired shrinking pattern for the clock pulses. The shrinking delays in time or advances in time the rising edge and/or the falling edge of the clock pulses.

Abstract: A novel clock control circuit and method in which phase synchronization with respect to an external clock can be realized without recourse to the external clocks. A clock controlling circuit includes a delay circuit sequence comprised of N stages of units each made up of a first delay circuit 10 and a first interior division circuit 11 for delaying the output signal of the first delay circuit, and a phase difference detection circuit 14 for detecting the clock period and the delay time difference of the delay circuit sequence from the input clock IN and a clock END output by the delay circuit sequence as a phase difference of the two signals. A plural number of second interior division circuits 12, fed with an output signal of the first delay circuit, delays a transition edge of an output signal of the first delay circuit by t2−n×T/N to output the delayed signal.

Abstract: A method for error detection and error correction in the monitoring of measurement values is disclosed, in which the value to be tested is checked for plausibility in an evaluation device, for example a computer, and in the event that an implausibility is identified, the existence of an error is determined. If a further check finds that the error no longer exists, then an error correction takes place. A prerequisite for the error correction, however, is that the range of the value to be monitored in which the error has occurred is also the range in which a current error is no longer occurring. In an expanded method, a differentiation is also made between different errors and an error correction is only possible if it involves the same type of error.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) coupled to the first circuit via one or more path circuits and (ii) configured to present an output signal in response to the one or more first control signals. All of the one or more first control signals may have a preferred edge skew.

Abstract: A clock detect indicator capable of determining the presence of high and low frequency clock signals is provided. The clock detect indicator, which operates independent of a reference clock, has detection circuitry that determines whether a particular clock signal has alternating high-to-low and low-to-high transitions. Based on the determination, the clock detect indicator outputs a transition on a clock detect indication signal. Further, a method for detecting a clock signal in an integrated circuit is provided.

Abstract: Multi-phase clock generators include a master-slave flip flop that generates a second pair of clock signals having a second frequency in response to a first pair of clock signals having a first frequency greater than the second frequency. The master-slave flip-flop includes a master stage that is responsive to a first one of the first pair of clock signals and has a first pair of differential inputs and a first pair of differential outputs. A slave stage is also provided. The slave stage is responsive to a second one of the first pair of clock signals and has a second pair of differential inputs coupled to the first pair of differential outputs and a second pair of differential outputs that are cross-coupled and fed back to the first pair of differential inputs of the master stage.

Abstract: In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.

Abstract: A clock monitoring apparatus according to the invention including a main clock monitoring portion including a first counter for counting a main clock, issuing a normal operation confirming flag indicating that a normal operation is being carried out when the first counter is overflowed or reaches a previously determined set value, monitoring the normal operation confirming flag by a sub clock, issuing a first main clock stop flag having an output in correspondence with H (high level)/L (low level) of the normal operation confirming flag and a main clock initializing signal for initializing the main clock when the main clock is determined to stop and resetting the first main clock stop flag when the main clock is recovered by receiving the main clock initializing signal, and a sub clock switching control portion including a second counter for counting a signal output produced by calculating a logical sum of the sub clock and the first main clock stop flag at fall of the sub clock at a time point of generating

Abstract: A phase adjustment circuit delays an external clock signal to generate an adjusted clock signal. A phase comparator compares phases of the external clock signal and the adjusted clock signal, and outputs a phase adjustment signal for adjusting a delay time of the phase adjustment circuit. A data output circuit outputs read data to a data terminal in synchronization with the adjusted clock signal. A data input circuit receives write data supplied to the data terminal, in synchronization with the adjusted clock signal. When performing input of the write data and output of the read data successively, switching control between the input operation of the write data and the output operation of the read data only has to be completed within one clock cycle. The clock cycle can thus be reduced to the time required for the switching control. Consequently, maximum frequency of the external clock signal can be increased.

Abstract: In a semiconductor integrated circuit having a first circuit which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n) each of which is delayed by a delay time of i×T (T is a constant time) from a reference signal, and a second circuit which carries out signal processing using n clock signals input from the first circuit via n signal wirings, for at least a part of the n signal wirings, the positions of the edges of two clock signals transmitted on the two adjacent signal wirings are separated, as seen on the time base, by more than T in the time.

Abstract: A clock signal generator having a DDS circuit which adds up a frequency word with a particular frequency and generates an output pulse when an overflow occurs. To reduce jitter, a parameter value corresponding to the ideal overflow time of the DDS circuit is determined and an output pulse generating circuit determines, in dependence on the parameter value and using a further, higher frequency, a corrected time for the output pulse and outputs the output pulse at this corrected time.

Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

Abstract: A phase alignment technique includes providing a clock signal to a first clock distribution spine and providing at least one additional clock distribution spine. One PLL (Phase Locked Loop) is provided for each additional clock distribution spine, each PLL having an REF input and an FBK input and an output. The REF input of each PLL is connected to the first clock distribution spine and the FBK input of each PLL is connected to its respective clock distribution spine and the output of each PLL is connected to its respective clock distribution spine to provide a clock signal thereto. Each PLL provides phase alignment between the clock signal on the first clock distribution spine and the clock signal outputted by the PLL to its respective clock distribution spine. The first clock distribution spine and each additional clock distribution spine and its respective PLL may be disposed on an integrated circuit die.

Abstract: An integrated circuit interconnection comprising a transmission line having a low characteristic impedance, and including a first end and a second end. A driver is coupled to the first end of the transmission line, and the transmission line is terminated with a current sense amplifier having an input impedance corresponding to the characteristic impedance of the transmission line. A plurality of components selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements are connected at spaced intervals to the transmission line between the first and second ends.

Abstract: The invention provides an ASIC architecture that incorporates an SSCG module therein and that utilizes both a frequency modulated clock signal and a pure clock signal, where both clock signals are substantially synchronized and where the ASIC architecture minimizes the number of pins and silicon area needed to provide the dual clock signals. Additionally, because the clock signals are derived from the same externally generated clock signal and are received into the ASIC through the same clock input buffer, the clock signals on both branch paths will be substantially synchronized, thereby reducing drift, skew or delay errors in the clock I/O buffers, between the various sections of the integrated circuit and/or between the various components coupled to, or part of the electronic device in which the integrated circuit is a part.

Abstract: A clock detect indicator capable of determining the presence of high and low frequency clock signals is provided. The clock detect indicator, which operates independent of a reference clock, has detection circuitry that determines whether a particular clock signal has alternating high-to-low and low-to-high transitions. Based on the determination, the clock detect indicator outputs a transition on a clock detect indication signal. Further, a method for detecting a clock signal in an integrated circuit is provided.

Abstract: A bifurcation circuit uses dynamic asP* protocol. to exchange data among three or more FIFOs. Each FIFO contains a plurality of places containing data and a plurality of paths that exchange data between neighboring places. The bifurcator circuit generally comprises a control FIFO, two subordinate FIFOs and a bifurcation path coupled to all three FIFOs. The bifurcator circuit further comprises a chain of data latches coupled to all three FIFOs at the bifurcation path. A data value carried in the control FIFO determines which of the subordinate FIFOs exchanges data with the control FIFO. Each place in the FIFOs contains a set reset flip-flop in which the state of each place is held by a single wire and stabilized by a keeper. A single transistor sets or resets the state of the place. The pulse that changes the state of the control flip-flops also makes the data latches momentarily transparent. The bifurcator circuit is generally capable of a branch or join operations.

Abstract: The present invention relates to an adjustable clock skew apparatus and method for generating clock signals, which resolves the drawbacks of costing a user much time and effort to adjust clock skews of all components on a motherboard. In order to accomplish the object, the present invention proposes three operating modes: hardware setup, software setup or a mixture of hardward and software setup. A user just needs to adjust a plurality of exterior switches or to adjust a Basic Input Output System (BIOS) of the motherboard to modify the parameter of clock skew, and clock signals with necessary clock skews will be obtained.

Abstract: An improved DDLL containing a majority filter counter circuit is disclosed. The majority filter counter circuit is located between the phase detector and the shift register of the DDLL. The majority filter counter circuit receives shifting commands from the phase detector and filters the shift commands from reaching the shift register until a predetermined number (e.g., 16) have been received from the phase detector before transmitting a shift command (either shift right or shift left) to the shift register. Once the shift register receives the shift command, the shift register directs the delay line to shift by one tap in either a shift right or a shift left direction depending upon the phase relationship between CLKIn and CLKOut. By waiting for e.g., 16 shift commands, the majority filter counter circuit ensures that a premature shift command is not delivered to the shift register in the case of a noise event.

Abstract: A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation where the gate and metal capacitance in a circuit vary independently across a process window. This is accomplished by regarding the inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the buildup factor to extend Shoji balancing from just one process parameter setting to the entire process window.

Abstract: A clock monitoring circuit is disclosed for detecting that the period of a clock signal has become shorter than a predetermined time interval. The clock monitoring monitoring circuit comprises a first and second flip-flop circuits that are D-type flip-flops, a delay circuit, and a gate circuit. The second flip-flop circuit receives as an input signal the output signal of the first flip-flop circuit. The output signal of the second flip-flop circuit is delayed a fixed time interval by the delay circuit and then supplied as an input signal to the first flip-flop circuit. The delay time of the delay circuit is set to be equal to the previously described predetermined period. The gate circuit receives the output signals of the first and second flip-flop circuits, and provides a signal whose logic level when the period of the received clock signal is the predetermined period differs from that when it is shorter than the predetermined period.

Abstract: A clock monitoring apparatus according to the invention including a main clock monitoring portion including a first counter for counting a main clock, issuing a normal operation confirming flag indicating that a normal operation is being carried out when the first counter is overflowed or reaches a previously determined set value, monitoring the normal operation confirming flag by a sub clock, issuing a first main clock stop flag having an output in correspondence with H (high level)/L (low level) of the normal operation confirming flag and a main clock initializing signal for initializing the main clock when the main clock is determined to stop and resetting the first main clock stop flag when the main clock is recovered by receiving the main clock initializing signal, and a sub clock switching control portion including a second counter for counting a signal output produced by calculating a logical sum of the sub clock and the first main clock stop flag at fall of the sub clock at a time point of generating

Abstract: A first circuit group for generating a dock signal, and a second circuit group for carrying out a transferring operation and a logical processing operation on a signal in accordance with this clock signal are arranged, and operation voltage sources of these circuit groups are made individually settable. Thus, the operation speeds of the first circuit group and the second circuit group are individually adjusted so as to eliminate a problem of an erroneous operation due to a racing through an operation. An erroneous operation due to a racing caused by dock skew can be reliably prevented through an external operation.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.