Abstract: A system and method for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins. An integrated circuit includes a clock generator that generates a high-speed clock signal. A clock characterizer circuit receives the high-speed clock signal. The clock characterizer generates a corresponding low-speed clock signal. The generated low-speed clock signal is output through a low-speed general-purpose input/output (GPIO) pin for measurement. The generated low-speed clock signal is sent to a sequential element for staging. The staging of the generated low-speed clock signal is done with sequential elements that use a reverse polarity of a clock signal than the polarity used by a previous stage. The high-speed clock signal is used for the staging. The output of each stage is sent to a low-speed GPIO pin for measurement.

Abstract: In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one Nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency. A digital-to-analog converter (DAC) digitizes an analog input signal based on the filtered clock signal. Attenuating noise in the Nyquist zones reduces jitter of the filtered clock signal, and passing at least one harmonic frequency of the clock signal other than the fundamental frequency limits the degradation of the slew rate of the clock signal. As a result, the filtered clock signal increases the signal-to-noise ratio of the output of the DAC.

Abstract: An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases.

Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.

Abstract: A display substrate includes a base substrate including a display area and a peripheral area, a pixel disposed on the display area, wherein the pixel includes; a pixel transistor connected to a gate line and a data line which cross each other, and a pixel electrode connected to the pixel transistor and the pixel electrode, and a gate driving circuit disposed on the peripheral area, wherein the gate driving circuit outputs a gate signal to the gate line and comprises a plurality of stages, an n-th stage of the gate driving circuit including a plurality of circuit transistors and a boosting capacitor including a first capacitor and a second capacitor, the plurality of circuit transistors and the first capacitor being disposed on a first area and the second capacitor being disposed on a second area of the peripheral area positioned between the first area and the display area.

Abstract: An embodiment relates to an apparatus and method for enhancing stability of electronic device having a high-accuracy clock. Specifically, there is disclosed a controller for an electronic device, including a control core configured to generate a signal for controlling operation of the electronic device, an internal clock source coupled to the control core and configured to provide a high-speed internal (HSI) clock signal to the control core to act as a drive signal, and at least one timing-sensitive component coupled to an external clock source of the controller and configured to receive a high-speed external (HSE) clock signal generated by an external clock source to act as a drive signal. There is further disclosed a method for driving such kind of controller. According to an embodiment, the high-clock-accuracy requirement and the stability and robustness requirement can be satisfied simultaneously.

Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.

Abstract: A method and an apparatus for calibrating a low frequency clock are disclosed. The method includes: calculating a frequency of a low frequency clock in a current low frequency clock calibration; and calculating an average value of low frequency clock frequencies in n clock calibrations before the current calibration, where n is greater than 1 and is an integer; judging whether a difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than a preset threshold for the difference; and if the difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than the preset threshold for the difference, calculating the number of sleep cycles according to the calculated and obtained frequency of the low frequency clock in the current low frequency clock calibration.

Abstract: Improvements in and relating to electronic pulse generation or oscillation circuitry based on a signal path exhibiting endless electromagnetic continuity and affording signal phase inversion in setting pulse duration or half-cycles of oscillation within time of signal traverse of said signal path, and having active switching means associated with said signal path to set rise and fall times of each said pulse or said half-cycle of oscillation, including for frequency adjustment by selective inductance and power saving without stopping pulse generation or oscillation.

Abstract: An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

Abstract: There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.

Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.

Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

Abstract: A clock generator or oscillating circuit is provided to generate a clock signal with high Power Supply Rejection Ratio (PSSR), or a stable clock signal that is resistant to variations in the power supply. The clock generator or oscillating circuit may also adjust the clock period (T) of the clock signal, either or both upwards and downwards, around its central value to compensate fabrication process variations.

Abstract: A synchronizing circuit compatible with a quad switching scheme in a digital-to-analog converter (DAC) to synchronize turning on or off of switches for steering current to a differential output. The synchronizing circuit receives signals from a decoder and synchronizes control signals to the switches by a clock signal. In one embodiment, the synchronizing circuit includes a predictor circuit and a latch circuit. The latch circuit may include four sets of cross-coupled inverters where a set of cross-coupled inverters are activated at a time. By using the synchronizing circuit in conjunction with the quad switching scheme, linearity of analog output from the DAC can be improved and data dependent noise in the analog output can be removed or reduced.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A clock tree power decoupling system includes a pre-decoupling processor that provides a clock tree that supports a critical timing path condition. The clock tree power decoupling system also includes a clock tree power decoupler having a clock tree module that identifies clock buffers in the clock tree corresponding to synchronous start and end points of the critical timing path condition, and a power decoupling module that inserts a decoupling capacitance proximate the clock buffers in the clock tree, wherein the decoupling capacitance is sized to rectify the critical timing path condition. The clock tree power decoupling system additionally includes a post-decoupling processor that provides a power-decoupled clock-inserted database employing the decoupling capacitance. A method of clock tree power decoupling is also provided.

Abstract: A PLL circuit includes: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count an output clock signal and generate a second counted value; a time measuring circuit to measure an interval between a transition edge of the reference clock signal and a transition edge of the output clock signal to output a third counted value; a phase difference normalizing circuit to multiply the third counted value by a normalizing coefficient to generate a first phase difference; an operating circuit to subtract a value obtained by subtracting the first phase difference from the second counted value from the first counted value to generate a phase difference signal; and an oscillator to change a frequency of the output clock signal based on the phase difference signal.

Abstract: A clock supply circuit includes a clock generating portion configured to generate a clock signal and to change a frequency of the clock signal from a first frequency to a second frequency being higher than the first frequency; and a intermittent clock generating portion configured to receive the clock signal and to mask a clock pulse of the clock signal at a predetermined rate for a predetermined period when the frequency of the clock signal is changed to the second frequency.

Abstract: A data receiver identifies an alignment symbol in a parallel data stream including encoded symbols, generates a bit order indicator indicating a bit order of the alignment symbol identified in the parallel data stream, and generates a symbol stream including the encoded symbols. Further, the data receiver decodes symbols in the symbol stream and generates a bit polarity indicator indicating a bit polarity of the parallel data stream based on the decoded symbols. Additionally, the data receiver generates a formatted symbol stream having a predetermined bit order and a predetermined bit polarity, based on the symbol stream, the bit order indicator, and the bit polarity indicator. In some embodiments, the data receives a serial data stream and generates the parallel data stream by deserializing data in the serial data stream.

Abstract: An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a predetermined range of frequencies. A slave clock synthesizer circuit is provided to track the output clock signal generated by the master clock synthesizer circuit. If the master clock synthesizer circuit fails or generates an invalid output clock signal, the slave clock synthesizer circuit takes over and functions as the master clock synthesizer circuit. In one embodiment a method of fault-tolerant spread spectrum clocking includes generating a first digital data stream; receiving the first digital data stream, a first input reference signal and a first clock signal in a master clock synthesizer circuit; generating an first output clock signal of varying frequency by the master clock synthesizer circuit in response to the first digital data stream and the first clock signal.

Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Abstract: An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic.

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract: A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).

Abstract: A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.

Abstract: A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method for improving timing budgets in a registered dual in-line memory module (RDIMM) may be implemented using the memory device having a register with an integrated delay-locked loop.

Abstract: A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided in the subsequent stage of the first signal processor and performs predetermined signal processing on an output signal from the first signal processor to provide a change to a characteristic value thereof. An amount of change provided to the characteristic value of the signal by the second signal processor is dependent on a power supply voltage. An amount of change provided to the characteristic value of the signal by the first signal processor is configured to be adjustable. A control circuit monitors a power supply voltage supplied to the second signal processor and adjusts in accordance with the power supply voltage the amount of change provided to the characteristic value of the signal by the first signal processor.

Abstract: A semiconductor device includes a first signal generator that generates a plurality of second signals having a delay relative to a first signal and having states that change at different timings. A second signal generator generates a third signal having a delay relative to the first signal. A detector detects a delay amount based on the states of the second signals when a state of the third signal changes. The first signal generator and the second signal generator are different from each other in an amount of change in delay relative to a change in an operating state.

Abstract: A switching device includes a first switch disposed between a power source voltage and an intermediate node, the first switch forming a current path on the basis of an input signal, a second switch disposed between the intermediate node and a ground, the second switch forming a current path on the basis of a voltage of the intermediate node, and a transmission gate receiving the input signal, the transmission gate outputting the input signal on the basis of the voltage of the intermediate node.

Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Abstract: An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).

Abstract: Timing setting data include an arbitrary combination of a set timing signal indicating a positive edge timing and a reset timing signal indicating a negative edge timing. A sort unit sorts n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data. With reference to the sorted timing setting data an open processor detects continuation of the set timing signals or continuation of the reset timing signals, and invalidates one of the continuous set timing signals or one of the continuous reset timing signals. An edge assigning unit sequentially assigns the set/reset timing signals remaining without being invalidated to, among the m variable delay circuits for setting/resetting, the variable delay circuits for setting/resetting in the ascending order of the frequencies of use thereof by then.

Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Abstract: A clock circuit which may include a first clock input for receiving a first clock signal and a second clock input for receiving a second clock signal. A clock calibration unit is connected to the first clock input and the second clock input. The calibration unit may calibrate the second clock signal relative to the first clock signal. The clock calibration unit may have a calibration output for outputting a calibrated clock signal. The clock circuit may include a switch unit connected to the first clock input and the calibration output. The switch unit can select a selected clock signal selected from the first clock signal and the calibrated signal. The switch unit has a switch output for outputting the selected clock signal. A switch control unit is connected to the switch unit for controlling which signal is selected based on a selection criterion and a clock circuit output is connected to the switch unit for outputting the selected clock signal.

Abstract: An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.

Abstract: A system for correcting duty cycle errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signals. A duty cycle error detector has inputs for a pair of amplified clock signals and an output for a duty cycle error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the duty cycle error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the duty cycle error correction signal. Also, a system for correcting cross point errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signal. A cross point error detector has inputs for a pair of amplified clock signals and an output for a cross point error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the cross point error correction signal.

Abstract: Clock data recovery circuitry with a high speed level shifting circuits and methods are disclosed. One embodiment provides clock data recover with a high speed level shifting circuit that uses an input signal to generate two intermediate signals and uses the intermediate signals to generate an output signal such that voltage stress on individual devices within the level shifting circuit is minimized. In one embodiment, the level shifter includes a first driver and second driver coupled in parallel to provide intermediate signals to an output driver. In a particular aspect, individual transistors of the output driver are subject to voltage stresses that are less than the peak-to-peak amplitude of the output signal. In one embodiment, the first driver includes an n-channel metal oxide semiconductor (“NMOS”) cascode circuit, the second driver includes a p-channel metal oxide semiconductor (“PMOS”) cascode circuit, and the output driver includes a complementary metal oxide conductor (“CMOS”) inverter stage.

Abstract: A semiconductor integrated circuit according to the present invention comprises a clock tree circuit for delay-adjusting a clock signal using various delay amounts, and a clock synchronizing circuit to which the delay-adjusted clock signal is supplied. The clock tree circuit comprises a first clock tree cell provided in a poststage of a clock signal introducing terminal, a second clock tree cell provided in a prestage of the clock synchronizing circuit and a poststage of the first clock tree cell, and a clock ramification point provided in a prestage of the second clock tree cell. The clock synchronizing circuit comprises a first clock synchronizing circuit to which the clock signal delay-adjusted by the second clock tree cell and thereafter outputted from the clock tree circuit is supplied, and a second clock synchronizing circuit to which the clock signal outputted from the clock tree circuit at the clock ramification point is supplied.

Abstract: The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, and further all local clock pulses are synchronized with respect to frequency in an assured manner, and a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, and the system clock pulse automatically achieves the maximum possible frequency. The invention further relates to such a hardware system.

Abstract: An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.

Abstract: An object is to provide a clock generating circuit that can suppress variation of an oscillation frequency from the clock generating circuit, which is due to a change in the output voltage according to a discharging characteristic of the battery, and effectively utilize the remaining power of the battery. A structure includes an output voltage detecting circuit for detecting an output voltage from a battery; a frequency-division number determining circuit for determining the number of frequency-division by a value of the output voltage detected by the output voltage detecting circuit; an oscillation circuit for outputting a reference clock signal depending on the output voltage; a counter circuit for counting a number of waves of the reference clock signal that depends on the number of frequency-division; and a frequency-dividing circuit that frequency-divides the reference clock signal depending on the number of waves counted by the counter circuit.

Abstract: A programmable logic device (PLD) includes a signal distribution network, separate from the high-quality, low-skew clock distribution networks of the PLD, for distributing, from peripheral input/output regions of the PLD, clock-type signals. The signal distribution network includes a central periphery clock bus, located near a group of peripheral input/output regions, for conducting clock-type signals from those regions onto a clock spine of the PLD. The clock spine may be dedicated to the signal distribution network, or may be part of a high-quality, low-skew clock distribution network covering all or part of the PLD. The signal distribution network allows greater skew than such high-quality, low-skew clock distribution networks, but nevertheless is of higher quality, and allows less skew, than the general programmable interconnect and routing resources.

Abstract: A method and device are disclosed. In one embodiment the method includes driving a first clock domain reference signal on a first clock tree and driving a second clock domain reference signal on a second clock tree. The first tree routes the first signal from a PLL to a first clock domain drop off circuit and the second tree routes the second signal from the PLL to a second clock domain drop off circuit. A jitter produced from the second tree is less than a jitter produced from the first tree. The method continues by detecting any phase misalignment between the first signal and the second signal. The method also causes the first signal to be delayed so that it aligns with the second signal.

Abstract: Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

Abstract: Disclosed herein is a clock supplying apparatus for supplying a clock to a digital circuit, including: a differential clock driver; a first clock line along which a first clock of a positive phase from the clock driver propagates; a second clock line along which a second clock of a reverse phase from the clock driver propagates; and a parallel resonance circuit of an inductor and a capacitor. The inductor of the parallel resonance circuit is connected at a first end to the first clock line and at a second end to the second clock line. The capacitor of the parallel resonance circuit is connected at a first electrode to the first clock line and at a second electrode to the second clock line.

Abstract: In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

Abstract: Disclosed is a clock adjusting circuit comprising a phase shifter that receives a clock signal and variably shifts, based on a control signal, respective timing phases of a rising edge and a falling edge of the clock signal; and a control circuit that supplies the control signal to the phase shifter circuit before each edge is output; wherein the clock signal, in which at least one of a period, a duty ratio, jitter and skew/delay of the input clock signal is changed over an arbitrary number of clock cycles, is output.

Abstract: A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.

Abstract: A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.