Abstract: A single reliable clock source that can be shared by all cards in a multiple card assembly. The clock delivers synchronous clock signals, so that there is no longer a need to provide crystal oscillators on each card, instead, a single non-interruptable clock source is shared by all cards. The clock is an Application Specific Integrated Circuit (ASIC), where single sources of failure have been removed by using redundant connection and majority logic. Thus, a plurality of selection means are redundantly coupled to receivers for selecting an oscillator signal to provide to phase-locked oscillators. Further, majority logic voters are redundantly coupled to the phase-locked oscillator to provide a clock output signal reflecting the state of the majority of the phase-locked oscillator signals. The clock includes three independent crystal oscillators, one clock ASIC, the wire and connectors which deliver the signals, and a 2.times.3 AND-OR majority logic on the receiving card.

Abstract: A signal disconnection detection apparatus includes a first counter, a first comparator, and a detector. The first counter is reset by a pulse signal received every predetermined period of a clock signal, and counts a clock signal transmitted together with data. The first comparator compares a count value of the first counter with a set value larger than the number of clock signals included in one period of the pulse signal, and stops an operation of the first counter when the count value of the first counter exceeds the set value. The detector detects that the count value of the first counter does not continuously change within a predetermined period of time to output a signal disconnection detection signal of at least one of the clock signal and the pulse signal.

Abstract: For clock delay compensation and duty control of a phase-locked loop in a decoder of a video signal receiving system, phases of two input clocks received into a phase comparative detector are compared to divide a reference clock from an oscillator of the phase comparative detector for obtaining a resultant phase error output in a divider in accordance with the result of the phase comparison, a duty ratio of the output clock therefrom is controlled in a duty controller to allow the phase comparative detector to be utilized free from the duty ratio of the clock, and a clock delay compensator performs correction of clock delay compensation of the system operated at high speed in the synchronized phase-locked loop, thereby controlling a duty ratio of a signal divided in the divider when determining accuracy, frequency and stabilization in the duty controller, and correcting an error in delay time by adding the clock delay compensator.

Abstract: A clock signal generation arrangement for generating clocking signals for use in a fault-tolerant computer system generates a timing signal in response to a common clock signal. The clock signal generation arrangement comprises a system clock signal generator and a clock signal recovery circuit interconnected by a plurality of clock signal transfer lines. The system clock signal generator generates, in response to a common clock signal, a plurality of system clock signals preferably of uniform frequency and phase for transmission over a like plurality of clock signal transfer lines. The clock signal recovery circuit receives the system clock signals from the clock signal transfer lines and generates a unitary timing signal. The clock signal recovery circuit includes a voting circuit, a latch circuit and a latch control circuit. The voting circuit generates a voted clock signal having signal transitions that are generally aligned with transitions of a majority of the system clock signals.

Abstract: To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.

Abstract: The objects are to speed up the operation of an integrated circuit device having a sequential circuit and increase margin of phase synchronization for performing data processing of time sequential circuit. The phase-locked circuit (57) is provided in the integrated circuit (50), and the clock signal (CK7) which is inputted from the outside through the phase-locked circuit is supplied to the sequential circuit (52). The data outputted from the sequential circuit (52) is fed back from the output end of the buffer (Bu56) to the phase-locked circuit (57). In the phase-locked circuit (57), the clock signal (CK7) inputted through the buffer (Bu50) and the output data of the sequential circuit (52) are compared in phase and the phase of the clock signal outputted to the sequential circuit (52) is adjusted so that the phases thereof agree. The output data (DO7) outputted from the sequential circuit (52) is not delayed with respect clock signal (CK7).

Abstract: A duplexed clock switching apparatus of the present invention includes two oscillators constantly working for outputting clock signals, wherein a phase of the stand-by clock signal is kept synchronized to the phase of the clock signal selected from the output signal of the oscillator to be supplied to the apparatus. Each of the duplexed clock switching apparatus of the present invention includes a clock signal generator for generating clock signals of a predetermined frequency independently; a clock selector for receiving clock signals generated by all clock signal generators and selecting one of them; a phase synchronization circuit for synchronizing a phase of a clock signal generated by the clock signal generator to the phase of the selected clock signal; and a clock switching circuit for switching an outputted clock signal to the selected clock signal. With reference to the phase synchronization circuit, it is desirable to include a phase-locked-loop (PLL) circuit.

Abstract: Clock signals of the same phase are formed even when signal delays occur in clock signals transmitted on a clock line. In a clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, the clock line is bent midway into a pair of clock lines, and a center phase signal generating means generates a clock signal having a phase which is in the center of two clock signals of differing phase obtained from arbitrary points on the pair of clock lines which are at equal distances from the point at which the clock line is bent over. By using pairs of clock signals of differing phases taken at equal distances from the bend over point, three clock signals all having equal phase are obtained.

Abstract: In a semiconductor device including a clock driver which provides clock signals, a plurality of electronic elements which are operable in timed relation to the clock signals, are provided a plurality of circumferentially-wired, lattice-shaped wiring blocks to which the electronic elements are connected and each of which has a center portion, and an interconnecting wiring pattern connected to the center portion. The interconnecting wiring pattern connects the clock driver with the center portion of each circumferentially-wired, lattice-shaped wiring block so that a distance between the clock driver and each center portion is substantially equal to one another in the center portions.

Abstract: A self-timed synchronous clock pulse circuit (100) is disclosed that includes a pulse pull-down circuit (102) pulling a first pulse node (104) to ground upon receiving the rising edge of an external clock. A pulse generator (108) responsive to a high-to-low transition at the first pulse node (104) generates a second clock pulse. A pulse pull-up circuit (110) is responsive to the second edge of the second clock pulse and pulls the first pulse node (104) to the positive power supply. An initialization circuit (112) is provided to prevent a lock-up condition upon power-up by sampling the logic level of the first pulse node (104) on the rising edge of the external clock. The logic value is essentially held throughout the remainder of the clock cycle by gating the value into a second latch during the second portion of an external clock cycle.

Abstract: An integrated circuit (IC) includes circuitry for generating a clock signal during both a normal mode of operation and a test mode of operation. During the normal mode, an input clock signal is delayed via a skew corrector. In test mode, an input test clock signal bypasses the skew corrector via a clock signal source selector. The clock signal source selector is controlled automatically by a mode detector that responds to the input clock signals to determine the mode of operation of the IC.

Abstract: A CMOS integrated circuit microcomputer is switchable under software control between high speed, high power operation and low speed, low power operation. The microcomputer includes asynchronous fast and slow clock oscillators. A synchronizing circuit coupled to the fast and slow clock oscillators receives a clock selection signal, and in response thereto produces a clock enable signal. The clock enable signal has the same frequency as and is synchronized with either the fast clock signal or the slow clock signal, depending on the state of the clock selection signal. The clock enable signal is input to gating circuitry that gates either the fast or the slow clock signal to provide a selectable speed clock signal to be used elsewhere in the microcomputer.

Abstract: A device checks the skew between two clock signals among a plurality of clock signals having the same frequency. The two clock signals of each possible pair of clock signals respectively enable two successive flip-flops that are initially set at distinct states. The whole set of the flip-flops is connected in a looped shift register configuration. An alarm signal is provided by an Exclusive-OR gate receiving the outputs of two successive flip-flops of the shift register.

Abstract: A method and apparatus are provided for translating small voltage continuous signals into large full supply signals to generate a clock signal. At least one oscillator input signal is applied to a first amplifier stage for generating an amplified voltage output signal. A first inverter is coupled to the first amplifier stage. A second inverter is coupled to the first inverter. An AC coupling capacitor couples the amplified voltage output signal to the first inverter input, and a feedback resistor is connected between the output and input of the first inverter.

Abstract: An integrated circuit for deskewing and adjusting a delay of a synthesized waveform. The synthesized waveform is initially produced by a digital-to-time domain converter which is coupled to a synchronous delay line and a pattern ROM through a shifter and a pattern register. The synchronous delay line generates a plurality of taps in response to a reference signal. Each one of the taps has a unit delay and is coupled to the digital-to-time domain converter. The integrated circuit which deskews and adjusts the delay of the synthesized waveform comprises a microdelay calibration circuit, a deskew control circuit, and a delay interpolation circuit. The microdelay calibration circuit is coupled to the taps of the synchronous delay line and the deskew control circuit. The deskew control circuit is coupled the shifter to perform coarse deskew operations. The deskew control circuit is further coupled to the delay interpolation circuit to perform fine deskew operations.

Abstract: In a sampling phase controlling apparatus for controlling a phase of a clock signal supplied to a transmission system including a discriminating circuit for discriminating a received signal and an equalizer for removing an intersymbol interference component from the received signal, a first phase control circuit is provided to control the phase of the clock signal in accordance with accumulated intersymbol interference components, and a second phase control circuit is provided to control the phase of the clock signal in accordance with the accumulated intersymbol interference components and a differential value thereof. One of the first and second phase control circuits is selected by a selector circuit.

Abstract: If, in a clock generator according to the present invention, the first clock is switched to the second clock with a lower frequency, the frequency count circuit counts the frequency of the second clock with using the first clock as reference. The clock switching control means judges whether the frequency of the second clock is stable or not based on the count result from said frequency count circuit and, if it is stable, switches the switching means for clock switching to the second clock.

Abstract: An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance wit

Abstract: A method and an arrangement minimizes skew in digital synchronous systems. The arrangement includes N number of driver circuits, each of which has a P number of buffer units, of which each has an input and an output. Each driver circuit has a delay of .delta..sub.1, .delta..sub.2, .delta..sub.3, .delta..sub.4 . . . .delta..sub.N. Of these buffer units, N-1 buffer units are reserved while the inputs of the remaining buffer units P-(N-1) are connected mutually in parallel. The reserved buffer units are used as follows. A signal deriving from a signal source is applied to an input of a first buffer unit in each of the N-number of driver circuits, where the signal is subjected to a delay. The one-time delayed signal from a driver circuit is then delayed once, and only once, in the reserved buffer units of each of the remaining driver circuits. This procedure is repeated for each of the once-delayed signals on the outputs of the first buffer unit in each of the remaining N-1 driver circuits.

Abstract: A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.

Abstract: A distributed clock generation scheme is provided for a microprocessor that reduces electromagnetic interference and power consumption. Rather than using a single, large internal clock generator circuit that meets the drive requirements of the remaining circuitry upon the microprocessor die, a plurality of smaller clock generator circuits are distributed across the die, each generating clock signals to drive a separate portion of the microprocessor circuitry. Each of the distributed clock generator circuits may be load matched with respect to the others to minimize the skew between clock signals, and each receives a synchronized timing signal provided from a master timing distribution circuit. As a result of the distributed clock generation scheme, the amount of current and the rate at which current is sourced or sunk at a given location on the semiconductor die is reduced, thereby reducing electromagnetic interference and increasing the signal to noise ratio.

Abstract: An optical clock distribution method and apparatus is disclosed that minimizes clock skew in the distribution of clock signals to logic assemblies in a computer system. The logic assemblies convert the optical signals into equivalent electrical signals.

Abstract: An oscillator which inhibits unwanted oscillations and requires a comparatively small power supply voltage is described. The oscillator includes an amplifier transistor 110 (220), an output current of which flows into the emitter of a load transistor 120 (220) via a load signal path. The amplifier stage acquires a bandpass characteristic by a passive capacitive bootstrap signal transfer from this signal path to the base of the load transistor. The oscillator thus preferably oscillates within the passband of the amplifier stage. The amplifier stage has a comparatively large gain within the passband even without a load resistor in the load signal path. Such a load resistor would cause a voltage drop and, hence, increase the required power supply voltage.

Abstract: A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. An external command signal may be provided to the microprocessor to initiate a test operation in which the variable delay units are tested for possible defects. During the test operation, a control unit selects the multiplexers such that the four delay units are electrically separated from one another. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time.

Abstract: A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency, have a different phase, and are shifted one clock period apart. The clocking signals are transferred over a first set of signal lines of equal length and impedance to computing systems components that are connected to a synchronous bus. Each component includes at least one clock repeater chip to convert the clocking signals (e.g., change these signals to a 5 volt CMOS level) to a different format. The converted clocking signals are then transferred over a second set of signal lines of equal length and impedance to the gate arrays. The gate arrays includes direct drive circuitry that receives the converted clocking signals and transmits these signals to internal driver circuitry. These signals are transferred over low skew lines.

Abstract: The ability to stop a clock in a CMOS peripheral device or other CMOS IC, and reliably restart it based on an asynchronous event, provides the basis for considerable power savings. In a computer system 20 an interface component 10 has a clock restart circuit 100. The restart circuit 100 includes a series of D-type CMOS flip-flops (110, 112, 118) that are initially set in their zero state. A logic OR gate 120 receives the microprocessor clock and the complimentary output of the last flip-flop to provide a reliable, restarted clock signal for the interface component 10 and its peripherals 26.

Abstract: A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop.

Abstract: A circuit monitors electronic devices which require continuous clocking for non-destructive operation. The circuit samples a repetitive signal, such as a clock, from a device of interest (DOI). If, for whatever reason, the clock signal becomes absent, the circuit responds by deactivating the DOI. If the clock revives or becomes intermittent the circuit will not reactivate the DOI. The circuit will reactivate the DOI only upon application of an explicit reset signal. The circuit is all digital and therefore technology independent, and provides for precise control of the deactivation response time.

Abstract: A clocking disable and enable circuit is provided having an input for receiving a clocking signal and another input for receiving a disable/enable signal. The disable and enable circuit provides a clocking disable/enable output from the circuit which is synchronized with the clocking signal during times in which the disable/enable signal is not activated. At times during which the disable/enable signal is activated, the clocking disable/enable signal transitions after at least a one half clocking period to a steady state value (either high or low voltage level). After the disable/enable signal becomes inactive again, clocking disable/enable signal automatically resynchronizes to the clocking signal. The clocking disable and enable circuit herein is well suited for providing glitch-free transition between a clocking state and a steady state to a synchronized digital or analog circuit which depends upon clocking synchronization for its operation.

Abstract: A system and method for a computer based system for enabling data phase clock corrections. Basing these corrections primarily on errors that cause consistent phase shift errors while reducing the effect of random data phase errors. An improved phase-locked loop (PLL) is used where multiple data bits are examined simultaneously, allowing us to examine "apparent future" and "apparent late" data. The average phase adjustment to the data window is calculated based upon the examined data bits.

Abstract: A clock signal distribution network in a microprocessor of a computer system for distributing a global clock signal to a plurality of units of the microprocessor includes a clock generator for generating a first clock signal with an input delay. A phase locked loop circuit generates a controllable delay to the first clock signal to become the global clock signal. A clock driver drives the global clock signal to the plurality of units. An electrical connector includes a plurality of connection lines for coupling the global clock signal to the plurality of units. A length equalizer equalizes the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time. Each of the plurality of units includes an area buffer for standardizing its input load to the clock driver. A dummy buffer introduces the input delay of the clock generator to the global clock signal.

Abstract: There is disclosed herein a method and apparatus for distributing high speed clock signals on an integrated circuit while eliminating clock skew. The invention is particularly useful in field programmable gate arrays where the signal paths are defined by the user after the integrated circuit leaves the place of manufacture and enables field programmable gate arrays to operate at clock speeds in excess of 200 MHz, a speed not previously attainable. Clock skew is eliminated by generating differential clock signals at each of four corners of the array from master differential clock signal delivered simultaneously to each of the four corners. The differential clock signals generated at each corner have ramps the rise time of which slightly exceeds the propagation delay of a clock signal traversing the array.

Abstract: In a semiconductor integrated circuit apparatus, a first logic circuit processes a clock signal inputted through an external clock input terminal, and each of a plurality of second logic circuits processes the clock signal outputted from the first logic circuit, and outputs the processed clock signal to a plurality of flip-flops. In the semiconductor integrated circuit apparatus, an inner clock signal line is provided for electrically connecting the plurality of second logic circuits with the plurality of flip-flops, wherein the inner clock signal line is formed in a ring shape in the periphery of the semiconductor integrated circuit apparatus so that the plurality of flip-flops are located within the inner clock signal line, thereby reducing the clock skews therebetween in the semiconductor integrated circuit.

Abstract: A circuit eliminates clock skew between an off-chip clock signal originating off an integrated circuit and an on-chip clock signal produced on the integrated circuit. The on-chip clock signal is produced by phase delaying the off-chip clock signal. A first delay path and a second delay path each phase delay the off-chip clock signal an identical amount. A multiplexor selects one of the delay paths to produce the on-chip clock signal. When phase delay through the first delay path is adjusted, the multiplexor selects the second delay path. When phase delay through the second delay path is adjusted, the selection means selects the first delay path. A phase detector and filter circuit generates control signals which indicate, based on phase difference between the off-chip clock signal and the on-chip clock signal, when to increase and when to decrease the phase delay through the delay paths.

Abstract: A clock signal supply system is disclosed for a semiconductor device with a semiconductor chip and a wiring substrate connected in flip-chip fashion and an optical waveguide interposed in the space between electrode members, in which the mutual arrangement of the electrical interconnection and the optical waveguide interconnection on the wiring substrate is not affected and can be used separately from each other for different applications, thereby improving the throughput of the interconnections as a whole.

Abstract: Each data sending high speed circuit generating and sending a stream of data slices and a stream of clock pulses is provided with a sync pulse generation circuit for synchronously generating and sending an accompanying stream of periodic sync pulses. The various streams of data slices, clock pulses, and periodic sync pulses incur varying amount of delays as they travel from the data sending high speed circuits to a data acquisition circuit. The data acquisition high speed circuit is provided with a plurality of circular buffer chains of appropriate length for independently buffering the skewed data slices until all corresponding data slices have been received and buffered, and then concurrently reading the buffered corresponding data slices out of the circular buffer chains.

Abstract: A circuit and method for providing phase synchronization between an ECL output signal and a TTL or CMOS output signal has been provided. The circuit includes phase locked loops (20, 24) to make the difference of delays through an ECL-TTL/CMOS translation path with that of a straight ECL path irrelevant. As a result, in order to achieve phase synchronization between an ECL signal and a TTL/CMOS signal, one only needs to match the propagation delay of a delay component (22) to that of a TTL/CMOS-ECL translator (26) as opposed to a delay component and an ECL-TTL/CMOS translator.

Abstract: A clock control apparatus having a basic period clock and a plurality of clocks with different phases from the basic period clock by t/N period, is used with an information processing unit.

Abstract: One embodiment of the present invention is a digital circuit (10) for providing glitch-free data in an asynchronous environment, the circuit comprising: an input circuit (11) for accepting data; combinational logic circuitry (12) for accepting the data from the input circuit (11 ) and manipulating the data to provide output data, wherein a delay in data flow occurs while the combinational logic manipulates the data; and an output circuit (14) for accepting the output data at a predetermined period after the receipt of data by the input circuit. Preferably, the predetermined period is at least as long as the delay in data flow.

Abstract: An integrated circuit incorporating at least a SRAM that includes memory, a data-out shift register, an ABIST data compression circuit, a fail address register and an array clock generator (ACG), the ACG comprising a clock chopper that comprises a first AND gate having an inherent delay DEL1, a first input for receiving a D clock signal, a second input for receiving the D signal inverted by an invertor having an inherent delay DEL2, and an output that generates an ungated LSSSD C clock signal; and a second AND gate having an inherent delay DEL4, a first input connected to the output of an inverter having an inherent delay DEL3, the inverter is coupled to the invertor having the delay DEL2, a second input is controlled by the D clock signal and an output for generating LSSD clock signals B and S.

Abstract: Providing low-skew clock signals to a Field Programmable Gate Array (FPGA) chip normally requires devoting a certain number of bondpads to that purpose. However, that limits the number of clocks that may be applied, and may also limit which bondpads can be used for that purpose. In the present invention, any input/output bondpad may be used to supply a low-skew clock, or other global type signal, to one or more of the Programmable Function Units (PFUs). This is accomplished by using a criss-crossed grid of parallel conductor groups. Any of the conductors may be supplied by a clock from a bondpad or alternatively driven directly from a PFU, thereby allowing the distribution of internally-generated clocks. To facilitate programmable interconnects between the horizontal and vertical conductors, the outer conductor in a group crosses over the others at defined intervals, to thereby become the inner conductor.

Abstract: A selectable timing delay system which provides for delaying an input signal a specified length of time within a specified tolerance wherein the range and resolution of the selectable timing delay system are so specified that the selected delay within the selected tolerance is obtainable regardless of the relative speed of the integrated circuit chips used in forming the selectable timing delay system.

Abstract: A skew fault detection system for detecting clock skew between two clock phases utilizes a plurality of skew fault detection circuits each of which employs two D-type flip-flops. The clock terminals of both of these flip-flops are connected to one of the clock phases, and one of the clock phases is coupled to a delay circuit on the D input terminal of one of the flip-flops. The delay circuit is adjustable to correspond to the clock pulse delay that is inherent in the circuit that is being monitored to control the maximum amount of clock skew that is allowable before this flip-flop will set. If the clock skew exceeds this allowable time, a skew fault occurs and the flip-flop will set. The circuit compares the initiation of one clock phase against the initiation of the other clock phase and to determine when the initiation of one clock phase occurs earlier than the initiation of the other clock pulse by a time duration that exceeds a predetermined allowable skew amount of time.

Abstract: The power consumption of an electrical device can be optimised by altering the clock frequency of circuits (MCU, 1-3) in the device which are controlled by a clock signal. The state and need for processing power of the circuits (MCU, 1-3) or blocks (21-23) in the circuits (2) is supervised, and the clock frequency of the circuit (MCU, 1-3) or block (21-23) in the device is changed according to the need for processing power. The appropriate clock frequency is selected from one of a plurality of clock signals (clk(1) . . . clk(n)), input to a selection circuit which is then coupled to the output of the selection circuit for use as the clock for the circuit.

Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

Abstract: A fault-tolerant clock having at least four channels, each providing its own clock output, and yet all clock output signals of all functioning channels being coherent with one another. One clock functions as a master with the other clocks of the remaining channels slaving themselves to that one clock. In view of a failure of the master, another clock reigns as the master clock to slave the remaining clocks. If the next master clock fails, then still another clock becomes a master to slave the remaining clock or clocks. The clocks are independently powered such that complete failure of one clock, including its power, does not necessarily prevent the other clocks from providing coherent outputs.

Abstract: A digital clock reconstruction circuit comprising a first flip flop, a programmable delay chain, and a first assembly of gates is provided to digitally compensate an entering digital clock's skew for a high speed digital circuit by digitally reconstructing the entering clock. The reconstructed clock will also provide the minimum amount of high and low time in a period required by the components of the high speed circuit. Additionally, at least one measurement or comparison circuit is provided for measuring the frequencies of the reconstructed clock under various delay settings of the programmable delay chain to calibrate the digital clock reconstruction circuit. Under the calibration process of the present invention, the delay setting is determined iteratively, starting from an initial setting and varying the delay setting in a predetermined manner.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A controller for a clock generator. The controller of the present invention enables a clock signal to the internal clocking mechanism of a device. The controller of the present invention includes a detector and a timer. The detector has two input sense levels, such that it is capable of detecting a clock signal at two separate levels, the first level being larger than the second. Initially, the detector only detects when the clock signal is at a level greater than or equal to the larger of the levels. When this occurs, the timer begins counting. When the clock signal has been at or above the greater level for a predetermined time as determined by the timer, the detector enables the clock signal to go to the internal clocking mechanism. Thereafter, the detector only senses when the clock signal falls below the second level. Thus, the detector enables the clock signal to go to the internal clocking mechanism while the level of the clock signal is above the second level.

Abstract: A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a clock distribution network of an integrated circuit (IC) chip associated with a clock repeater chip. Circuits of the remote delay regulator are contained on the repeater chip and on the associated IC chip. Delay measurement of the remote IC clock distribution network is provided by sensing the clock signal at the beginning of the network using a BEFORE sense tap and at the end of the network using an AFTER sense tap. The BEFORE and AFTER sense taps are routed to a signal generation circuit on the repeater chip where measurement signals are generated that define the beginning and end of a measurement cycle.