Abstract: The present invention encompasses the use of multiple feedback paths in a clock source for an integrated circuit device to maintain phase lock to an external clock. It is further contemplated by the present invention that feedback paths are provided from the internal clock distribution path and from a matching path that approximates the delay of the clock distribution path. The matching path may comprise a delay locked loop. Feedback from the clock distribution path is used in normal operation and feedback from the matching path is used when the internal clock distribution path is disabled. The clock source of the present invention also may implement power management functions.

Abstract: Buffer trees are detected in an inputted logic circuit and sets of driver gates included in the respective buffer trees are made (in Step 102). A set of gates relating to more than one buffer tree, i.e., a group of gates to be optimized, is detected (in Step 103). The groups of gates to be optimized are classified according to the symmetry in logic structure (in Step 104). Each group of gates to be optimized is extracted (in Step 105). The buffer trees are restructured so as to be in a symmetrical relation with each other (In Step 106). Through the above process, the buffer trees are optimized to be in a symmetrical relation of logic structure. Thus, the method of optimizing the logic circuit to ensure reduction in routing area, total length of interconnections and delay of the layout after placement is accomplished.

Abstract: A delay/digital converting circuit in a phase compensating apparatus detects a time period after a measurement start signal that is an internal clock signal is input, until a measurement end signal that is an output signal of a digital/delay converting circuit is input, and outputs the resultant data as digital data to a digital/delay converting circuit. The delay/digital converting circuit outputs the difference between the cycle of an external clock signal and an amount of delay time of a clock distributing circuit as the digital data. The digital/delay converting circuit delays the external clock signal according to the digital data. An internal clock signal which is the output signal of the digital/delay converting circuit that has been delayed by the clock distributing circuit is a signal that has a delay for one cycle of the external clock signal. Thus, the phase of the external clock signal accords with the phase of the internal clock signal.

Abstract: A programmable logic device (PLD) which includes a phase comparator in addition to the conventional configurable logic circuitry normally present in the PLD. The configurable logic circuitry of the PLD includes a clock distribution circuit which is configured to route a clock signal VCO.sub.OUT generated by a voltage controlled oscillator (VCO) throughout the PLD as a distributed clock signal (DIST.sub.-- CLK). The DIST.sub.-- CLK signal is used to clock the output registers which route data values out of the PLD. The DIST.sub.-- CLK signal is also provided to the phase comparator. The phase comparator is also coupled to receive a clock signal CLK.sub.IN from an external device. In response, the phase comparator generates an error signal which is representative of the phase difference between the CLK.sub.IN and DIST.sub.-- CLK signals. This error signal is provided to a loop filter. In response, the loop filter generates a control signal, which in turn, controls the frequency of the VCO.sub.

Abstract: A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock.

Abstract: A clock for digital devices. Ordinarily, when multiple digital devices are clocked by a common clock, the clock signals frequently arrive at the digital devices at different times, due to propagation delays. The devices are thus not clocked synchronously. Under the invention, the multiple devices are connected to a common transmission line. A standing wave is generated on the transmission line, and the periodic collapse of the standing wave is used to clock the devices. Synchronous clocking to within about 1.0 nano-seconds has been attained, in a transmission line about ten feet long, wherein a clock signal ordinarily takes about 15 nanoseconds to travel from one end to the other.

Abstract: There is provided an adjustment circuit which delays a first and a second signal by a desired delay. After the first and the second signal are inputted to the adjustment circuit via a first and a second signal line, respectively, the first and the second signal are exchanged and are inputted via the second and the first signal line, respectively. A detection circuit receives the first and the second signal from the adjustment circuit, and detects the phase differences of these signals, before and after the exchange. The holding circuit holds a first phase difference detected by the detection circuit before the exchange, and holds a second phase difference detected by the detection circuit after the exchange. When the holding circuit holds the first and the second phase difference, a comparison circuit compares these phase differences. A counter counts in accordance with the comparison results of the comparison circuit, and sets the desired delay of the adjustment circuit.

Abstract: A system clock signal switching device capable of switching outputs from a plurality of clock signal generation systems i order to ensure the continuous supply of a stable system clock signal. An oscillation circuit A generates a clock signal CK1 as an ordinary system clock signal while an oscillation circuit B generates a clock signal CK2 as another separate clock signal, such as the time-count clock signal. The output lines of these circuits are connected with the input terminals of a multiplexer. An output clock signal monitor circuit checks the clock signal CK1 from the oscillation circuit A, wherein input terminals of the monitor are connected with the output lines to attain the operational clock signals for its monitoring operation. A monitor flag from the monitor circuit is supplied to a switching signal input terminal of the multiplexer via a line.

Abstract: The oscillation-stop detecting device accurately detects the stopping of a clock signal due to various causes. The voltage detecting circuit detects when a clock signal output from the clock signal oscillator remains at a high, a low or an intermediate level, and outputs a clock voltage detection signal. The oscillation-stop detecting circuit outputs a detection signal in response to the voltage detection signal.

Abstract: A clock generator serves to generate a stable frequency system clock for a clock-controlled electronic device. To ensure that the system clock causes only little electromagnetic interference to nearby electronic equipment, the system clock is modulated with respect to a reference clock by means of a phase modulator controlled by a random signal source which is noise colored by means of a weighting device.

Abstract: The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input path circuit also includes one or more decode units each having a number of logic gate cells such as NAND gate cells or NOR gate cells. Circuitry is provided within the logic gates for reducing timing delay differences between propagation of multiple bit binary signals, such as address signals, through the logic gates. In an exemplary NAND gate described herein, reduction in timing delay differences is achieved by positioning an additional PMOS device along a current path between a power source and an output path otherwise including only a pair of parallel PMOS devices.

Abstract: An integrated circuit (10) provides analog and digital circuitry on a common substrate (12). A first digital circuit (14) operates in combination with an analog circuit (18) to perform a useful function. A second duplicate digital circuit (26) is disposed adjacent to the first digital circuit and operates out-of-phase with respect to the first digital circuit. The second duplicate digital circuit introduces voltage spikes equal and opposite to the voltage spikes introduced into the substrate by the first digital circuit. The equal and opposite voltage spikes tend to cancel and thereby minimize cross-talk between the digital and analog circuits. A guard ring (16,28) surrounds each of the first and second digital circuits and the analog circuit to reduce voltage spikes into the substrates. By minimizing cross-talk, the analog circuit operates without interference from the digital circuits.

Abstract: A method and a completely integrable circuit arrangement are proposed for recovery of a timing signal from a data stream. Two groups of phase regulators are supplied with a locally existing reference timing signal, preferably in each case one of mutually complementary reference timing signals. One phase regulator in each case, which has assumed a state within its operating range, is selected to provide the recovered timing signal, while a phase regulator which is currently not selected is kept in the state within its operating range which is diametrically opposite to the state of the currently selected phase regulator. On reaching the limit of the operating range of the currently selected phase regulator, a changeover is made to the phase regulator which has been kept ready until this point.

Abstract: A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.

Abstract: A dual delay-locked loop is employed to reduce timing skew between two signals, such as localized clock signals, which are both derived from a common input signal. Individually controllable variable delay circuits are used in the signal paths between the common input signal and each of the two signals to nominally create additional delay between the common input signal and each of the two signals. The two signals are compared, the timing skew therebetween is indicated, and the variable delay circuits are each adjusted to reduce the skew between the two signals. The common input signal is not used as a reference signal for the comparison. Rather, the two variably-delayed signals themselves are compared, and both variable delays are adjusted to reduce the skew.

Abstract: An apparatus for use in a synchronous transmission system (STS) efficiently tests N clock signals provided from a device incorporated in the STS, wherein N is a positive integer larger than 1 and the N clock signals are represented by a first predetermined clock frequency. The N clock signals are first received by a counting device in response to a reset signal issued by a system controller in the STS to produce an error reference signal for each of the N received clock signals. And then, at a clock generator, a reference clock signal represented by a second predetermined clock frequency is provided. A first set of error detection signals for the N clock signals is derived based on the N clock signals, the reference clock signal and the error reference signals at a first error detection device. Thereafter, at a second error detection device, a second set of error detection signals for the N clock signals is obtained based on the reference clock signal and the error reference signals.

Abstract: An external clock signal CK is input to a buffer, which generates an internal clock signal CLK having a skew of D1 with respect to the external clock signal CK. The internal clock signal is input first to a delay circuit which has a delay time A, then to a delay array which provides a delay time D2, and finally to a delay circuit which has a delay time of D2. The delay circuit generates a corrected internal clock signal CK' which is synchronous with the external clock signal CK. The delay array is composed of delay units, each having a state-holding section. The state-holding section of any delay unit that has passed a forward pulse is set in a predetermined state. Once its state-holding section is set in the predetermined state, the delay unit provides a correct delay time of 2.times..DELTA..

Abstract: The present invention provides an analog biased pre-driver and pad as well as a duty cycle adjustment cell prior to the pre-driver and pad. The pre-driver and pad may operate in either a 3 volt mode, a 5 volt mode or any voltage in between depending only on the power supply voltage present. No production configuration or post-production configuration is required. The present invention utilizes a special bias circuit to reduce the Vcc, temperature and other processing variations. A duty cycle cell produces a range of duty cycles when the circuit is operating between a 3 volt and 5 volt range.

Abstract: The present invention is directed to a method and apparatus for synchronizing one or more data signal lines of a data bus to multiple clocks, and for guaranteeing the validity of the synchronized values. Exemplary embodiments avoid the need to eliminate delays between the asynchronous clocks. Thus, exemplary embodiments of the present invention can be used for reliably synchronizing the in-pointer and out-pointer of a first-in first-out memory.

Abstract: A phase adjusting circuit includes a circuit for providing an internal clock signal in synchronization with a reference clock signal, a delay circuit for delaying the internal clock signal for a predetermined delay time and an adjusting section for adjusting a phase difference between a phase of the reference clock signal and a phase of the internal clock signal delayed for the predetermined delay time.

Abstract: A low-skew single-ended to differential signal converter includes a conventional single-ended to differential converter that drives a pair of output driver circuits. Each driver circuit is formed from a pair of transfer gates that receive a supply voltage or a reference voltage, respectively. The transfer gates transfer only a portion of the supply or reference voltage in response to the inverted signal from the conventional converter. The portion of the transferred voltage is insufficient to trigger output members in the output drivers and the output voltages from the drivers do not transition in response to the noninverted signal. The inverted signal causes the outputs of the transfer gates to transition fully, triggering the respective output inverters. Because the inverted signal causes transitions of both of the output signals, skew of the output signals is reduced relative to skew of the inverted and noninverted signals.

Abstract: A clock circuit for providing an integrated circuit with a high accuracy, crystal oscillator clock which interfaces to an "off-chip" crystal to provide a high accuracy clock signal while an internal, low power oscillator provides a low power clock source. Either clock may be selected to drive a programmable processor under program control. When high accuracy and stability are required, the crystal oscillator may be chosen as the processor clock, and when lower power is desired, the low power oscillator may be chosen as the processor clock while the high accuracy clock is disabled. The high accuracy oscillator is used to clock a first timer circuit, while the low power oscillator is used to clock a second timer circuit. The second timer circuit output, in turn, is synchronized to the processor clock so that the programmable processor can utilize the second timer circuit even when the processor clock is asynchronous to the second timer circuit.

Abstract: A deviation of a clock rate of the timepiece clock signal is determined relative to a reference clock rate of a reference clock signal (CR) which is either issued while the mobile unit is switched on or is contained in a received signal. The reference clock rate is higher than the clock rate of the timepiece clock signal. A count number (N) is calculated based on the deviation of the clock rate of the timepiece clock signal. The clock signal is generated such that the clock pulses the clock signal are successively issued each time the clock pulses of the timepiece clock signal counted up to the count number.

Abstract: A frequency departure detecting circuit permits flexibly modify a detecting condition of frequency departure. A working reference clock is counted for a given period. On the basis of uniformity between bits of given number of upper bits of the counted value, large magnitude of frequency departure of repeated frequency of the reference clock from a frequency that should be is judged. Also, through comparison of given number of lower bits of the counted value and externally set detecting value, departure of the repeated frequency of the reference clock from the frequency that should be, is judged. When the counted value reaches a predetermined value, free running condition of the counter is judged to stop counting operation. When judgement is made that the repeated frequency of the reference clock is departed from the frequency that should be, the working reference clock is replaced with a back-up reference clock in response to an alarm.

Abstract: A clock signal generator for an IC tester has a clock control circuit provided between a jitter reduction circuit and an IC device to be tested. The clock control circuit inhibit the clock signal from reaching the IC device for a time period required for a clock signal changes to a new frequency. The clock signal generator includes: a timing generator for generating clock signals and timing signals based on a test program, a pattern generator which receives the timing signals from the timing generator for producing test pattern signals to be supplied to the IC device based on the test program, a jitter reduction circuit for receiving a clock signal from the timing generator and for reducing a jitter of the clock signal, and a clock control circuit for inhibiting the clock signal from the jitter reduction circuit from being supplied to the IC device for a inhibit period determined by the test program when a frequency of the clock signal has been changed.

Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.

Abstract: A clock distributing apparatus which can decrease the clock skew and can prevent the swing of a signal on clock transmission lines and can achieve a low power consumption, a lower noise of a power supply, and a high speed operation, wherein converts clock signals adjusted in phase to the same phase as a reference clock by a PLL circuit to current signals by voltage/current converters and sends the current signals to clock transmission lines and converts the current signals transmitted to the clock transmission lines to voltage signals by current/voltage converters and sends the voltage signals to circuit blocks of an integrated circuit.

Abstract: A clock signal generated by a clock signal generating circuit is supplied to a frequency-dividing circuit formed using a D-type flip-flop circuit, being supplied to a controlled circuit after being divided down. Furthermore, the clock signal generated by the clock signal generating circuit is supplied to the controlled circuit by way of a through circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity of the frequency-dividing circuit, the through circuit being formed using the D-type flip-flop circuit in the same way as the frequency-dividing circuit.

Abstract: A method and apparatus for clocking latches in a system having both pulse latches and two-phase latches includes a clock generating circuit for generating a local clock signal based on a global clock signal and also includes a pulse generating circuit for generating a pulse signal based on the global clock signal. A clock signal path transfers the local clock signal from the clock generating circuit to both a first portion and a second portion of the two-phase latch. Similarly, a pulse signal path transfers the pulse signal from the pulse generating circuit to the pulse latch. According to one embodiment, the pulse generating circuit and the clock generating circuit have paths of equal delay, thereby causing a rising edge of the local clock signal to occur at the same time as a rising edge of the pulse signal.

Abstract: A single-phase clocking scheme for use in a VLSI chip having a plurality of localized logic blocks implemented thereon is presented. The present invention includes a first level global clock buffer for receiving an external global clock and producing a first level global clock. A plurality of second level clock buffers, one corresponding to each localized logic block, receive the first level global clock via protected equal length lines, and each produce a respective second level global clock. Each of the localized logic blocks include a plurality of third level clock buffers, wherein each third level clock buffer receives the second level global clock of its respective localized logic block, and each produces a third level local clock. The third level local clock buffers within each localized logic block generate different clocking schemes from each of the other third level local clock buffers contained within the same localized block.

Abstract: A method and circuit in which one of at least two asynchronous constant frequency input clock signals is selected for being used as an output clock signal by use of a separate selection signal for providing redundancy for an asynchronous clock signal.

Abstract: A clock generator circuit for clock controlled electronic devices, which causes minimal electromagnetic interference in adjacent electronic equipment. The clock generator circuit includes a clock source for generating a basic clock signal having a predetermined frequency. The basic clock signal defines a reference clock signal having a period T. A phase modulator coupled to the clock source for producing a system clock signal by delaying the basic clock signal. A signal source coupled to the phase modulator, which controls the phase modulator so that the system clock signal is delayed with respect to the reference clock signal by a time period less than half of the period T of the reference clock signal.

Abstract: Clock skew is minimized in an ASIC by grid-partitioning the IC chip into a number of preferably equal sized regions. An on-chip clock or buffer unit provides a clock signal to be distributed to buffers and clocked loads also on the IC. Equal length metal interconnect traces are formed in a preferably "H"-shaped configuration such that the termini and the center of the traces overlie buffer regions that will receive the distributed clock signal. Metallization interconnect paths are dictated by placement of joiner cells. By making each metal interconnect trace equal in overall length and in layer sub-lengths (if multiple metallization layers are present), clock skew along the interconnect traces is minimized macroscopically. A series of prioritized net lists is generated, defining interconnect paths to each region. A buffer is centrally located within each region, and is surrounded by a ring containing clocked loads to be coupled to the clock signal.

Abstract: Disclosed is a radio apparatus in a synchronous digital hierarchy (SDH) network in which a radio transmission line having a plurality of radio lines is installed between optical transmission lines each having a plurality of optical lines. The radio apparatus includes a plurality of channel boards, each of which is provided between an optical line and a radio line, for transmitting an optical signal received from the optical line to the radio line and transmitting a signal received from the radio line to the optical line, a setting unit, which is provided to be shared by each channel board, for attaching, per channel board, priority value to clock contained in each signal sent in via an optical line and a radio line, and for setting, per channel board, whether the clock of each priority value is to be outputted or not, and an equipment-clock decision unit for deciding a clock shared by the entire apparatus.

Abstract: A pulse generator for use in generating pulses at different locations within a circuit has a first circuit 501 for a time dependent operation after receipt of a first input pulse and a second circuit 502 for carrying out a time dependent operation after receipt of a second input pulse after the first input pulse. A third circuit 503 is responsive to each of the first and second circuits 501,502 reaching respective predetermined conditions so that an output pulse is produced by the third circuit 503 at a time dependent on the average durations of operation of the first and second circuits 501 and 502.

Abstract: A modular bus permitting single or double termination is described. The bus includes a terminated motherboard data net for communicating data signals between a master and one or more motherboard devices. A socket is used for coupling the data signals between the motherboard data net and a terminated module data net of a removable module. The module data net communicates the data signals between the master and one or more module devices. The data signal swing and level of reflection of the data signals are substantially independent of the presence of the module.

Abstract: A clock distribution network for distributing a clock signal across a VLSI chip. A H-tree is combined with an x-y grid to allow buffering of the clock signal, while minimizing clock skew across the chip. The H-tree distributes a plurality of repower buffer levels above a final repower buffering level. The output of the final level are coupled by the x-y grid to minimizes clock skew caused by the chip and by local loading variations in the circuits.

Abstract: A clock signal failure detection and recovery circuit for use in a system utilizing multiple, redundant clock signals. Multiple clock source circuits generate a clock signal and a periodic sync pulse, which in turn are manipulated to produce a clock signal present pulse and a periodic clock pulse. The periodic clock pulse associated with one clock signal will clock the circuitry which monitors a clock signal present pulse associated with a different clock signal. In this way, the absence of a clock signal present pulse can still be clocked into the monitoring circuitry when that particular clock signal has failed. Each clock signal present pulse is compared to at least two other clock signal present pulses, and upon recognition of a predetermined number of inconsistencies between the compared clock signal present pulses, a clock signal error signal will be issued.

Abstract: A clock system includes internal monitor circuitry such that the clock system is testable in a secure environment. In particular, the clock system includes a plurality of separately enableable clock generator circuit modules. Each of the clock generator circuit modules generates a separate clock signal when enabled. Combining circuitry receives the separate clock signals from those clock generator circuit modules which are enabled and derives a derived clock signal therefrom. Monitor circuitry receives the derived clock signal, detects whether there are transitions in the derived clock signal, and provides a monitor indication of a result of the detection. Thus, the clock system can be tested without providing the separate clock signals outside the clock system. Preferably, the clock system also includes a programmable clock control register that holds clock control data, the clock control data determining which of the clock generator circuit modules are enabled.

Abstract: A clock system (2) for providing a system clock signal at a clock output (4) for use by a processing unit comprises a first oscillator circuit (6) which is enabled in response to a wake up signal provided by the processing unit to provide a first clock signal (RINGO CLOCK) at an output, and a second oscillator circuit (8) comprising a PLL (14) and an oscillator (16). The second oscillator (8) circuit provides a second clock signal (PLL CLOCK) and a lock signal (LOCKED) at first and second outputs respectively when the PLL is locked.

Abstract: A clocking system for complex electronic devices is created in an hierarchial manner whereby the master clock pulse is provided to a plurality of digital pulse aligners which in turn provide phase aligned clock signals at the field replaceable unit level to either a slave clock or a digital phase aligner. The slave clock or the digital phase aligner at the field replaceable unit level in turn provides an aligned clock pulse to a timing node on respective chips. A third level of the hierarchy provides similarly aligned pulses to individual using-circuits on the chips of the system. The digital phase aligner, aligning the output pulse at the timing node of the next level with the reference pulses being provided to the digital phase aligner at each level, insures that the timing pulses arriving at the utilizing circuits are synchronously aligned with clock pulses of the master clock.

Abstract: A clock regulator that provides two controlled timing references per clock cycle on a single clock distribution. The regulator includes two phase detectors and phase aligner pairs to independently regulate both rising and falling edges of the clock distribution, rather than regulating only one edge as conventional regulators.

Abstract: A fail-safe clock generator which has particular utility in implantable cardiac defibrillators includes a crystal oscillator for generating a crystal clock signal, a back-up circuit, and a one-shot generator. The back-up circuit includes a low frequency oscillator for generating a low frequency clock signal having a frequency less than that of the crystal clock signal, and an overspeed/underspeed detector responsive to the low frequency clock signal for detecting the frequency of the crystal clock signal during each period of the low frequency clock signal, and for generating a back-up mode control signal in response to detection of either an overspeed or underspeed failure mode over a plurality of consecutive periods of the low frequency clock signal.

Abstract: A processor (PR) is connected to the output of a phase comparator (PK) in a phase-locked loop. The processor (PR) calculates the phase shift of an input signal (f.sub.E) within an observation time span (for example, .DELTA.t=0-T) from the phase difference (.DELTA..phi.) at the output of the phase comparator (PK) and the parameters of the phase-locked loop (FT1, PK, FI, VCO, FT2).

Abstract: A system in which line reflections in a clock distribution network are cancelled by providing the clock distribution network with a branching point and suitably arranging recipient devices with respect to the branching point to provide for clock pulse reflection cancellation and attenuation. Moreover, the system can be arranged so that clock pulse reflections are not received as pulses which are discrete from legitimate clock pulses. The system also provides capability for reducing electromagnetic interference.

Abstract: A modular bus permitting single or double termination is described. The bus includes a terminated motherboard data net for communicating data signals between a master and one or more motherboard devices. A socket is used for coupling the data signals between the motherboard data net and a terminated module data net of a removable module. The module data net communicates the data signals between the master and one or more module devices. The data signal swing and level of reflection of the data signals are substantially independent of the presence of the module.

Abstract: A semiconductor integrated circuit has a test circuit capable of accurately measuring the clock skew of a clock signal in an LSI. The test circuit includes first and second flip flops driven by the clock signal in a maximum clock skew to receive a test signal. The test signal is supplied through a test signal input pin to data inputs of the first and second flip flops in the same signal delay. The outputs of the first and second flip flops are connected to the inputs of an exclusive OR gate. The test signal is varied stepwise by an amount at a time corresponding to the resolution of an LSI tester, and the output of the exclusive OR gate is detected to measure the clock skew in the clock signal.

Abstract: A signal is supplied to a number of synchronizing circuits with a small skew. A signal supply circuit (400a) includes four driver circuits (1a), (401), (402) and (403). The driver circuit (1a) receives an input signal which is supplied to synchronizing circuits (301) to (332). An output of the driver circuit (1a) is supplied to the left-hand side edge of a first wire (5). The driver circuits (401), (403) and (402) are disposed at the left-hand side edge, the right-hand side edge and a center of first wire (5), respectively, so that outputs from the driver circuits (401), (403) and (402) are supplied to a second wire (6). Input terminals of the synchronizing circuits (301) to (332) are each connected to the second wire (6). The driver circuits (401), (402) and (403), i.e., second signal transmitting elements, start transmission in this order, and therefore, a transition of the signal becomes abrupt at the driver circuits (401), (402) and (403) in this order.

Abstract: A system clock signal is delivered to a plurality of load devices by means of a common loop filter and delay line and a plurality of phase detectors and charge pumps each associated to a different load. The delay line provides a plurality of substantially identical phase corrected clock signals, each clock signal being coupled to the associated load device via an associated conductor member. In one embodiment, each conductor member comprises a loop consisting of a pair of conductors having substantially identical path lengths. The phase adjusted clock signals on the proximal end of the outbound conductor are coupled back as a first feedback signal to one input of the associated phase detector. Another feedback signal comprises the clock signal returned from the device node along the second conductor of the pair. A third input to the phase detector is the system input clock signal, which is also coupled to a reference input of the delay line.

Abstract: A system clock signal is distributed to a plurality of load devices via a plurality of phase correction circuits each coupled to a different pair of a plurality of pairs of clock signal conductors. The proximal end of one of the pair of conductors is coupled to the output of a delay line and receives a phase corrected version of the system clock signal. The distal end of this conductor is coupled to the load device at a clock connection node. The clock connection node is fed back to the phase correction circuit via the other one of the pair of conductors. The first and second conductors have equal path lengths in order to provide equal propagation delays. The clock signal fed back from the load device node is coupled as a feedback input to a three input phase detector circuit. The other two inputs are the clock signal output from the phase correction circuit delay line and the system clock signal.