With Common Output Patents (Class 327/294)
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Patent number: 7999593Abstract: An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).Type: GrantFiled: December 6, 2006Date of Patent: August 16, 2011Assignee: NXP B.V.Inventors: Robert Spindler, Roland Brandl, Ewald Bergler
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Patent number: 7996705Abstract: A multilevel input interface device connected to a signal bus including one or more data lines that transmit an M-level signal and a clock line that transmits a transmission clock signal indicating the timings of reading level information for the M-level signal, includes: a threshold value generation unit that produces a plurality of voltage outputs as a plurality of variable comparison reference signals according to the level-varying supply voltage; a level detection unit that compares, in synchronization with the transmission clock signal, the M-value level signal with the variable comparison reference signals and generates a logic output corresponding to an instantaneous value of the M-level signal; and a logic circuit unit that converts the logic output to a data signal.Type: GrantFiled: December 13, 2007Date of Patent: August 9, 2011Assignee: Seiko Epson CorporationInventor: Kesatoshi Takeuchi
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Patent number: 7977995Abstract: The described embodiments provide a circuit that can be configured as a pulse generator or as an oscillator. The circuit includes a pulse generator circuit and a test circuit that is coupled to the pulse generator circuit. In the described embodiments, an disable signal is coupled to the test circuit. When the disable signal is asserted, the test circuit is disabled, and the pulse generator circuit outputs pulses of a predetermined duration. In contrast, when the disable signal is deasserted, the test circuit is enabled, and the pulse generator circuit outputs an oscillating signal.Type: GrantFiled: June 30, 2009Date of Patent: July 12, 2011Assignee: Oracle America, Inc.Inventors: Robert P. Masleid, Anand Dixit
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Publication number: 20110163785Abstract: An apparatus for interleaved phase shift clock synchronization includes a master clock generator and at least one slave clock generator. The master clock generator provides a ramp signal or reset signal for each slave clock generator to generate a clock synchronized with the clock of the master clock generator, and the master and slave clock generators have different reference voltages for generating clocks. Therefore, the clocks generated will be synchronized and interleaved phase with each other.Type: ApplicationFiled: December 23, 2010Publication date: July 7, 2011Applicant: RICHTEK TECHNOLOGY CORP.Inventors: ISAAC Y. CHEN, AN-TUNG CHEN
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Patent number: 7973584Abstract: Timing setting data include an arbitrary combination of a set timing signal indicating a positive edge timing and a reset timing signal indicating a negative edge timing. A sort unit sorts n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data. With reference to the sorted timing setting data an open processor detects continuation of the set timing signals or continuation of the reset timing signals, and invalidates one of the continuous set timing signals or one of the continuous reset timing signals. An edge assigning unit sequentially assigns the set/reset timing signals remaining without being invalidated to, among the m variable delay circuits for setting/resetting, the variable delay circuits for setting/resetting in the ascending order of the frequencies of use thereof by then.Type: GrantFiled: September 4, 2008Date of Patent: July 5, 2011Assignee: Advantest CorporationInventors: Nobuei Washizu, Hiroaki Tateno
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Patent number: 7956664Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.Type: GrantFiled: December 3, 2007Date of Patent: June 7, 2011Assignee: The Regents of the University of MichiganInventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
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Patent number: 7936199Abstract: A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state.Type: GrantFiled: February 6, 2008Date of Patent: May 3, 2011Assignee: Micron Technology, Inc.Inventors: Michael V. Ho, Tyler J. Gomm, Scott E. Smith
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Patent number: 7936200Abstract: A clock circuit which may include a first clock input for receiving a first clock signal and a second clock input for receiving a second clock signal. A clock calibration unit is connected to the first clock input and the second clock input. The calibration unit may calibrate the second clock signal relative to the first clock signal. The clock calibration unit may have a calibration output for outputting a calibrated clock signal. The clock circuit may include a switch unit connected to the first clock input and the calibration output. The switch unit can select a selected clock signal selected from the first clock signal and the calibrated signal. The switch unit has a switch output for outputting the selected clock signal. A switch control unit is connected to the switch unit for controlling which signal is selected based on a selection criterion and a clock circuit output is connected to the switch unit for outputting the selected clock signal.Type: GrantFiled: January 8, 2007Date of Patent: May 3, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Kamel Abouda, Laurent Guillot
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Patent number: 7928786Abstract: A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.Type: GrantFiled: January 14, 2010Date of Patent: April 19, 2011Assignee: Hynix Semiconductor Inc.Inventor: Kwang Jun Cho
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Patent number: 7928773Abstract: Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections.Type: GrantFiled: July 9, 2008Date of Patent: April 19, 2011Assignee: Integrated Device Technology, IncInventors: Yi Li, Ji Fu Chi
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Patent number: 7902899Abstract: An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.Type: GrantFiled: June 22, 2010Date of Patent: March 8, 2011Assignee: Hynix Semiconductor Inc.Inventor: Nam-Pyo Hong
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Publication number: 20110025284Abstract: A multi-phase DC-DC converter is disclosed. The DC-DC converter has a plurality of phases, each with a separate PWM generator for driving a totem pole of transistors. A master PWM generator operates off of a master clock signal. The remainder of the phases are slaved to the master PWM generator.Type: ApplicationFiled: August 3, 2010Publication date: February 3, 2011Inventors: Peng Xu, Jian Jiang, Jinghai Zhou
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Patent number: 7876144Abstract: A start-up circuit receives a start-up signal instructing start-up of an equipment mounted with the circuit, and executes a predetermined sequence when start-up is instructed by the start-up signal. An oscillator generates a clock signal. A sequence circuit receives the start-up signal and a clock signal output from the oscillator, measures time by counting the clock signal when the start-up signal transits to a predetermined level, and executes a predetermined event at a predetermined timing. The oscillator operates for a period where the start-up signal is at the predetermined level if the start-up signal is at the predetermined level during the period the power key of the equipment mounted with the circuit is being pushed.Type: GrantFiled: May 9, 2007Date of Patent: January 25, 2011Assignee: Rohm Co., Ltd.Inventors: Tetsuro Hashimoto, Akihito Ito, Yoshikazu Sasaki, Isao Yamamoto
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Publication number: 20100308884Abstract: A clock receiver in a semiconductor integrated circuit includes a first clock buffer configured to buffer an external clock to generate a low frequency buffered clock in response to a first operation signal; a second clock buffer configured to buffer the external clock to generate a high frequency buffered clock in response to a second operation signal; and an internal clock generating unit configured to receive the low frequency buffered clock and the high frequency buffered clock, to control states of the first operation signal and the second operation signal and to generate an internal clock.Type: ApplicationFiled: December 23, 2009Publication date: December 9, 2010Applicant: Hynix Semiconductor Inc.Inventors: Won Joo Yun, Hyun Woo Lee, Ki Han KIM
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Patent number: 7816952Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.Type: GrantFiled: August 1, 2008Date of Patent: October 19, 2010Assignee: Panasonic CorporationInventors: Shinichi Hashimoto, Tadahiro Yoshida, Ryogo Yanagisawa
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Patent number: 7808272Abstract: An integrated circuit for analyzing the waveform of an input signal includes a first storage circuit and a second storage circuit that are each supplied with the input signal. The first and second storage circuits are controlled by a clock signal. The first storage circuit is used to store a state for the input signal when the clock signal has a rising edge. The second storage circuit is used to store a state for the input signal when the clock signal has a falling edge. An evaluation circuit compares the states of the input signal that are stored in the first and second storage circuits during a selected time span. The comparison can be used to decide whether the input signal assumes periodic fluctuations or an approximately permanently static value during the time span.Type: GrantFiled: December 8, 2005Date of Patent: October 5, 2010Assignee: Qimonda AGInventors: Robert Kaiser, Florian Schamberger
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Patent number: 7808292Abstract: A wireless communication device is described having a transmitter that generates electromagnetic interference when operating in a transmit mode. The wireless communication device comprises a clock circuit including a first clock element configured to generate a first clock output, and a second clock element configured to generate a second clock output. Also included is a controller configured to switch between the first clock output and the second clock output when the transmitter is operating in the transmit mode.Type: GrantFiled: January 12, 2009Date of Patent: October 5, 2010Assignee: Research In Motion LimitedInventors: Mark A. J. Carragher, John W. Wynen
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Patent number: 7800424Abstract: An apparatus for supplying an overdriving signal in a memory apparatus. The apparatus includes: a voltage detecting block that outputs a plurality of detection signals according to the level of an external voltage, and a pulse generator that outputs the overdriving signals having different pulse widths according to the plurality of detection signals.Type: GrantFiled: December 17, 2007Date of Patent: September 21, 2010Assignee: Hynix Semiconductor Inc.Inventor: Sang Jin Byeon
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Patent number: 7791392Abstract: An apparatus for generating a pulse which generates an internal signal. The apparatus includes a latch circuit latching an input signal to output a first signal. A clock period detector detects a period of an external clock signal to output a period detecting signal and a delay controller adjusts a delay time of the first signal to output a second signal in response to the period detecting signal. A signal generator receives the first signal and the second signal to output a pulse signal.Type: GrantFiled: December 28, 2006Date of Patent: September 7, 2010Assignee: Hynix Semiconductor Inc.Inventor: Young-Hoon Oh
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Patent number: 7768333Abstract: An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.Type: GrantFiled: June 26, 2007Date of Patent: August 3, 2010Assignee: Hynix Semiconductor Inc.Inventor: Nam-Pyo Hong
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Publication number: 20100188129Abstract: Various apparatuses and methods for offsetting the phase and/or frequency of a clock signal are disclosed herein. For example, some embodiments provide an apparatus for generating a clock signal, including a quadrature delay circuit connected to an input clock signal. The quadrature delay circuit outputs components of the input clock signal with different phase shifts. A first amplitude modulator is connected to the first output of the quadrature delay circuit, and a second amplitude modulator is connected to the second output of the quadrature delay circuit. A summer combines the output of the first and second amplitude modulators.Type: ApplicationFiled: January 28, 2009Publication date: July 29, 2010Inventor: Stanley Jeh-Chun Ma
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Publication number: 20100182065Abstract: The present invention relates to a multi-phase ultra-wideband signal generator using differential pulse oscillators and an array thereof. The multi-phase ultra-wideband signal generator using differential pulse oscillators and an array thereof includes N pulse oscillators for generating pulse signals based on supply of power. The multi-phase ultra-wideband signal generator further comprises N inverting amplification units for outputting inverted amplified signals of output signals of the N pulse oscillators when a number of pulse oscillators is at least two, wherein, when the number of pulse oscillators is an even or odd number, the pulse oscillators are arrayed such that they have a connection form in which output terminals OUT(+) and OUT(?) of a relevant pulse oscillator are connected to output terminals OUT(+) and OUT(?) of a next pulse oscillator through a relevant inverting amplification unit, and the connection form is consecutively applied to the pulse oscillators.Type: ApplicationFiled: January 13, 2010Publication date: July 22, 2010Inventors: Seong Cheol Hong, Sang Hoon Sim
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Patent number: 7755409Abstract: A clock signal generator including: a signal generation unit that outputs a first clock signal composed of a single frequency component; and a phase angle detection unit that detects phase angles of the first clock signal by comparing a plurality of threshold values set within the amplitude of the first clock signal with instantaneous values of the first clock signal by using window comparators, and generates a second clock signal by determining rising and/or falling edges of the signal according to the detected phase angles.Type: GrantFiled: December 13, 2007Date of Patent: July 13, 2010Assignee: Seiko Epson CorporationInventor: Kesatoshi Takeuchi
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Patent number: 7750713Abstract: A spread spectrum clock generator for sequentially modulating a source clock of a fixed frequency with a predetermined frequency range, including: a plurality of first loading units configured to delay clock edges of the source clock by a delay time corresponding to the number of unit delay steps determined by delay step control signals, wherein each of the first loading units comprises a plurality of second loading units each of which is configured to vary a delay value of each unit delay step by changing an inner interconnection configuration thereof in response to unit delay step control signals.Type: GrantFiled: December 26, 2007Date of Patent: July 6, 2010Assignee: Hynix Semiconductor Inc.Inventor: Young-Hoon Oh
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Patent number: 7746144Abstract: The pulse generator comprises: a delay line arranged to receive a digital input signal and to produce a plurality of delay line output signals; first and second pulse generator blocks comprising logic circuitry arranged to generate a plurality of successive first output pulses in response to said different delay line output signals; and pulse combiner circuitry arranged to combine said first output pulses to produce second output pulses. The first pulse generator block is arranged to be responsive to rising edges of said input signal, and the second pulse generator blocks is responsive to falling edges of said input signal. Thus, both rising and falling edges of said input signal are used to create pulses. The device can be used in impulse radio transmitters and receivers.Type: GrantFiled: March 5, 2007Date of Patent: June 29, 2010Assignee: Seiko Epson CorporationInventors: Jose Luis Gonzalez Jimenez, Diego Mateo Pena, Enrique Barajas Ojeda, Ignasi Cairo, Masayuki Ikeda
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Patent number: 7746143Abstract: An object is to provide a clock generating circuit that can suppress variation of an oscillation frequency from the clock generating circuit, which is due to a change in the output voltage according to a discharging characteristic of the battery, and effectively utilize the remaining power of the battery. A structure includes an output voltage detecting circuit for detecting an output voltage from a battery; a frequency-division number determining circuit for determining the number of frequency-division by a value of the output voltage detected by the output voltage detecting circuit; an oscillation circuit for outputting a reference clock signal depending on the output voltage; a counter circuit for counting a number of waves of the reference clock signal that depends on the number of frequency-division; and a frequency-dividing circuit that frequency-divides the reference clock signal depending on the number of waves counted by the counter circuit.Type: GrantFiled: November 19, 2007Date of Patent: June 29, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventor: Masami Endo
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Patent number: 7737752Abstract: A clock generator (622) includes a first circuit (812) and a second circuit (814). The first circuit (812) includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to receive a second clock signal at the first frequency, and an output. The second clock signal is out-of-phase with the first clock signal. The second circuit (814) is coupled to the first circuit (812) and includes a mode signal input configured to receive a mode signal. The output of the first circuit (812) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.Type: GrantFiled: May 17, 2007Date of Patent: June 15, 2010Inventors: Craig Eaton, Daniel W. Bailey
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Publication number: 20100109737Abstract: A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator.Type: ApplicationFiled: December 29, 2009Publication date: May 6, 2010Inventor: Hun Sam Jung
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Publication number: 20100052761Abstract: A dual power source pulse generator in power connection with a pair of electrodes having a first electrode, a second electrode and an air gap therebetween. The dual power source pulse generator includes a first pulse source producing a high voltage low current pulse across the pair of electrodes to allow dielectric breakdown, and a second pulse source electrically connected in parallel with an output of the first pulse source, and producing a low voltage high current pulse to thereby produce a current flow of high-density plasma between the same electrodes of the pair of electrodes in response to the high voltage low current pulse.Type: ApplicationFiled: September 3, 2008Publication date: March 4, 2010Applicant: General Electric CompanyInventors: George William Roscoe, John James Dougherty, Cecil Rivers, JR., Thangavelu Asokan, Adnan Kutubuddin Bohori
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Patent number: 7667516Abstract: A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator.Type: GrantFiled: December 27, 2007Date of Patent: February 23, 2010Assignee: Hynix Semiconductor Inc.Inventor: Hun Sam Jung
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Patent number: 7659763Abstract: A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.Type: GrantFiled: March 4, 2008Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Hibourahima Camara, Sergey V. Rylov
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Patent number: 7642822Abstract: Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop arrangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth).Type: GrantFiled: April 3, 2008Date of Patent: January 5, 2010Assignee: Tektronix, Inc.Inventors: Daniel G. Baker, Gilbert A. Hoffman, Michael S. Overton, Barry A. McKibben
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Patent number: 7639058Abstract: The semiconductor device is provided with a clock signal generation circuit that includes a reference clock signal generation circuit which generates a first reference clock signal, a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal, a second counter circuit which counts the number of rising edges of the first reference clock signal by using an enumerated value of the first counter circuit, a first divider circuit which divides a frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides a frequency of the second reference clock signal and generates a clock signal.Type: GrantFiled: January 29, 2008Date of Patent: December 29, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Masami Endo, Hiroki Dembo, Daisuke Kawae, Takayuki Inoue, Munehiro Kozuma
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Patent number: 7629829Abstract: Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter receiving the first signal and outputting a third clock signal, a duty detection unit receiving the third and fourth clock signals to detect a difference between duty cycles of the third and fourth clock signals, a combination unit for outputting a second signal, a shift register for outputting a first control signal, a phase detection unit receiving the first and second clock signals and outputting a second control signal representing a difference between duty cycles of the first and second clock signals. The mixer adjusts a mixing ratio by using the first and second control signals.Type: GrantFiled: August 13, 2007Date of Patent: December 8, 2009Assignee: Hynix Semiconductor Inc.Inventor: Hyun Woo Lee
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Patent number: 7612597Abstract: An electronic circuit for performing clock gating on a clock signal supplied to a clock system using both edges, has a non-inverted/inverted signal selector which has an input connected to an input terminal, is fed with the clock signal through the input terminal, and outputs a first signal obtained by non-inverting or inverting the clock signal in response to a control signal; a signal latch which has an input connected to an output of the non-inverted/inverted signal selector, outputs the inputted first signal as a second signal through an output terminal, and latches a state of the second signal in response to an enable signal inputted through an enable terminal; and an input/output comparator which compares the clock signal and the second signal and outputs the control signal to the non-inverted/inverted signal selector such that the first signal agrees with the second signal.Type: GrantFiled: August 30, 2007Date of Patent: November 3, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Shuuji Matsumoto
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Patent number: 7598790Abstract: A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output signals represents a different phase of a periodic waveform signal. The extraction circuit extracts a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits. The clock signal generation circuit converts the most significant bits into a serial bit stream that serves as an output clock signal.Type: GrantFiled: January 30, 2008Date of Patent: October 6, 2009Assignee: Altera CorporationInventors: Benjamin Esposito, Hong Shan Neoh
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Patent number: 7573312Abstract: A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the external clock elapses and outputs a period determination signal. A frequency selector selectively transmits the external clock or the high-frequency external clock to a clock input buffer under the control of a power-up signal and the period determination signal.Type: GrantFiled: July 17, 2007Date of Patent: August 11, 2009Assignee: Hynix Semiconductor Inc.Inventor: Seong Jun Lee
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Patent number: 7521979Abstract: A ternary pulse generation circuit includes a logic circuit section including three logic elements and a switching control section including three switching elements each controlled by an output of corresponding one of the three logic elements, and the circuit outputs three different voltage values in a switching manner by controlling the three switching elements such that the three switching elements are not turned on simultaneously.Type: GrantFiled: October 19, 2006Date of Patent: April 21, 2009Assignee: Sanyo Electric Co., Ltd.Inventor: Takashi Tanimoto
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Publication number: 20090072876Abstract: There is provided an ultra-wide band pulse signal generator that can vary a waveform and bandwidth of a pulse signal by delaying transmitted data according to a clock signal without using a delay line to generate the pulse signal. An ultra-wide band pulse signal generator according to an aspect of the invention may include: a signal generating unit sequentially delaying transmitted data according to a predetermined clock signal to generate a plurality of pulse signals; an amplification unit amplifying the plurality of pulse signals from the signal generating unit according to predetermined amplification ratios; and a combination unit combining the plurality of pulse signals amplified by the amplification unit.Type: ApplicationFiled: September 12, 2008Publication date: March 19, 2009Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Yu Sin KIM, Chang Seok Lee, Kwang Du Lee, Chang Soo Yang
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Patent number: 7501872Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.Type: GrantFiled: October 12, 2007Date of Patent: March 10, 2009Assignee: Actel CorporationInventors: Shin-Nan Sun, Limin Zhu, Theodore Speers, Gregory Bakker
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Patent number: 7489177Abstract: A wireless communication device is described having a transmitter that generates electromagnetic interference when operating in a transmit mode. The wireleess communication device comprises a clock circuit including a first clock element configured to generate a first clock output, and a second clock element configured to generat a second clock output. Also included is a controller configured to switch between the first clock output and the second clock output when the transmitter is operating in the transmit mode.Type: GrantFiled: June 5, 2006Date of Patent: February 10, 2009Assignee: Research In Motion LimitedInventors: Mark A. J. Carragher, John W. Wynen
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Patent number: 7456674Abstract: Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, differences in delay time, referred to as skew, are minimized. An embodiment of the clock generation circuit incorporates a waveform generator and a timing-improved deskewer. The waveform generator is clocked by a clock-in signal. The deskewer comprises a flip-flop, a level-sensitive latch, and a multiplexer. The flip-flop and latch are connected in parallel and each receives waveform signals from the waveform generator as well as the clock-in signal in order to generate output signals. The multiplexer gates the flip-flop and latch output signals with the clock-in signal in order to generate the clock-out signal. A testable deskewer for edge-sensitive multiplexer scan designs is also disclosed.Type: GrantFiled: February 7, 2008Date of Patent: November 25, 2008Assignee: International Business Machines CorporationInventor: Steven F. Oakland
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Patent number: 7456675Abstract: A disclosed semiconductor integrated circuit device includes a selection circuit that is supplied with a first clock signal and a second clock signal, a selection signal, and a switching signal, and configured to select one of the first clock signal and the second clock signal according to the selection signal and to change the selected one of the first clock signal and the second clock signal to the other one of the first clock signal and the second clock signal according to the switching signal. The disclosed semiconductor integrated circuit device also includes an output fixing circuit configured to generate a pulse that is maintained at a high level or a low level during a certain period, to perform an OR operation on the output signal from the selection circuit and the generated pulse, and to output a result of the OR operation as the output clock signal.Type: GrantFiled: February 12, 2007Date of Patent: November 25, 2008Assignee: Mitsumi Electric Co., Ltd.Inventor: Makio Abe
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Patent number: 7446588Abstract: In a first aspect, a first method is provided that includes providing a plurality of select signals and a plurality of input signals for input by a multiplexer. Each select signal is adapted to cause the multiplexer to select a different one of the plurality of input signals for output by the multiplexer when the select signal is in a first logic state. The first method further includes preventing a first of the select signals that is in the first logic state from being provided to the multiplexer until the other select signals are in a second logic state. Number other aspects are provided.Type: GrantFiled: December 11, 2003Date of Patent: November 4, 2008Assignee: International Business Machines CorporationInventors: David W. Boerstler, Eskinder Hailu, H. Peter Hofstee
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Patent number: 7446587Abstract: The invention provides a semiconductor device which can suppress a variation of clock signals. According to the invention, a single clock signal is divided into a plurality of clock signals and supplied to each of a plurality of circuits in a semiconductor device. Propagation delay time of each of the clock signals is not completely fixed in a design phase, but a circuit (variable delay circuit) which can appropriately change propagation delay time of a clock signal even after forming the semiconductor device is provided. By using the variable delay circuit, a variation in the propagation delay time is compensated so that a circuit provided in a subsequent stage of the variable delay circuit can operate normally on a desired condition. In specific, a phase of each clock signal is controlled.Type: GrantFiled: July 28, 2004Date of Patent: November 4, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kiyoshi Kato
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Patent number: 7433430Abstract: A wireless communications device may include a wireless receiver receiving signals having alternating known and unknown symbol portions over a channel, and a demodulator systolic array. The demodulator systolic array may include a channel estimation module generating respective channel estimates for each unknown symbol portion based upon the known symbol portions. An autocorrelation module may generate autocorrelation matrices based upon the channel estimates. A channel match filter module may generate respective channel matching coefficients for the unknown symbol portions, and a factorization module may divide the autocorrelation matrices into respective upper and lower autocorrelation matrices. A transformation module may transform the channel matching coefficients into upper and lower channel matching coefficients.Type: GrantFiled: February 9, 2005Date of Patent: October 7, 2008Assignee: Harris CorporationInventors: Michael Andrew Wadsworth, John Wesley Nieto
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Patent number: 7433392Abstract: A wireless communications device may include a wireless receiver for receiving signals comprising alternating known and unknown symbol portions, and a demodulator connected thereto. The demodulator may include a channel estimation module for generating respective channel estimates for a prior unknown symbol portion(s), current unknown symbol portion and for future unknown symbol portion(s). An autocorrelation module may generate autocorrelation matrices for the prior, current and future unknown symbol portions. A channel match filter module may generate respective channel matching coefficients for the prior and current/future unknown symbol portions, and a factorization module may divide the autocorrelation matrices into respective upper and lower autocorrelation matrices. A transformation module may transform the channel matching coefficients into upper and lower channel matching coefficients.Type: GrantFiled: February 9, 2005Date of Patent: October 7, 2008Assignee: Harris CorporationInventors: John Wesley Nieto, Michael Andrew Wadsworth
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Patent number: 7427879Abstract: The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock for extracting a period of the input clock to generate a pulse, and the digital signal generator is coupled to the pulse generator for converting the pulse into a plurality of logic values. The digital signal generator includes: a delay module coupled to the pulse, for delaying the pulse to generate a plurality of delayed pulses according to a plurality of delay amounts, respectively; and a sampling module coupled to the delay module for sampling the pulse to generate the logic values according to the delayed pulses, respectively. The decoder is coupled to the digital signal generator for determining the frequency of the input clock according to the logic values.Type: GrantFiled: November 22, 2006Date of Patent: September 23, 2008Assignee: Nanya Technology Corp.Inventor: Wen-Chang Cheng
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Patent number: 7423459Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.Type: GrantFiled: November 13, 2006Date of Patent: September 9, 2008Assignee: Matsushita Electric Indutrial Co., Ltd.Inventors: Shinichi Hashimoto, Tadahiro Yoshida, Ryogo Yanagisawa
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Publication number: 20080205559Abstract: A template pulse generating circuit that generates a template pulse used for detection of a received pulse in pulse communication includes an output mode switching circuit for switching an output mode in accordance with a supplied control signal between a continuous output mode that continuously outputs the template pulses and an intermittent output mode that intermittently outputs the template pulses so that the template pulse is generated in either one of the continuous output mode and the intermittent output mode.Type: ApplicationFiled: February 27, 2008Publication date: August 28, 2008Applicant: SEIKO EPSON CORPORATIONInventor: Izumi IIDA