Abstract: A circuit arrangement for delaying a useful signal which is stored in the form of time-discrete signal samples in a row of storage devices at time intervals which are determined by a clock signal and is read therefrom after expiration of a selectable delay time. Each storage device is connectable, via a respective input circuit to a useful signal input and, via a respective output circuit, to a useful signal output.

Abstract: In an address transition detection summing circuit, the varying address signal pulse widths can result in output signals from the address transition detection summing circuit which can compromise the performance of the associated memory circuitry. A parallel signal delay path, activated by the leading edge of the address signal, is incorporated in the address transition detection summing circuit and a logic ANDing element so that not only is the signal resulting from the trailing edge of the address signal applied to the logic ANDing element, but the trailing edge signal from the parallel signal delay path must be applied to the logic ANDing element before the trailing edge of the output pulse from the address transition detection summing circuit is generated. In the manner, an address transition always results in an output signal pulse having a preselected minimum width.

Abstract: A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.

Abstract: A waveform formatter for use in testing a semiconductor device is capable of reducing a total size of circuit configuration. The waveform formatter includes a plurality of clock generators in which at low-speed operation, clocks are used to generate waveforms and control signals of drivers, while at high-speed operation, all clocks are used to generate waveforms for drivers. The waveform formatter further includes a parallel-serial converter for converting parallel signals to a serial signal, a data selector for selecting the parallel signals or the serial signal, and a waveform combining circuit for accepting output signals of the clock generators through a format control unit and for generating waveforms and control signals for the drivers using the clocks from the clock generators.

Abstract: A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. An external command signal may be provided to the microprocessor to initiate a test operation in which the variable delay units are tested for possible defects. During the test operation, a control unit selects the multiplexers such that the four delay units are electrically separated from one another. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time.

Abstract: In input transition detection pulse generators used in semiconductor memory devices, etc., in order to permit a designer to arbitrarily design the power supply voltage dependency of an output pulse width in accordance with use, a scheme is employed such that the functional block for detecting transition of an input or inputs to generate a pulse signal or signals, or the functional block for setting the width of each pulse signal is caused to have a function to generate pulse signals having different power supply voltage dependencies of pulse widths to perform a predetermined logical operation by a logical operation unit on the basis of pulse signals from the input transition detection pulse generation block or the pulse width setting block, thus to output a pulse having a pulse width optimum for a power supply voltage used.

Abstract: A pulse shaping circuit of the clock stretcher/chopper type which is sufficiently simplified to be included on an integrated circuit chip with other circuits without significantly reducing the chip area on which such other circuits may be formed achieves a fast recovery time by developing differential delays in response to each of two different characteristics of a signal input to a delay line. Pulse stretching is accomplished by a latch circuit and pulse chopping is accomplished by a delay arrangement which controls the latching action and the output signal. The delay arrangement may also be made programmable. By controlling the latching and the output signal in response to the delay line, a wide range of duty cycles of input and output signals may be accommodated, even at extremely high frequencies.

Abstract: A programmable clock divider in which a system reference clock signal is divided by a programmed integer value. A storage register stores a value equal to the desired divisor minus two. A stored value of zero results in a divide by two. The stored value is loaded into a compare register and a counter is implemented to count reference clock signals. The compare register value and the counter value are compared by a comparator logic circuit. When the two values are equal, a flip-flop is toggled to switch the prescale clock value output. The flip-flop control logic includes circuitry for ensuring that odd divides exhibit an output clock frequency having a 50/50 duty cycle by controlling the flip-flop toggle to coincide with system clock edges. The flip-flop control logic also controls the timing for loading and resetting the compare and counter logic, respectively.

Abstract: A plurality of clock signals, which determine the edge timing of a driver output waveform, are generated by a timing generator. Pattern data and control data synchronized therewith from selecting a waveform mode in real time are generated by a patter generator. An enable data generator generates enable data which determines whether to use A, B and C clock signals ACK, BCK and CCK which determine the edge timing of the driver output waveform, on the basis of a selected one of a plurality of waveform modes stored in a storage and the pattern data. A waveform generator generates the driver output waveform on the basis of the enable data and the A, B, and C clock signals which determine the edge timing of the driver output waveform.

Abstract: A pulse generator circuit 20 is disclosed herein. An asymmetric delay element 22 is coupled to one of the inputs of a logic element 24, such as a NAND gate. For the asymmetric delay 22, the time to propagate a transition from a high level to a low level is different then the time to propagate a transition from a low level to a high level. The input of the asymmetric delay element 22 is coupled to another of the inputs of the logic gate 24. The pulse generator circuit 20 of the present invention generates a pulse at its output OUT when a signal applied to its input IN transitions from a first signal level to a second signal level.