Abstract: Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then transmits the UP or DOWN control signal to edge adjusting circuits connected to each strobe and data stream between the flip flop and pre-driver. The edge adjusting then adds a delay to each respective strobe and data stream which incrementally compensates for the mismatch created by PVT variations. The process is repeated until the high and low data outputs are effectively matched, thereby maximizing the data eye.

Abstract: A method for generating a pulse train is provided with adjustable start and end times of individual pulses, in which additional clock signals are generated from a 0th clock signal, the signals which in each case have a frequency of the 0th clock signal and whose phase is shifted in each case relative to a phase of the 0th clock signal. Pairs of one first clock signal and one second clock signal are provided, partial pulses are generated from the properties of the first and second clock signal of a pair in accordance with a timing vector, and the pulse train is generated by superimposition of partial pulses.

Abstract: A pulse generating circuit and related method, for producing extremely narrow pulses for use in monolithic microwave integrated circuits (MMICs) for radar, high-speed sampling, pulse radio and other applications. A sinusoidal input signal is supplied to two nonlinear shock wave generators, which are oppositely biased to produce periodic outputs that are mirror images of each other, one with a very steep rising edge and one with a very steep falling edge. The combined outputs would cancel each other completely but for the introduction of a slight time delay in one of them, which results in a narrow peak in the combined signals.

Abstract: A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to be a second level and to output the clock as a composite clock for clock switching, for a specified period including one of a leading edge and a trailing edge of the clock as well as additional time before and after the edge, when the signal becomes active while the clock is at a first level; a switching demand signal generation circuit that receives the clock and the signal, and outputs a clock switching demand signal; a clock selection signal generation circuit that changes a level of a first clock selection signal when the signal becomes active; and a first selector that selects one of the clock and the clock, according to the level of the signal, and outputs the selected clock.

Abstract: A clock switching device capable of automatic switching to a clock distribution system for back-up without interrupting processing of the device, which includes an abnormality detection unit which detects lack of coincidence in a logical level between a current clock pulse and a one-cycle preceding clock pulse as abnormality in a waveform on the basis of a plurality of cock pulses, a phase adjustment unit for switching which adjusts a phase of other clock pulse to a phase of a clock pulse being output, and a switching unit which switches to and outputs other clock pulse whose phase is adjusted by the phase adjustment unit for switching based on detection of lack of coincidence in a logical level by said abnormality detection unit.

Abstract: A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A clock signal is inverted by an input buffer and applied to a NAND gate together with a mask signal. When the signal from the NAND gate rises, the signal of the second integrating portion falls after a delay time due to the integration circuit. The signal from the NAND gate is applied together with the signal from the second integrating portion to a second NAND gate, and the signal from the second NAND gate is fixed at “L” during the period from the time of the rise of the clock signal for the duration of the delay time of the integration circuit. The signal from the second NAND gate is delayed by a third integrating portion and a delay time of the third integrating portion is added by an AND gate to generate a mask signal.

Abstract: A remote voltage regulator module (VRM) for high-current, low voltage applications. In one embodiment, an electronic system includes a VRM configured to provide a DC output voltage. The VRM is coupled to a load board via a first bus bar and a second bus bar. The VRM includes a first capacitance of a first amount, while the load board includes a second capacitance of a second amount. A loop between the VRM and the load board is formed by the first and second bus bars and first and second capacitances. The loop is characterized by a transfer function that is second order or less.

Abstract: A multiple mode clock receiver including first and second input AC-coupled capacitors, first and second voltage dividers and a differential amplifier. The voltage dividers each include first and second junctions, respectively, coupled to the first and second AC-coupled capacitors, respectively. The differential amplifier has first and second inputs coupled to the first and second junctions, respectively, and an output providing an output clock signal that is aligned with an input clock signal provided through the AC-coupled capacitors. The multiple mode clock receiver is a single circuit that aligns the output clock signal to any one of multiple forms of input clock signals, including a sole single-ended clock signal, a single-ended clock signal with a corresponding reference signal, and a differential clock signal.

Abstract: An integrated semiconductor memory includes a clock generator circuit driven by an external clock signal and a control circuit driven by the external clock signal. The clock generator circuit generates an internal clock signal with a first level if the external clock signal level lies above a sensitivity level of the clock generator circuit for at least the duration of a sensitivity time of the clock generator circuit, and generates the internal clock signal with a second level if the external clock signal level lies below the sensitivity level for at least the duration of the sensitivity time of the clock generator circuit. The control circuit controls the clock generator circuit such that the control circuit selects the sensitivity time of the clock generator circuit in response to characteristics of the external clock signal.

Abstract: A level shift circuit for shifting levels of a pair of binary input signals having a first voltage range to produce a pair of binary output signals having a second voltage range includes a first circuit to shift a level of a first one of the binary input signals thereby to produce a first signal having the second voltage range, a second circuit to shift a level of a second one of the binary input signals thereby to produce a second signal having the second voltage range, and a timing adjustment circuit to produce the binary output signals by adjusting a pulse width thereof in response to the first and second signals such that the pulse width is equal to a time interval from when one of the first and second circuits stops level shift operation to when another one of the first and second circuits stops level shift operation.

Abstract: A pulse generator electrical circuit capable of operating as both a clock-based pulse generator and a delay-based pulse generator while minimizing the limitations of these two types of pulse generators is disclosed. When the pulse generator operates in “delay mode,” the smallest output pulse width possible corresponds to the minimum set point delay between the two delay circuits. The largest possible output pulse width corresponds to the difference between the maximum and minimum of the delay circuits. When the pulse generator operates in “clock mode,” the output of one of the delay circuits is blocked so that the output of the gate depends solely on the output of other delay circuit. This limits the lower pulse width interval to that of the retimer clock, but allows for an arbitrarily long (wide) pulse.

Abstract: A method and apparatus for controlling a voltage generator of a memory device are provided. In one embodiment, a first clock signal and a second clock signal are provided. The voltage generator is selectively enabled in conjunction with the first clock signal when a period of the first clock signal is less than a period of the second clock signal and the voltage generator is selectively enabled in conjunction with the second clock signal when the period of the second clock signal is less than the period of the first clock signal.

Abstract: Clock sources are provided which are especially useful for reducing phase noise in signal samplers that typically provide samples of an analog input signal in signal-conditioning systems such as analog-to-digital converters. This phase noise reduction is realized with the recognition that sampler noise is related to clock jitter by a ratio of the input signal's slew rate to the clock's slew rate. Clock embodiments include a frequency divider and a signal gate. The divider divides a first signal to provide a second signal with a slew rate lowered from the slew rate of the first signal and the gate passes the second signal when commanded by the first signal to thereby generate a clock signal.

Abstract: A redundant-source clock generator has only two oscillators, rather than three oscillators. A secondary oscillator is phase-locked to a primary clock from a primary oscillator using a phase detector, charge pump, and filter that generate a control voltage to the secondary oscillator that determine the frequency of a secondary clock. The primary clock is compared to the secondary clock to detect primary clock failure. When clock failure is detected, a mux is switched to select a delayed secondary clock rather than a delayed primary clock to output as a system clock. Since the mux receives delayed clock signals, clock-failure detection has additional time to detect the clock failure before the clock failure is propagated through the mux. When the primary oscillator fails and the clock failure is detected, the phase detector stops comparing a feedback secondary clock to the primary clock and instead holds the control voltage steady.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: A stop and release circuit of a sync signal, to temporarily suspend or interrupt the sync signal, the input sync signal having a plurality of leading edges and a plurality of trailing edges, the circuit including a first divider that receives the input sync signal and supplies a first signal made up of the sync signal divided by two starting from a leading edge, a second divider that receives the inverse input sync signal and supplies a second signal made up of the sync signal divided by two starting from a trailing edge, an exclusive OR circuit that receives the first signal and the second signal and that supplies an output sync signal, a stop circuit for the first divider and the second divider, and an asynchronous command signal generated by the stop circuit for the temporary interruption of the output sync signal.

Abstract: An output clock is provided by a logic module and at least one flip-flop based on a reference clock. Each flip-flop receives the reference clock at a corresponding clock end and changes a signal level outputted at a corresponding output port according to rising or falling edges within each period of the reference clock. The logic module performs a logic operation among signals at each output port of the flip-flops to generate the output clock synchronized with the reference clock. Thereafter the output clock can be outputted through the data path provided by the logic module, and additional logical operations can be performed between the output clock and other signals.

Abstract: There is provided a pulse generator capable of generating a pulse with a reduced number of transistors that toggle in response to a clock signal, thereby reducing power consumption. The pulse generator includes a plurality of unit cells, wherein an nth unit cell (n is a natural number more than 2) generates a pulse in response to a divided-by-N clock signal (N is a natural number), a signal output from an (n?1)th unit cell and a signal output from an (n+1 )th unit cell. The nth unit cell is reset or generates the pulse whose width is equivalent to the width of the clock signal, according to the logic level of the signal output from the n+1th unit cell.

Abstract: A clock circuit comprises an analog clock element, a digital clock element, and a controller. The analog clock element is configured to generate an oscillating output. The digital clock element is configured to generate a digital clock output. The controller is configured to switch between the analog clock element and the digital clock element. The oscillating output and the digital clock output have substantially equivalent frequencies.

Abstract: A gated clock circuit outputs a gated clock signal in response to a master clock signal and a control signal that has a rising or falling edge that follows a rising edge of the master clock signal by a delay. The gated clock signal has a pulse width that is equal to, and in phase with, the pulse width of a master clock signal, while at the same time substantially increasing the maximum value of the delay.

Abstract: A synchronized optical clocking signal is provided to a plurality of optical receivers by providing a layer of a high absorption coefficient material, such as SiGe or Ge, on a front surface of a low absorption coefficient substrate, such as silicon. Diodes are formed in the germanium containing layer for receiving an optical signal and converting the optical signal into an electrical signal. An optical clocking signal is shined on the back surface of the silicon substrate. The light has a wavelength long enough so that it penetrates through the silicon substrate to the germanium containing layer. The wavelength is short enough so that the light is absorbed in the germanium containing layer and converted to the electrical clocking signal used for neighboring devices and circuits. The germanium concentration is graded so that minority carriers are quickly swept across junctions of the diodes and collected.

Abstract: A method and circuit for regenerating clock signals. The method and circuit convert clock signals having either single- ended clock pulses or differential clock pulses into clock signals having substantially the same voltage swing. In one embodiment, the single-ended clock pulses are provided by a TTL logic circuit and the differential clock pulses are produced by a PECL logic circuit.

Abstract: Method and related apparatus for realizing frequency-multiplication by generating a high frequency signal according to a plurality of low frequency signals. The method includes: according to a plurality output signals generated by a phase-locked loop (PLL) or a delay-locked loop (DLL), generating a plurality of reference signals with a same frequency and different phases; when a number of the reference signals with signal level high is greater than a number of the reference signals with signal level low, making a signal level of the output signal remains a first level; otherwise, making the signal level of the output signal remains a second level substantially different from the first level. Thus the frequency of the output signals is a multiplication of the frequency of the input signals.

Abstract: A synchronous mirror delay (SMD)includes a model delay line that is coupled to a bi-directional delay line. In operation, an initial edge an input clock signal is applied through the model delay line to the bi-directional delay line. The SMD thereafter operates in a forward delay mode to alternately operate the bi-directional delay line in a forward mode and a backward mode to propagate the initial edge of the input clock signal through the bi-directional delay line and delay the initial edge of the input clock signal by a forward delay. In response to a subsequent edge of the input clock signal, the SMD mirrors the propagation of the input clock signal through the bi-directional delay line during the forward mode and further delay the initial edge of the input clock signal by a backward delay that is substantially equal to the forward delay.

Abstract: The present invention includes a system that has been developed to vary the starting and stopping of a pulse train of arbitrary phase without glitches, spurious pulses, or spurious change in duty cycle. This is accomplished by a system for generating a gated periodic waveform, the system includes a generator for generating a periodic waveform of adjustable phase; a device for providing a delayed enable signal based on the phase of the periodic waveform so that the gated periodic waveform can be started and stopped without creating undesirable changes in the gated periodic waveform; and a logic element for generating a gated periodic waveform based on the delayed enable signal and the periodic waveform of adjustable phase.

Abstract: A clock switching circuit has a clock output circuit and clock signal transfer circuits. The output circuit provides a selected clock signal. The transfer circuits receive input clock signals and select signals, and output transfer signals to the output circuit. Each of the transfer circuits includes a transmitting circuit, a generating circuit and a passing circuit. The transmitting circuit is connected to the output circuit, and receives the select signal and provides the received select signal responsive to the selected clock signal. The generating circuit is connected to the transmitting circuit, and provides an internal select signal responsive to the received select signal and the input clock signal. The passing circuit is connected to the generating circuit and the output circuit, and provides the input clock signal to the output circuit responsive to the internal select signal.

Abstract: A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first pre-stage delay circuit and a first post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the first bidirectional delay circuit string (BDDA), a second pre-stage delay circuit and a second post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the second bidirectional delay circuit string (BDDB), and a multiplexer, supplied with and multiplexing outputs of the first and second post-stage delay circuits to output the resulting signals. An output signal of the first delay circuit is supplied in common to the first and second pre-stage delay circuits.

Abstract: A phase locked loop that may use UP and/or DN signals having programmable active state durations to control the speed of a clock signal.

Abstract: A phase locked loop that may use UP and/or DN signals having programmable active state durations to control the speed of a clock signal.

Abstract: A clock generation apparatus includes a first clock generation circuit which generates a clock signal by making state transition in synchronization with a master clock signal after exiting from a predetermined state in response to a timing signal supplied from an exterior of the apparatus, a counter which counts clock pulses of the master clock signal after exiting from a reset state in response to the timing signal, and a reset circuit which resets the counter and sets the first clock generation circuit in the predetermined state in response to the count of the counter reaching a first predetermined value.

Abstract: A clock modulating circuit includes a first to nth delay circuits, a selection signal generator and a selection circuit. The first delay circuit receives an original clock signal and outputs a delayed clock signal. The second to nth delay circuits receive the delayed signal output from the preceding delay circuit and output delayed clock signals. The selection signal generator outputs a selection signal in response to the original clock signal. The selection signal has an instruction for selecting in ascending order from the first to nth delay circuits and then in descending order from the nth to first delay circuits. The selection circuit is connected to the first to nth delay circuits and the selection signal generator. The selection circuit receives the delayed signals from the first to nth delay circuits and outputs one of the delayed clock signals in response to the selection signal.

Abstract: An electronic device such as a processor receives a master clock signal from a system clock generator. The clock signal may be single-ended or differential. The disclosure presents methods and devices for automatically producing a clock signal that follows the master clock signal, regardless of whether the master clock signal is single-ended or differential.

Abstract: A timing vernier applies a pair of stable bias voltages to intermediate points of an impedance string to establish reliable and calibratable delay cell biases for a fine multiplexer. A coarse input multiplexer is switched to a new timing signal substantially immediately after passing a prior valid timing signal to maximize the time prior to each valid output that the waveform is independent of the prior delay pattern. Logic circuitry is provided for three different phase differential regimes between successive timing signals to ensure that invalid output signals separated by less than a clock period are not produced. Mask commands are inserted into a series of timing control commands to equalize the average rates of writing and reading out the timing control commands with the mask commands skipped at readout.

Abstract: A delayed signal generation circuit includes a first delay circuit having a plurality of delay elements connected in series and delaying a reference signal applied thereto, a second delay circuit having a plurality of delay elements connected in series each of which sends out an output signal which is delayed with respect to an input signal applied to the second delay circuit, a detector unit, responsive to the reference signal, for detecting a number of delay elements of the first delay circuit which output an output signal that is delayed with respect to the reference signal after a lapse of a predetermined time interval, and a selection unit for selecting one delay element from the second delay circuit according to the number of delay elements of the first delay circuit, and for outputting the output signal from the selected delay element as a delayed signal.

Abstract: Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.

Abstract: A method for driving a plurality of circuit units to be controlled includes applying a control signal to a control signal connection unit and an activation signal to an activation connection unit. A hold signal is the generated on the in response to the activation signal. This hold signal is combined with the control signal to obtain a modified control signal, which is then made available at an output.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) coupled to the first circuit via one or more path circuits and (ii) configured to present an output signal in response to the one or more first control signals. All of the one or more first control signals may have a preferred edge skew.

Abstract: Circuitry for a phase locked loop (PLL) includes a reference signal input and a frequency doubler. The output of the frequency doubler is a second reference signal having a frequency that is approximately twice that of the initial reference signal, and which is fed into the PLL. The frequency doubler includes a first delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The frequency doubler can include one or more additional delay circuits in series after the first delay circuit, the output of which is provided to a multiplexer. The multiplexer includes a selection signal input for selecting an output from at least one of the delay circuits to be provided to the XOR circuit. The frequency doubler allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter.

Abstract: A clock circuit comprises an analog clock element, a digital clock element, and a controller. The analog clock element is configured to generate an oscillating output. The digital clock element is configured to generate a digital clock output. The controller is configured to switch between the analog clock element and the digital clock element. The oscillating output and the digital clock output have substantially equivalent frequencies.

Abstract: An internal clock generating circuit of a semiconductor device includes: a delay chain having a plurality of delay units for generating multi-phase clocks by adjusting an input clock; a thermometer for outputting a thermometer code value in response to an input selection data; a multiplexer for selectively outputting one of a plurality of clocks input from the delay chain in response to the thermometer code value of the thermometer; and a pulse regenerator for outputting an adjusted internal clock by restoring a pulse form of the clock output from the multiplexer into its original state and controlling the delay thereof as much as desired.

Abstract: A low-jitter phase-locked loop (PLL) circuit includes a reference signal generator and a PLL. The reference signal generator is configured to quadruple a frequency of a first reference signal to produce a second reference signal. The PLL includes a filter coupled in series with a voltage controlled oscillator (VCO), and a frequency phase detector configured to generate a first error signal based on a frequency difference between the second reference signal and a first divided VCO output signal. The PLL further includes a phase detector configured to generate a second error signal based on a phase difference between the second reference signal and a second divided VCO output signal at each rising and falling transition of the second reference signal.

Abstract: A digital clock generator circuit with built-in frequency and duty cycle control may include a pulse generator for generating a start pulse. The pulse generator may be connected to a ring oscillator to generate multiple signals having a specified frequency and programmable duty cycles. The oscillator may further be connected to a multiplexer which selectively connects one output of the ring oscillator to a final output to produce a signal of the specified frequency and specified duty cycle. The duty cycle may be adjustable over a wide range and across the full frequency band of operation.

Abstract: A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.

Abstract: A clock selection circuit for selecting one of a plurality of clocks as an output clock. When the selection circuit switches between two of the plurality of clocks for output, the currently output clock is removed from the output. The removal of the currently output clock is performed synchronously to the currently selected clock. The newly selected clock is then coupled to the output. Coupling of the newly selected clock is performed synchronously to the newly selected clock.

Abstract: The invention relates to a circuit (100) with which one of a plurality of input clock signals (CLK_SRC1, . . . , CLK_SCR_n) can be selected and passed on to an output signal (CLK_OUT). The input clock signals are present at a multiplexer (MUX) which applies one of these signals in dependence upon the selection signal (CFG_i) from its control input to its output. The output signal (MUX_OUT) of the multiplexer is applied via a switch (S) and a signal latch (LATCH) to the output of the circuit as output signal (CLK_OUT). Switching between two input signals is controlled by a state machine (FSM) which first intransparently switches the signal latch (LATCH) after a change of the external configuration signal (CFG), then switches the multiplexer (MUX) and transparently switches the signal latch again after the multiplexer output (MUX_OUT) has changed at least once and assumed the value stored in the signal latch. The state machine (FSM) is supplied with its own fast clock (FCLK).

Abstract: A reset first latching mechanism comprises a pulse chopper circuit responsive to a pulsed signal to control initiation and termination of a reset pulse wherein a domino node is to be precharged in response to the reset pulse. The reset first latching mechanism also includes domino logic circuit responsive to an evaluate pulse at an input to evaluate at the domino node based on a logic function performed by the domino logic circuit. The reset pulse is timed such that the reset pulse is completed before the evaluate at the domino node occurs.

Abstract: A clock buffer circuit having a reduced propagation delay therethrough. The clock buffer circuit has a clock input for receiving an initial clock pulse thereto, and a clock output for transmitting a buffered clock pulse therethrough. A first driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from a low voltage level to a high voltage level. A second driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from the high voltage level to the low voltage level. A holder circuit and a first and trigger circuit for the second driver chain are also included.

Abstract: A synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal. The synchronized data capture circuit includes a timer generator having a first timer generator output. The timer generator is coupled to receive the first plurality of timing signals and to serially output on the first timer generator output, as a first high frequency timing pulse stream, first timing pulses responsive to timing pulses of the plurality of timing signals. The first high frequency timing pulse stream has a timing pulse stream frequency that is higher than a timing input frequency associated with one of the first plurality of timing signals. The synchronized data capture circuit also includes first plurality of data driver circuits coupled to receive the first plurality of data signals and the plurality of timing signals.

Abstract: A circuit comprising a clock generator and a state machine. The clock generator may be configured to generate an output clock signal in response to (i) a first enable signal and (ii) a second enable signal. The state machine may be configured to generate the second enable signal in response to a first and a second control signal.

Abstract: The present invention relates to a clock signal converting apparatus of a transmission system which is capable of coinciding synchronization of clock signals of a system by sharing signals of a first clock signal generator as a working unit and a second clock signal generator as a protection unit in common. In addition, the second clock signal generator can output system signals having same phase with the first clock signal generator by using output of the first clock signal as a reset signal of the counter of the second clock signal generator.